From 9a68db7220d05fb28de139a7db93bd6866cc86fa Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Thu, 26 Oct 2017 00:03:27 -0400 Subject: [PATCH 01/17] Revert "drm/amd/display: Match actual state during S3 resume." This reverts commit 4f346e655d24140fb40b46f814506ba17ac34ea1. fix s3 hang issue. Acked-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 ------------------- 1 file changed, 33 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d0ee1b3b8b5c8..bb134a6320bf8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -641,11 +641,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) struct drm_connector *connector; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; - struct dm_crtc_state *dm_crtc_state; - struct drm_plane *plane; - struct drm_plane_state *plane_state; - struct dm_plane_state *dm_plane_state; - struct dm_atomic_state *cached_state; int ret = 0; int i; @@ -684,34 +679,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) new_crtc_state->active_changed = true; - cached_state = to_dm_atomic_state(adev->dm.cached_state); - - /* - * During suspend, the cached state is saved before all streams are - * disabled. Refresh cached state to match actual current state before - * restoring it. - */ - WARN_ON(kref_read(&cached_state->context->refcount) > 1); - dc_release_state(cached_state->context); - - for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { - dm_crtc_state = to_dm_crtc_state(new_crtc_state); - if (dm_crtc_state->stream) { - WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1); - dc_stream_release(dm_crtc_state->stream); - dm_crtc_state->stream = NULL; - } - } - - for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) { - dm_plane_state = to_dm_plane_state(plane_state); - if (dm_plane_state->dc_state) { - WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1); - dc_plane_state_release(dm_plane_state->dc_state); - dm_plane_state->dc_state = NULL; - } - } - ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); drm_atomic_state_put(adev->dm.cached_state); From 3b21b6d239f43c0d797bf0deb8c0f8c846862eb1 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Tue, 17 Oct 2017 15:36:13 -0400 Subject: [PATCH 02/17] drm/amd/display: Fix no display on Fiji MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allocate memory for the second pipe allocate_mem_input() needs to be done prior to program pipe front end. It shows sensitive to Fiji. Failure to do so will cause error in allocate memory  allocate_mem_input() on the second connected display. Signed-off-by: Jerry Zuo Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../display/dc/dce110/dce110_hw_sequencer.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 2a6d3ca129543..399a5984ada3a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1370,16 +1370,6 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; - /* mst support - use total stream count */ - if (pipe_ctx->plane_res.mi != NULL) { - pipe_ctx->plane_res.mi->funcs->allocate_mem_input( - pipe_ctx->plane_res.mi, - stream->timing.h_total, - stream->timing.v_total, - stream->timing.pix_clk_khz, - context->stream_count); - } - pipe_ctx->stream->sink->link->psr_enabled = false; return DC_OK; @@ -2891,6 +2881,15 @@ static void dce110_apply_ctx_for_surface( if (pipe_ctx->stream != stream) continue; + /* Need to allocate mem before program front end for Fiji */ + if (pipe_ctx->plane_res.mi != NULL) + pipe_ctx->plane_res.mi->funcs->allocate_mem_input( + pipe_ctx->plane_res.mi, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, + pipe_ctx->stream->timing.pix_clk_khz, + context->stream_count); + dce110_program_front_end_for_pipe(dc, pipe_ctx); program_surface_visibility(dc, pipe_ctx); From 4d3e00dad80a2c317d542358620facd8ca698428 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 19 Oct 2017 22:34:15 +0530 Subject: [PATCH 03/17] drm/amd/display : add high part address calculation for underlay Currently the high part of the address structure is not populated in case of luma and chroma. This patch adds this calculation. Signed-off-by: Shirish S Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb134a6320bf8..635a8a3df3699 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1771,6 +1771,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, { uint64_t tiling_flags; uint64_t fb_location = 0; + uint64_t chroma_addr = 0; unsigned int awidth; const struct drm_framebuffer *fb = &amdgpu_fb->base; int ret = 0; @@ -1833,9 +1834,13 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(fb_location); + plane_state->address.video_progressive.luma_addr.high_part + = upper_32_bits(fb_location); + chroma_addr = fb_location + (u64)(awidth * fb->height); plane_state->address.video_progressive.chroma_addr.low_part - = lower_32_bits(fb_location) + - (awidth * fb->height); + = lower_32_bits(chroma_addr); + plane_state->address.video_progressive.chroma_addr.high_part + = upper_32_bits(chroma_addr); plane_state->plane_size.video.luma_size.x = 0; plane_state->plane_size.video.luma_size.y = 0; plane_state->plane_size.video.luma_size.width = awidth; From 56087b31f4b2861c773185ec45d313b55dbbb69d Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 26 Oct 2017 16:15:01 +0530 Subject: [PATCH 04/17] drm/amd/display: fix high part address in dm_plane_helper_prepare_fb() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The high part calculation of luma and chroma address' was missing in dm_plane_helper_prepare_fb(). This fix brings uniformity in the address' at atomic_check and atomic_commit for both RGB & YUV planes. Signed-off-by: Shirish S Reviewed-by: Michel Dänzer Reviewed-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 635a8a3df3699..c2fefd3e657e6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2896,6 +2896,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, struct amdgpu_framebuffer *afb; struct drm_gem_object *obj; struct amdgpu_bo *rbo; + uint64_t chroma_addr = 0; int r; struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; unsigned int awidth; @@ -2937,11 +2938,16 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); } else { awidth = ALIGN(new_state->fb->width, 64); + plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(afb->address); + plane_state->address.video_progressive.luma_addr.high_part + = upper_32_bits(afb->address); + chroma_addr = afb->address + (u64)(awidth * new_state->fb->height); plane_state->address.video_progressive.chroma_addr.low_part - = lower_32_bits(afb->address) + - (awidth * new_state->fb->height); + = lower_32_bits(chroma_addr); + plane_state->address.video_progressive.chroma_addr.high_part + = upper_32_bits(chroma_addr); } } From 7bef1af3b9c2a5690a41298b5986dbde82fbedbc Mon Sep 17 00:00:00 2001 From: Shirish S Date: Fri, 27 Oct 2017 03:25:55 +0000 Subject: [PATCH 05/17] drm/amd/display: check if modeset is required before adding plane Adding affected planes without checking if modeset is requested from the user space causes performance regression in video p/b scenarios when full screen p/b is not composited. Hence add a check before adding a plane as affected. bug: https://bugs.freedesktop.org/show_bug.cgi?id=103408 Acked-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Shirish S Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c2fefd3e657e6..fd3e995fc4266 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4653,6 +4653,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } else { for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + if (!new_crtc_state->enable) continue; From cc57306f426e3953118f1fcf8a7254dbad46c5f6 Mon Sep 17 00:00:00 2001 From: Andrew Jiang Date: Fri, 20 Oct 2017 16:40:45 -0400 Subject: [PATCH 06/17] drm/amd/display: Use constants from atom.h for HDMI caps read Get rid of the constant we copied over before and just directly use the constants from the file. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c47da645d3b8d..e70612eaf2576 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -24,6 +24,7 @@ */ #include "dm_services.h" +#include "atom.h" #include "dm_helpers.h" #include "dc.h" #include "grph_object_id.h" @@ -45,7 +46,6 @@ #include "dce/dce_11_0_enum.h" #include "dce/dce_11_0_sh_mask.h" -#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C /* Copied from atombios.h */ #define LINK_INFO(...) \ dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \ __VA_ARGS__) @@ -1696,7 +1696,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps & EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; - if (masked_chip_caps == (0x2 << 2)) { + if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { /* DP159, Retimer settings */ eng_id = pipe_ctx->stream_res.stream_enc->id; @@ -1707,7 +1707,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) write_i2c_default_retimer_setting(pipe_ctx, is_vga_mode, is_over_340mhz); } - } else if (masked_chip_caps == (0x1 << 2)) { + } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { /* PI3EQX1204, Redriver settings */ write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); } From 30b7c6147d18d77c6120a8f689d04d2518d3f5e4 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 26 Oct 2017 15:35:14 -0400 Subject: [PATCH 07/17] drm/amd/display: Don't print error when bo_pin is interrupted MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: Also don't print for ERESTARTSYS or EAGAIN v3: Best practice is to only ignore ERESTARTSYS Signed-off-by: Harry Wentland Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fd3e995fc4266..b94987bb6af95 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2923,7 +2923,8 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, amdgpu_bo_unreserve(rbo); if (unlikely(r != 0)) { - DRM_ERROR("Failed to pin framebuffer\n"); + if (r != -ERESTARTSYS) + DRM_ERROR("Failed to pin framebuffer with error %d\n", r); return r; } From f5ba60fefa00ca789c4eb35df38b171d532b3155 Mon Sep 17 00:00:00 2001 From: Drew Davenport Date: Fri, 27 Oct 2017 12:34:46 -0600 Subject: [PATCH 08/17] amdgpu/dc: Avoid dereferencing NULL pointer crtc is dereferenced from within drm_atomic_get_new_crtc_state, so check for NULL before initializing new_crtc_state. Signed-off-by: Drew Davenport Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b94987bb6af95..84591781fca13 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3853,8 +3853,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, /* update planes when needed */ for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { struct drm_crtc *crtc = new_plane_state->crtc; - struct drm_crtc_state *new_crtc_state = - drm_atomic_get_new_crtc_state(state, crtc); + struct drm_crtc_state *new_crtc_state; struct drm_framebuffer *fb = new_plane_state->fb; bool pflip_needed; struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); @@ -3864,7 +3863,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, continue; } - if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active) + if (!fb || !crtc || pcrtc != crtc) + continue; + + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + if (!new_crtc_state->active) continue; pflip_needed = !state->allow_modeset; From 55d9038b0c680ec90e3a7d2440e717ac6a2a8064 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 26 Oct 2017 11:47:42 +0530 Subject: [PATCH 09/17] drm/amd/display: fix null pointer dereference While setting cursor position in case of mpo, input_pixel_processor is not available for underlay, hence add check of the same to avoid null pointer access issue. Signed-off-by: Shirish S Reviewed-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 5cf69af9693d2..572b885195c75 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -288,7 +288,7 @@ bool dc_stream_set_cursor_position( pos_cpy.enable = false; - if (ipp->funcs->ipp_cursor_set_position != NULL) + if (ipp !=NULL && ipp->funcs->ipp_cursor_set_position != NULL) ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); if (mi != NULL && mi->funcs->set_cursor_position != NULL) From efa6a8b7ca0f1c6073a2ac7f5a02f8ea333daf92 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 20 Oct 2017 08:42:41 -0400 Subject: [PATCH 10/17] drm/amd/display: Use plane pointer to avoid line breaks Signed-off-by: Harry Wentland Reviewed-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 84591781fca13..2df9f951b7e7e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1328,13 +1328,16 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) } for (i = 0; i < dm->dc->caps.max_planes; i++) { - mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), - GFP_KERNEL); - if (!mode_info->planes[i]) { + struct amdgpu_plane *plane; + + plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); + mode_info->planes[i] = plane; + + if (!plane) { DRM_ERROR("KMS: Failed to allocate plane\n"); goto fail_free_planes; } - mode_info->planes[i]->base.type = mode_info->plane_type[i]; + plane->base.type = mode_info->plane_type[i]; /* * HACK: IGT tests expect that each plane can only have one From cd8a2ae8dc08a92d4804a7adda645f1f8d1f7586 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 20 Oct 2017 08:28:59 -0400 Subject: [PATCH 11/17] drm/amd/display: Use single fail label in init_drm_dev No need for multiple labels as kfree will always do a NULL check before freeing the memory. Signed-off-by: Harry Wentland Reviewed-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2df9f951b7e7e..6eb7b32fb763f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1335,7 +1335,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (!plane) { DRM_ERROR("KMS: Failed to allocate plane\n"); - goto fail_free_planes; + goto fail; } plane->base.type = mode_info->plane_type[i]; @@ -1351,14 +1351,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) { DRM_ERROR("KMS: Failed to initialize plane\n"); - goto fail_free_planes; + goto fail; } } for (i = 0; i < dm->dc->caps.max_streams; i++) if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { DRM_ERROR("KMS: Failed to initialize crtc\n"); - goto fail_free_planes; + goto fail; } dm->display_indexes_num = dm->dc->caps.max_streams; @@ -1375,20 +1375,20 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); if (!aconnector) - goto fail_free_planes; + goto fail; aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); if (!aencoder) - goto fail_free_connector; + goto fail; if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { DRM_ERROR("KMS: Failed to initialize encoder\n"); - goto fail_free_encoder; + goto fail; } if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { DRM_ERROR("KMS: Failed to initialize connector\n"); - goto fail_free_encoder; + goto fail; } if (dc_link_detect(dc_get_link_at_index(dm->dc, i), @@ -1413,14 +1413,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_VEGA10: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - goto fail_free_encoder; + goto fail; } break; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: if (dcn10_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - goto fail_free_encoder; + goto fail; } /* * Temporary disable until pplib/smu interaction is implemented @@ -1430,17 +1430,15 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) #endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); - goto fail_free_encoder; + goto fail; } drm_mode_config_reset(dm->ddev); return 0; -fail_free_encoder: +fail: kfree(aencoder); -fail_free_connector: kfree(aconnector); -fail_free_planes: for (i = 0; i < dm->dc->caps.max_planes; i++) kfree(mode_info->planes[i]); return -1; From 96719c5439b4d75bfd6b3c5cb24f1a8e537125bb Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 20 Oct 2017 08:43:40 -0400 Subject: [PATCH 12/17] drm/amd/display: Explicitly call ->reset for each object We need to avoid calling reset after detection because the next commit adds freesync properties on the atomic_state which are set during detection. Calling reset after this clears them. The easiest way to accomplish this right now is to call ->reset on the connector right after creation but before detection. To stay consistent call ->reset on every other object as well after creation. v2: Provide better reason for this change in commit msg. Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6eb7b32fb763f..33a15a1d818ca 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1433,8 +1433,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail; } - drm_mode_config_reset(dm->ddev); - return 0; fail: kfree(aencoder); @@ -3081,6 +3079,11 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); + /* Create (reset) the plane state */ + if (aplane->base.funcs->reset) + aplane->base.funcs->reset(&aplane->base); + + return res; } @@ -3116,6 +3119,10 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); + /* Create (reset) the plane state */ + if (acrtc->base.funcs->reset) + acrtc->base.funcs->reset(&acrtc->base); + acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; @@ -3468,6 +3475,9 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, &aconnector->base, &amdgpu_dm_connector_helper_funcs); + if (aconnector->base.funcs->reset) + aconnector->base.funcs->reset(&aconnector->base); + amdgpu_dm_connector_init_helper( dm, aconnector, From b7fa8519057319aef8405923dc8fa6782fce969f Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 31 Oct 2017 16:28:57 -0400 Subject: [PATCH 13/17] drm/amd: Add DCE12 resource strap registers We need them for initializing audio properly. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h | 4 ++++ .../drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h index 75b660d57bdfa..f730d06290201 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h @@ -1841,6 +1841,10 @@ #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define mmDCIO_WRCMD_DELAY 0x2094 #define mmDCIO_WRCMD_DELAY_BASE_IDX 2 +#define mmDC_PINSTRAPS 0x2096 +#define mmDC_PINSTRAPS_BASE_IDX 2 +#define mmCC_DC_MISC_STRAPS 0x2097 +#define mmCC_DC_MISC_STRAPS_BASE_IDX 2 #define mmDC_DVODATA_CONFIG 0x2098 #define mmDC_DVODATA_CONFIG_BASE_IDX 2 #define mmLVTMA_PWRSEQ_CNTL 0x2099 diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h index d8ad862b3a748..6d3162c42957e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h @@ -2447,6 +2447,14 @@ //DCCG_CBUS_WRCMD_DELAY #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0x0000000FL +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +//CC_DC_MISC_STRAPS +#define CC_DC_MISC_STRAPS__HDMI_DISABLE__SHIFT 0x6 +#define CC_DC_MISC_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 +#define CC_DC_MISC_STRAPS__HDMI_DISABLE_MASK 0x00000040L +#define CC_DC_MISC_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x00000700L //DCCG_DS_DTO_INCR #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL From 4a74635ce23a4b8758047a733faf791e38032263 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 1 Nov 2017 10:24:51 -0400 Subject: [PATCH 14/17] drm/amd/display: Read resource_straps from registers for DCE12 Now that the registers exist, assign them to the resource_straps struct. v2: Fix indentation v3: Fix trailing whitespace and checkpatch warnings. bug: https://bugs.freedesktop.org/show_bug.cgi?id=103404 Reviewed-by: Harry Wentland Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- .../amd/display/dc/dce120/dce120_resource.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 3ed28a870e207..5c48c22d9d98e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -501,12 +501,19 @@ static void read_dce_straps( struct dc_context *ctx, struct resource_straps *straps) { - /* TODO: Registers are missing */ - /*REG_GET_2(CC_DC_HDMI_STRAPS, - HDMI_DISABLE, &straps->hdmi_disable, - AUDIO_STREAM_NUMBER, &straps->audio_stream_number); - - REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/ + uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); + + straps->audio_stream_number = get_reg_field_value(reg_val, + CC_DC_MISC_STRAPS, + AUDIO_STREAM_NUMBER); + straps->hdmi_disable = get_reg_field_value(reg_val, + CC_DC_MISC_STRAPS, + HDMI_DISABLE); + + reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); + straps->dc_pinstraps_audio = get_reg_field_value(reg_val, + DC_PINSTRAPS, + DC_PINSTRAPS_AUDIO); } static struct audio *create_audio( From d8eed8263aa09c0c92416d06321eae4ad3eda343 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 15:24:40 +0100 Subject: [PATCH 15/17] drm/amdgpu/display: provide ASSERT macros unconditionally It seems impossible to build this driver without setting either CONFIG_DEBUG_KERNEL or CONFIG_DEBUG_DRIVER: drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h: In function 'set_reg_field_value_ex': drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:132:2: error: implicit declaration of function 'ASSERT'; did you mean 'IS_ERR'? [-Werror=implicit-function-declaration] This moves the ASSERT() macro and related helpers outside of the #ifdef to get it to build again. Reviewed-by: Harry Wentland Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/os_types.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h index 86170b40b5c5f..a87c0329541f5 100644 --- a/drivers/gpu/drm/amd/display/dc/os_types.h +++ b/drivers/gpu/drm/amd/display/dc/os_types.h @@ -61,8 +61,6 @@ * general debug capabilities * */ -#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER) - #if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB) #define ASSERT_CRITICAL(expr) do { \ if (WARN_ON(!(expr))) { \ @@ -86,8 +84,6 @@ #define BREAK_TO_DEBUGGER() ASSERT(0) -#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */ - #define DC_ERR(...) do { \ dm_error(__VA_ARGS__); \ BREAK_TO_DEBUGGER(); \ From d8d46ae97ffd4ace4b8a7f45c232ff4bb8b6c129 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 12:26:42 +0100 Subject: [PATCH 16/17] drm/amdgpu/display: remove unused REG_OFFSET macro The name conflicts with another macro of the same name on the ARM ixp4xx platform, leading to build errors. Neither of the users actually should use a name that generic, but the other one was here first and the dc driver doesn't actually use it. Reviewed-by: Harry Wentland Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_services.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index c8190c38a6443..d4917037ac426 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -160,9 +160,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, /* These macros need to be used with soc15 registers in order to retrieve * the actual offset. */ -#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX]) -#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX]) - #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) From 1f3493faa8d73b0332d46ea79448b10b66fb1af0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 Nov 2017 12:26:43 +0100 Subject: [PATCH 17/17] drm/amdgpu/display: fix integer arithmetic problem gcc warns about an ambiguous integer calculation: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 'calculate_bandwidth': drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:534:5: error: this decimal constant is unsigned only in ISO C90 [-Werror] data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48)); ^~~~ Marking the constant as explicitly unsigned makes it work fine everywhere without warnings. Reviewed-by: Harry Wentland Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 15cbfc4006334..4f8a95368ffcf 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -531,7 +531,7 @@ static void calculate_bandwidth( } switch (data->lb_bpc[i]) { case 8: - data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48)); + data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48)); break; case 10: data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));