From a2a44f8da29352f76c99c6904ee652911b8dc7dd Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 22 Nov 2024 17:37:22 +0800 Subject: [PATCH 01/25] mmc: core: Respect quirk_max_rate for non-UHS SDIO card The card-quirk was added to limit the clock-rate for a card with UHS-mode support, although let's respect the quirk for non-UHS mode too, to make the behaviour consistent. Signed-off-by: Shawn Lin Message-ID: <1732268242-72799-1-git-send-email-shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson --- drivers/mmc/core/sdio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 9566837c9848e..4b19b8a16b096 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -458,6 +458,8 @@ static unsigned mmc_sdio_get_max_clock(struct mmc_card *card) if (mmc_card_sd_combo(card)) max_dtr = min(max_dtr, mmc_sd_get_max_clock(card)); + max_dtr = min_not_zero(max_dtr, card->quirk_max_rate); + return max_dtr; } From 5feebfb4b34c18411d699e64247111221e3c4abc Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 13 Nov 2024 16:56:01 -0600 Subject: [PATCH 02/25] dt-bindings: mmc: marvell,xenon-sdhci: Simplify Armada 3700 if/then schema Properties are supposed to be defined in the top-level schema and then disallowed in an if/then schema if necessary. Move the "marvell,pad-type" property to follow this. "reg" can also be similarly described at the top-level with only the number of entries restricted in the if/then schema. Signed-off-by: Rob Herring (Arm) Acked-by: Conor Dooley Message-ID: <20241113225602.1782573-1-robh@kernel.org> Signed-off-by: Ulf Hansson --- .../bindings/mmc/marvell,xenon-sdhci.yaml | 48 +++++++++---------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml index cfe6237716f4e..3f48d8292d5be 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml @@ -38,15 +38,9 @@ properties: reg: minItems: 1 - maxItems: 2 - description: | - For "marvell,armada-3700-sdhci", two register areas. The first one - for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD - Voltage Control register. Please follow the examples with compatible - "marvell,armada-3700-sdhci" in below. - Please also check property marvell,pad-type in below. - - For other compatible strings, one register area for Xenon IP. + items: + - description: Xenon IP registers + - description: Armada 3700 SoC PHY PAD Voltage Control register clocks: minItems: 1 @@ -61,6 +55,17 @@ properties: interrupts: maxItems: 1 + marvell,pad-type: + $ref: /schemas/types.yaml#/definitions/string + enum: + - sd + - fixed-1-8v + description: + Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is + selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to + 1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY + PAD is fixed 1.8V, such as for eMMC. + marvell,xenon-sdhc-id: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 @@ -147,27 +152,18 @@ allOf: then: properties: reg: - items: - - description: Xenon IP registers - - description: Armada 3700 SoC PHY PAD Voltage Control register - - marvell,pad-type: - $ref: /schemas/types.yaml#/definitions/string - enum: - - sd - - fixed-1-8v - description: | - Type of Armada 3700 SoC PHY PAD Voltage Controller register. - If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning - and is switched to 1.8V when later in higher speed mode. - If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for - eMMC. - Please follow the examples with compatible - "marvell,armada-3700-sdhci" in below. + minItems: 2 required: - marvell,pad-type + else: + properties: + reg: + maxItems: 1 + + marvell,pad-type: false + - if: properties: compatible: From 8593b6871314cff8200308cbc6a1cf6da3fbf356 Mon Sep 17 00:00:00 2001 From: Dharma Balasubiramani Date: Tue, 19 Nov 2024 09:40:10 -0700 Subject: [PATCH 03/25] dt-bindings: mmc: atmel,sama5d2-sdhci: add microchip,sama7d65-sdhci Add mmc binding documentation for SAMA7D65. Signed-off-by: Dharma Balasubiramani Message-ID: Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml b/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml index 8c8ade88e8fe8..ba75623b7778b 100644 --- a/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - microchip,sam9x7-sdhci + - microchip,sama7d65-sdhci - microchip,sama7g5-sdhci - const: microchip,sam9x60-sdhci From 0202dfbdc5dea70e213205aa42ab49a1a08aad3a Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Mon, 25 Nov 2024 10:33:56 +0200 Subject: [PATCH 04/25] mmc: sdhci-esdhc-imx: enable 'SDHCI_QUIRK_NO_LED' quirk for S32G Enable SDHCI_QUIRK_NO_LED quirk for S32G2/S32G3 variants as the controller does not have a LED signal line. Signed-off-by: Ciprian Marian Costea Reviewed-by: Frank Li Acked-by: Adrian Hunter Reviewed-by: Haibo Chen Message-ID: <20241125083357.1041949-1-ciprianmarian.costea@oss.nxp.com> Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-esdhc-imx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index d55d045ef2363..e23177ea9d916 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -304,6 +304,7 @@ static struct esdhc_soc_data usdhc_s32g2_data = { | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES | ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE, + .quirks = SDHCI_QUIRK_NO_LED, }; static struct esdhc_soc_data usdhc_imx7ulp_data = { From ea79df10331218b04d90f028a605f33c879c518d Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Mon, 25 Nov 2024 14:23:11 +0100 Subject: [PATCH 05/25] mmc: core: Drop the MMC_RSP_R1_NO_CRC response The MMC_RSP_R1_NO_CRC type of response is not being used by the mmc core for any commands. Let's therefore drop it, together with the corresponding code in the host drivers. Signed-off-by: Ulf Hansson Acked-by: Wolfram Sang # for TMIO Reviewed-by: Avri Altman Message-ID: <20241125132311.23939-1-ulf.hansson@linaro.org> --- drivers/mmc/host/rtsx_pci_sdmmc.c | 2 -- drivers/mmc/host/rtsx_usb_sdmmc.c | 3 --- drivers/mmc/host/tmio_mmc_core.c | 1 - include/linux/mmc/core.h | 3 --- 4 files changed, 9 deletions(-) diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c index 48d3b0aae5a00..0c6eb60a95fdb 100644 --- a/drivers/mmc/host/rtsx_pci_sdmmc.c +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c @@ -115,8 +115,6 @@ static int sd_response_type(struct mmc_command *cmd) return SD_RSP_TYPE_R0; case MMC_RSP_R1: return SD_RSP_TYPE_R1; - case MMC_RSP_R1_NO_CRC: - return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; case MMC_RSP_R1B: return SD_RSP_TYPE_R1b; case MMC_RSP_R2: diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c b/drivers/mmc/host/rtsx_usb_sdmmc.c index 107c78df53cf4..d229c2b83ea99 100644 --- a/drivers/mmc/host/rtsx_usb_sdmmc.c +++ b/drivers/mmc/host/rtsx_usb_sdmmc.c @@ -313,9 +313,6 @@ static void sd_send_cmd_get_rsp(struct rtsx_usb_sdmmc *host, case MMC_RSP_R1: rsp_type = SD_RSP_TYPE_R1; break; - case MMC_RSP_R1_NO_CRC: - rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; - break; case MMC_RSP_R1B: rsp_type = SD_RSP_TYPE_R1b; break; diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 45a474ccab1c9..04c1c54df791b 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -297,7 +297,6 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host, switch (mmc_resp_type(cmd)) { case MMC_RSP_NONE: c |= RESP_NONE; break; case MMC_RSP_R1: - case MMC_RSP_R1_NO_CRC: c |= RESP_R1; break; case MMC_RSP_R1B: c |= RESP_R1B; break; case MMC_RSP_R2: c |= RESP_R2; break; diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 56972bd78462d..e13856ab6ad05 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -64,9 +64,6 @@ struct mmc_command { #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) -/* Can be used by core to poll after switch to MMC HS mode */ -#define MMC_RSP_R1_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE) - #define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE)) /* From ed97550d470d00ebafe9de888fd100cb82d3abb6 Mon Sep 17 00:00:00 2001 From: Andy-ld Lu Date: Tue, 26 Nov 2024 20:48:22 +0800 Subject: [PATCH 06/25] mmc: core: Introduce the MMC_RSP_R1B_NO_CRC response The R1B response type with ignoring CRC is used in the mmc_cqe_recovery(), introduce the MMC_RSP_R1B_NO_CRC response type to simplify the code. Signed-off-by: Andy-ld Lu Message-ID: <20241126125041.16071-2-andy-ld.lu@mediatek.com> Signed-off-by: Ulf Hansson --- drivers/mmc/core/core.c | 6 ++---- include/linux/mmc/core.h | 1 + 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index d996d39c0d6fa..4ba28a10b2dfa 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -557,8 +557,7 @@ int mmc_cqe_recovery(struct mmc_host *host) memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_STOP_TRANSMISSION; - cmd.flags = MMC_RSP_R1B | MMC_CMD_AC; - cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */ + cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */ cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT; mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES); @@ -567,8 +566,7 @@ int mmc_cqe_recovery(struct mmc_host *host) memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_CMDQ_TASK_MGMT; cmd.arg = 1; /* Discard entire queue */ - cmd.flags = MMC_RSP_R1B | MMC_CMD_AC; - cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */ + cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */ cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT; err = mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES); diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index e13856ab6ad05..01e0f591a20b1 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -57,6 +57,7 @@ struct mmc_command { #define MMC_RSP_NONE (0) #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) #define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) +#define MMC_RSP_R1B_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE|MMC_RSP_BUSY) #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) #define MMC_RSP_R3 (MMC_RSP_PRESENT) #define MMC_RSP_R4 (MMC_RSP_PRESENT) From 02fcf9c9e237e3a8c31cacf67dbb0366b78a7e4f Mon Sep 17 00:00:00 2001 From: Andy-ld Lu Date: Tue, 26 Nov 2024 20:48:23 +0800 Subject: [PATCH 07/25] mmc: mtk-sd: Add support for ignoring cmd response CRC The current process flow does not handle MMC requests that are indicated to ignore the command response CRC. For instance, cmd12 and cmd48 from mmc_cqe_recovery() are marked to ignore CRC, but they are not matched to the appropriate response type in msdc_cmd_find_resp(). As a result, they are defaulted to 'MMC_RSP_NONE', which means no response is expected. This commit applies the flag 'MMC_RSP_R1B_NO_CRC' to fix the response type setting in msdc_cmd_find_resp() and adds the logic to ignore CRC in msdc_cmd_done(). Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Andy-ld Lu Message-ID: <20241126125041.16071-3-andy-ld.lu@mediatek.com> Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index efb0d2d5716b9..e2c385853eef8 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -1097,11 +1097,12 @@ static inline u32 msdc_cmd_find_resp(struct msdc_host *host, u32 resp; switch (mmc_resp_type(cmd)) { - /* Actually, R1, R5, R6, R7 are the same */ + /* Actually, R1, R5, R6, R7 are the same */ case MMC_RSP_R1: resp = 0x1; break; case MMC_RSP_R1B: + case MMC_RSP_R1B_NO_CRC: resp = 0x7; break; case MMC_RSP_R2: @@ -1351,7 +1352,8 @@ static bool msdc_cmd_done(struct msdc_host *host, int events, * CRC error. */ msdc_reset_hw(host); - if (events & MSDC_INT_RSPCRCERR) { + if (events & MSDC_INT_RSPCRCERR && + mmc_resp_type(cmd) != MMC_RSP_R1B_NO_CRC) { cmd->error = -EILSEQ; host->error |= REQ_CMD_EIO; } else if (events & MSDC_INT_CMDTMO) { From 65169604e8d00308c23d66d02a70d67a5e4ff68c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 18 Nov 2024 08:29:07 +0100 Subject: [PATCH 08/25] mmc: core: don't include 'pm_wakeup.h' directly The header clearly states that it does not want to be included directly, only via 'device.h'. 'platform_device.h' works equally well. Remove the direct inclusion. Signed-off-by: Wolfram Sang Message-ID: <20241118072917.3853-9-wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson --- drivers/mmc/core/core.c | 1 - drivers/mmc/core/host.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 4ba28a10b2dfa..5241528f8b90f 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 48bda70145ee6..bdb22998357ea 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include From 634717a2b89a9b2a18af569ddb44ed3cc7de0ec9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Nov 2024 10:47:58 +0100 Subject: [PATCH 09/25] dt-bindings: Drop Bhupesh Sharma from maintainers For more than a year all emails to Bhupesh Sharma's Linaro emails bounce and there were no updates to mailmap. No reviews from Bhupesh, either, so change the maintainer to Bjorn and Konrad (Qualcomm SoC maintainers). Cc: Bhupesh Sharma Signed-off-by: Krzysztof Kozlowski Acked-by: Konrad Dybcio Message-ID: <20241130094758.15553-1-krzysztof.kozlowski@linaro.org> Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 3 ++- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 3 ++- Documentation/devicetree/bindings/net/qcom,ethqos.yaml | 3 ++- .../devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index c09be97434ac0..62310add2e44d 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm crypto engine driver maintainers: - - Bhupesh Sharma + - Bjorn Andersson + - Konrad Dybcio description: This document defines the binding for the QCE crypto diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 8b393e26e025f..eed9063e9bb35 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SDHCI controller (sdhci-msm) maintainers: - - Bhupesh Sharma + - Bjorn Andersson + - Konrad Dybcio description: Secure Digital Host Controller Interface (SDHCI) present on diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index 0bcd593a7bd09..f117471fb06fb 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Ethernet ETHQOS device maintainers: - - Bhupesh Sharma + - Bjorn Andersson + - Konrad Dybcio description: dwmmac based Qualcomm ethernet devices which support Gigabit diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml index 758adb06c8ddd..059cb87b4d6c2 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SM6115 Peripheral Authentication Service maintainers: - - Bhupesh Sharma + - Bjorn Andersson + - Konrad Dybcio description: Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots From aee2ae1423a2f147d28075499af5d9bf063774c5 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 2 Dec 2024 12:51:40 +0100 Subject: [PATCH 10/25] mmc: bcm2835: add suspend/resume pm support Add a minimalistic suspend/resume PM support. Signed-off-by: Stefan Wahren Message-ID: <20241202115140.33492-1-wahrenst@gmx.net> Signed-off-by: Ulf Hansson --- drivers/mmc/host/bcm2835.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c index 7847f0c8b4652..e5f151d092cd3 100644 --- a/drivers/mmc/host/bcm2835.c +++ b/drivers/mmc/host/bcm2835.c @@ -1343,6 +1343,25 @@ static int bcm2835_add_host(struct bcm2835_host *host) return 0; } +static int bcm2835_suspend(struct device *dev) +{ + struct bcm2835_host *host = dev_get_drvdata(dev); + + clk_disable_unprepare(host->clk); + + return 0; +} + +static int bcm2835_resume(struct device *dev) +{ + struct bcm2835_host *host = dev_get_drvdata(dev); + + return clk_prepare_enable(host->clk); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pm_ops, bcm2835_suspend, + bcm2835_resume); + static int bcm2835_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1471,6 +1490,7 @@ static struct platform_driver bcm2835_driver = { .name = "sdhost-bcm2835", .probe_type = PROBE_PREFER_ASYNCHRONOUS, .of_match_table = bcm2835_match, + .pm = pm_ptr(&bcm2835_pm_ops), }, }; module_platform_driver(bcm2835_driver); From b2b8e93ec00b8110cb37cbde5400d5abfdaed6a7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 28 Nov 2024 16:16:41 +0100 Subject: [PATCH 11/25] dt-bindings: mmc: controller: clarify the address-cells description The term "slot ID" has nothing to do with the SDIO function number which is specified in the reg property of the subnodes, rephrase the description to be more accurate. Fixes: f9b7989859dd ("dt-bindings: mmc: Add YAML schemas for the generic MMC options") Signed-off-by: Neil Armstrong Acked-by: Rob Herring (Arm) Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-1-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 58ae298cd2fcf..23884b8184a9d 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -25,7 +25,7 @@ properties: "#address-cells": const: 1 description: | - The cell is the slot ID if a function subnode is used. + The cell is the SDIO function number if a function subnode is used. "#size-cells": const: 0 From 3aee3eec6d2a1a5a2e80ed26906bbc0e431a3007 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 28 Nov 2024 16:16:42 +0100 Subject: [PATCH 12/25] dt-bindings: mmc: controller: move properties common with slot out to mmc-controller-common Move the common MMC "slot" properties because they are shared by the single-slot or multi-slot controllers, and will help defining a simple mmc-slot bindings document with proper slot properties and nodename. Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-2-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson --- .../bindings/mmc/mmc-controller-common.yaml | 357 ++++++++++++++++++ .../bindings/mmc/mmc-controller.yaml | 344 +---------------- 2 files changed, 360 insertions(+), 341 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml new file mode 100644 index 0000000000000..d8297af578049 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMC Controller & Slots Common Properties + +maintainers: + - Ulf Hansson + +description: | + These properties are common to multiple MMC host controllers and the + possible slots or ports for multi-slot controllers. + +properties: + "#address-cells": + const: 1 + description: | + The cell is the SDIO function number if a function subnode is used. + + "#size-cells": + const: 0 + + # Card Detection. + # If none of these properties are supplied, the host native card + # detect will be used. Only one of them should be provided. + + broken-cd: + $ref: /schemas/types.yaml#/definitions/flag + description: + There is no card detection available; polling must be used. + + cd-gpios: + maxItems: 1 + description: + The card detection will be done using the GPIO provided. + + non-removable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Non-removable slot (like eMMC); assume always present. + + # *NOTE* on CD and WP polarity. To use common for all SD/MMC host + # controllers line polarity properties, we have to fix the meaning + # of the "normal" and "inverted" line levels. We choose to follow + # the SDHCI standard, which specifies both those lines as "active + # low." Therefore, using the "cd-inverted" property means, that the + # CD line is active high, i.e. it is high, when a card is + # inserted. Similar logic applies to the "wp-inverted" property. + # + # CD and WP lines can be implemented on the hardware in one of two + # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or + # as dedicated pins. Polarity of dedicated pins can be specified, + # using *-inverted properties. GPIO polarity can also be specified + # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the + # latter case. We choose to use the XOR logic for GPIO CD and WP + # lines. This means, the two properties are "superimposed," for + # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the + # respective *-inverted property property results in a + # double-inversion and actually means the "normal" line polarity is + # in effect. + wp-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + The Write Protect line polarity is inverted. + + cd-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + The CD line polarity is inverted. + + # Other properties + + bus-width: + description: + Number of data lines. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 4, 8] + default: 1 + + max-frequency: + description: | + Maximum operating frequency of the bus: + - for eMMC, the maximum supported frequency is 200MHz, + - for SD/SDIO cards the SDR104 mode has a max supported + frequency of 208MHz, + - some mmc host controllers do support a max frequency upto + 384MHz. + So, lets keep the maximum supported value here. + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 400000 + maximum: 384000000 + + disable-wp: + $ref: /schemas/types.yaml#/definitions/flag + description: + When set, no physical write-protect line is present. This + property should only be specified when the controller has a + dedicated write-protect detection logic. If a GPIO is always used + for the write-protect detection logic, it is sufficient to not + specify the wp-gpios property in the absence of a write-protect + line. Not used in combination with eMMC or SDIO. + + wp-gpios: + maxItems: 1 + description: + GPIO to use for the write-protect detection. + + cd-debounce-delay-ms: + description: + Set delay time before detecting card after card insert + interrupt. + + no-1-8-v: + $ref: /schemas/types.yaml#/definitions/flag + description: + When specified, denotes that 1.8V card voltage is not supported + on this system, even if the controller claims it. + + cap-sd-highspeed: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD high-speed timing is supported. + + cap-mmc-highspeed: + $ref: /schemas/types.yaml#/definitions/flag + description: + MMC high-speed timing is supported. + + sd-uhs-sdr12: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR12 speed is supported. + + sd-uhs-sdr25: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR25 speed is supported. + + sd-uhs-sdr50: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR50 speed is supported. + + sd-uhs-sdr104: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR104 speed is supported. + + sd-uhs-ddr50: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS DDR50 speed is supported. + + cap-power-off-card: + $ref: /schemas/types.yaml#/definitions/flag + description: + Powering off the card is safe. + + cap-mmc-hw-reset: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC hardware reset is supported + + cap-sdio-irq: + $ref: /schemas/types.yaml#/definitions/flag + description: + enable SDIO IRQ signalling on this interface + + full-pwr-cycle: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card is supported. + + full-pwr-cycle-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card in suspend is supported. + + mmc-ddr-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (1.2V I/O) is supported. + + mmc-ddr-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (1.8V I/O) is supported. + + mmc-ddr-3_3v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (3.3V I/O) is supported. + + mmc-hs200-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS200 mode (1.2V I/O) is supported. + + mmc-hs200-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS200 mode (1.8V I/O) is supported. + + mmc-hs400-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 mode (1.2V I/O) is supported. + + mmc-hs400-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 mode (1.8V I/O) is supported. + + mmc-hs400-enhanced-strobe: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 enhanced strobe mode is supported + + no-mmc-hs400: + $ref: /schemas/types.yaml#/definitions/flag + description: + All eMMC HS400 modes are not supported. + + dsr: + description: + Value the card Driver Stage Register (DSR) should be programmed + with. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffff + + no-sdio: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send SDIO commands during + initialization. + + no-sd: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send SD commands during initialization. + + no-mmc: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send MMC commands during + initialization. + + fixed-emmc-driver-type: + description: + For non-removable eMMC, enforce this driver type. The value is + the driver type as specified in the eMMC specification (table + 206 in spec version 5.1) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + + post-power-on-delay-ms: + description: + It was invented for MMC pwrseq-simple which could be referred to + mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay + waiting for I/O signalling and card power supply to be stable, + regardless of whether pwrseq-simple is used. Default to 10ms if + no available. + default: 10 + + supports-cqe: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the corresponding + MMC host controller supports HW command queue feature. + + disable-cqe-dcmd: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the MMC + controller\'s command queue engine (CQE) does not support direct + commands (DCMDs). + + keep-power-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + SDIO only. Preserves card power during a suspend/resume cycle. + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + SDIO only. Enables wake up of host system on SDIO IRQ assertion. + + vmmc-supply: + description: + Supply for the card power + + vqmmc-supply: + description: + Supply for the bus IO line power, such as a level shifter. + If the level shifter is controlled by a GPIO line, this shall + be modeled as a "regulator-fixed" with a GPIO line for + switching the level shifter on/off. + + mmc-pwrseq: + $ref: /schemas/types.yaml#/definitions/phandle + description: + System-on-Chip designs may specify a specific MMC power + sequence. To successfully detect an (e)MMC/SD/SDIO card, that + power sequence must be maintained while initializing the card. + +patternProperties: + "^.*@[0-9]+$": + type: object + description: | + On embedded systems the cards connected to a host may need + additional properties. These can be specified in subnodes to the + host controller node. The subnodes are identified by the + standard \'reg\' property. Which information exactly can be + specified depends on the bindings for the SDIO function driver + for the subnode, as specified by the compatible string. + + properties: + compatible: + description: | + Name of SDIO function following generic names recommended + practice + + reg: + items: + - minimum: 0 + maximum: 7 + description: + Must contain the SDIO function number of the function this + subnode describes. A value of 0 denotes the memory SD + function, values from 1 to 7 denote the SDIO functions. + + required: + - reg + + "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": + $ref: /schemas/types.yaml#/definitions/uint32-array + + minItems: 2 + maxItems: 2 + items: + minimum: 0 + maximum: 359 + description: + Set the clock (phase) delays which are to be configured in the + controller while switching to particular speed mode. These values + are in pair of degrees. + +dependencies: + cd-debounce-delay-ms: [ cd-gpios ] + fixed-emmc-driver-type: [ non-removable ] + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 23884b8184a9d..99c01ce318d3e 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -18,351 +18,13 @@ description: | (and the corresponding mmcblkN devices) by defining an alias in the /aliases device tree node. +$ref: mmc-controller-common.yaml# + properties: $nodename: pattern: "^mmc(@.*)?$" - "#address-cells": - const: 1 - description: | - The cell is the SDIO function number if a function subnode is used. - - "#size-cells": - const: 0 - - # Card Detection. - # If none of these properties are supplied, the host native card - # detect will be used. Only one of them should be provided. - - broken-cd: - $ref: /schemas/types.yaml#/definitions/flag - description: - There is no card detection available; polling must be used. - - cd-gpios: - maxItems: 1 - description: - The card detection will be done using the GPIO provided. - - non-removable: - $ref: /schemas/types.yaml#/definitions/flag - description: - Non-removable slot (like eMMC); assume always present. - - # *NOTE* on CD and WP polarity. To use common for all SD/MMC host - # controllers line polarity properties, we have to fix the meaning - # of the "normal" and "inverted" line levels. We choose to follow - # the SDHCI standard, which specifies both those lines as "active - # low." Therefore, using the "cd-inverted" property means, that the - # CD line is active high, i.e. it is high, when a card is - # inserted. Similar logic applies to the "wp-inverted" property. - # - # CD and WP lines can be implemented on the hardware in one of two - # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or - # as dedicated pins. Polarity of dedicated pins can be specified, - # using *-inverted properties. GPIO polarity can also be specified - # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the - # latter case. We choose to use the XOR logic for GPIO CD and WP - # lines. This means, the two properties are "superimposed," for - # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the - # respective *-inverted property property results in a - # double-inversion and actually means the "normal" line polarity is - # in effect. - wp-inverted: - $ref: /schemas/types.yaml#/definitions/flag - description: - The Write Protect line polarity is inverted. - - cd-inverted: - $ref: /schemas/types.yaml#/definitions/flag - description: - The CD line polarity is inverted. - - # Other properties - - bus-width: - description: - Number of data lines. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 4, 8] - default: 1 - - max-frequency: - description: | - Maximum operating frequency of the bus: - - for eMMC, the maximum supported frequency is 200MHz, - - for SD/SDIO cards the SDR104 mode has a max supported - frequency of 208MHz, - - some mmc host controllers do support a max frequency upto - 384MHz. - So, lets keep the maximum supported value here. - - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 400000 - maximum: 384000000 - - disable-wp: - $ref: /schemas/types.yaml#/definitions/flag - description: - When set, no physical write-protect line is present. This - property should only be specified when the controller has a - dedicated write-protect detection logic. If a GPIO is always used - for the write-protect detection logic, it is sufficient to not - specify the wp-gpios property in the absence of a write-protect - line. Not used in combination with eMMC or SDIO. - - wp-gpios: - maxItems: 1 - description: - GPIO to use for the write-protect detection. - - cd-debounce-delay-ms: - description: - Set delay time before detecting card after card insert - interrupt. - - no-1-8-v: - $ref: /schemas/types.yaml#/definitions/flag - description: - When specified, denotes that 1.8V card voltage is not supported - on this system, even if the controller claims it. - - cap-sd-highspeed: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD high-speed timing is supported. - - cap-mmc-highspeed: - $ref: /schemas/types.yaml#/definitions/flag - description: - MMC high-speed timing is supported. - - sd-uhs-sdr12: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR12 speed is supported. - - sd-uhs-sdr25: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR25 speed is supported. - - sd-uhs-sdr50: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR50 speed is supported. - - sd-uhs-sdr104: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR104 speed is supported. - - sd-uhs-ddr50: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS DDR50 speed is supported. - - cap-power-off-card: - $ref: /schemas/types.yaml#/definitions/flag - description: - Powering off the card is safe. - - cap-mmc-hw-reset: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC hardware reset is supported - - cap-sdio-irq: - $ref: /schemas/types.yaml#/definitions/flag - description: - enable SDIO IRQ signalling on this interface - - full-pwr-cycle: - $ref: /schemas/types.yaml#/definitions/flag - description: - Full power cycle of the card is supported. - - full-pwr-cycle-in-suspend: - $ref: /schemas/types.yaml#/definitions/flag - description: - Full power cycle of the card in suspend is supported. - - mmc-ddr-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (1.2V I/O) is supported. - - mmc-ddr-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (1.8V I/O) is supported. - - mmc-ddr-3_3v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (3.3V I/O) is supported. - - mmc-hs200-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS200 mode (1.2V I/O) is supported. - - mmc-hs200-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS200 mode (1.8V I/O) is supported. - - mmc-hs400-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 mode (1.2V I/O) is supported. - - mmc-hs400-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 mode (1.8V I/O) is supported. - - mmc-hs400-enhanced-strobe: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 enhanced strobe mode is supported - - no-mmc-hs400: - $ref: /schemas/types.yaml#/definitions/flag - description: - All eMMC HS400 modes are not supported. - - dsr: - description: - Value the card Driver Stage Register (DSR) should be programmed - with. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 0xffff - - no-sdio: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send SDIO commands during - initialization. - - no-sd: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send SD commands during initialization. - - no-mmc: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send MMC commands during - initialization. - - fixed-emmc-driver-type: - description: - For non-removable eMMC, enforce this driver type. The value is - the driver type as specified in the eMMC specification (table - 206 in spec version 5.1) - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 4 - - post-power-on-delay-ms: - description: - It was invented for MMC pwrseq-simple which could be referred to - mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay - waiting for I/O signalling and card power supply to be stable, - regardless of whether pwrseq-simple is used. Default to 10ms if - no available. - default: 10 - - supports-cqe: - $ref: /schemas/types.yaml#/definitions/flag - description: - The presence of this property indicates that the corresponding - MMC host controller supports HW command queue feature. - - disable-cqe-dcmd: - $ref: /schemas/types.yaml#/definitions/flag - description: - The presence of this property indicates that the MMC - controller\'s command queue engine (CQE) does not support direct - commands (DCMDs). - - keep-power-in-suspend: - $ref: /schemas/types.yaml#/definitions/flag - description: - SDIO only. Preserves card power during a suspend/resume cycle. - - wakeup-source: - $ref: /schemas/types.yaml#/definitions/flag - description: - SDIO only. Enables wake up of host system on SDIO IRQ assertion. - - vmmc-supply: - description: - Supply for the card power - - vqmmc-supply: - description: - Supply for the bus IO line power, such as a level shifter. - If the level shifter is controlled by a GPIO line, this shall - be modeled as a "regulator-fixed" with a GPIO line for - switching the level shifter on/off. - - mmc-pwrseq: - $ref: /schemas/types.yaml#/definitions/phandle - description: - System-on-Chip designs may specify a specific MMC power - sequence. To successfully detect an (e)MMC/SD/SDIO card, that - power sequence must be maintained while initializing the card. - -patternProperties: - "^.*@[0-9]+$": - type: object - description: | - On embedded systems the cards connected to a host may need - additional properties. These can be specified in subnodes to the - host controller node. The subnodes are identified by the - standard \'reg\' property. Which information exactly can be - specified depends on the bindings for the SDIO function driver - for the subnode, as specified by the compatible string. - - properties: - compatible: - description: | - Name of SDIO function following generic names recommended - practice - - reg: - items: - - minimum: 0 - maximum: 7 - description: - Must contain the SDIO function number of the function this - subnode describes. A value of 0 denotes the memory SD - function, values from 1 to 7 denote the SDIO functions. - - required: - - reg - - "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 2 - maxItems: 2 - items: - minimum: 0 - maximum: 359 - description: - Set the clock (phase) delays which are to be configured in the - controller while switching to particular speed mode. These values - are in pair of degrees. - -dependencies: - cd-debounce-delay-ms: [ cd-gpios ] - fixed-emmc-driver-type: [ non-removable ] - -additionalProperties: true +unevaluatedProperties: true examples: - | From b55a9f72878bfe8b4b5fb8c80ca0ca9f3464e642 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 28 Nov 2024 16:16:43 +0100 Subject: [PATCH 13/25] dt-bindings: mmc: controller: remove '|' when not needed Adding "|" is used to keep the description format, remove it when not needed after the split into mmc-controller.yaml and mmc-controller-common.yaml files. Signed-off-by: Neil Armstrong Acked-by: Rob Herring (Arm) Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-3-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/mmc-controller-common.yaml | 6 +++--- Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index d8297af578049..9a72354397591 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -9,14 +9,14 @@ title: MMC Controller & Slots Common Properties maintainers: - Ulf Hansson -description: | +description: These properties are common to multiple MMC host controllers and the possible slots or ports for multi-slot controllers. properties: "#address-cells": const: 1 - description: | + description: The cell is the SDIO function number if a function subnode is used. "#size-cells": @@ -321,7 +321,7 @@ patternProperties: properties: compatible: - description: | + description: Name of SDIO function following generic names recommended practice diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 99c01ce318d3e..9d7a1298c4554 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -9,7 +9,7 @@ title: MMC Controller Common Properties maintainers: - Ulf Hansson -description: | +description: These properties are common to multiple MMC host controllers. Any host that requires the respective functionality should implement them using these definitions. From b833f3deb1abdccc171e6a7ad6aa2f3f66e4f7f7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 28 Nov 2024 16:16:44 +0100 Subject: [PATCH 14/25] dt-bindings: mmc: document mmc-slot Document the mmc-slot, which is a subnode of a multi-slot MMC controller, each slot is represented as a full MMC controller, the top node handling all the shared resources and slot mux. Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-4-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/mmc-slot.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/mmc-slot.yaml diff --git a/Documentation/devicetree/bindings/mmc/mmc-slot.yaml b/Documentation/devicetree/bindings/mmc/mmc-slot.yaml new file mode 100644 index 0000000000000..1f06678280634 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-slot.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-slot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMC slot properties + +maintainers: + - Ulf Hansson + +description: + These properties defines slot properties for MMC controlers that + have multiple slots or ports provided by the same controller and + sharing the same resources. + +$ref: mmc-controller-common.yaml# + +properties: + $nodename: + pattern: "^slot(@.*)?$" + + compatible: + const: mmc-slot + + reg: + description: + the slot (or "port") ID + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mmc { + #address-cells = <1>; + #size-cells = <0>; + slot@0 { + compatible = "mmc-slot"; + reg = <0>; + bus-width = <4>; + }; + }; + +... From ea049a037e9e01e4dd92e44c21f8d594e64e4396 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 28 Nov 2024 16:16:45 +0100 Subject: [PATCH 15/25] dt-bindings: mmc: convert amlogic,meson-mx-sdio.txt to dtschema Convert the Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller bindings to dt-schema. Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong Message-ID: <20241128-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v4-5-11d9f9200a59@linaro.org> Signed-off-by: Ulf Hansson --- .../bindings/mmc/amlogic,meson-mx-sdio.txt | 54 ----------- .../bindings/mmc/amlogic,meson-mx-sdio.yaml | 94 +++++++++++++++++++ 2 files changed, 94 insertions(+), 54 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt deleted file mode 100644 index 8765c605e6bc7..0000000000000 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller - -The highspeed MMC host controller on Amlogic SoCs provides an interface -for MMC, SD, SDIO and SDHC types of memory cards. - -Supported maximum speeds are the ones of the eMMC standard 4.41 as well -as the speed of SD standard 2.0. - -The hardware provides an internal "mux" which allows up to three slots -to be controlled. Only one slot can be accessed at a time. - -Required properties: - - compatible : must be one of - - "amlogic,meson8-sdio" - - "amlogic,meson8b-sdio" - along with the generic "amlogic,meson-mx-sdio" - - reg : mmc controller base registers - - interrupts : mmc controller interrupt - - #address-cells : must be 1 - - size-cells : must be 0 - - clocks : phandle to clock providers - - clock-names : must contain "core" and "clkin" - -Required child nodes: -A node for each slot provided by the MMC controller is required. -NOTE: due to a driver limitation currently only one slot (= child node) - is supported! - -Required properties on each child node (= slot): - - compatible : must be "mmc-slot" (see mmc.txt within this directory) - - reg : the slot (or "port") ID - -Optional properties on each child node (= slot): - - bus-width : must be 1 or 4 (8-bit bus is not supported) - - for cd and all other additional generic mmc parameters - please refer to mmc.txt within this directory - -Examples: - mmc@c1108c20 { - compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; - reg = <0xc1108c20 0x20>; - interrupts = <0 28 1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; - - slot@1 { - compatible = "mmc-slot"; - reg = <1>; - - bus-width = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml new file mode 100644 index 0000000000000..022682a977c6d --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller + +description: | + The highspeed MMC host controller on Amlogic SoCs provides an interface + for MMC, SD, SDIO and SDHC types of memory cards. + + Supported maximum speeds are the ones of the eMMC standard 4.41 as well + as the speed of SD standard 2.0. + + The hardware provides an internal "mux" which allows up to three slots + to be controlled. Only one slot can be accessed at a time. + +maintainers: + - Neil Armstrong + +properties: + compatible: + items: + - enum: + - amlogic,meson8-sdio + - amlogic,meson8b-sdio + - const: amlogic,meson-mx-sdio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: clkin + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "slot@[0-2]$": + $ref: mmc-slot.yaml# + description: + A node for each slot provided by the MMC controller + + properties: + reg: + enum: [0, 1, 2] + + bus-width: + enum: [1, 4] + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + mmc@c1108c20 { + compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; + reg = <0xc1108c20 0x20>; + interrupts = ; + clocks = <&clk_core>, <&clk_in>; + clock-names = "core", "clkin"; + #address-cells = <1>; + #size-cells = <0>; + + slot@1 { + compatible = "mmc-slot"; + reg = <1>; + bus-width = <4>; + }; + }; From 88e3008424d3882af1d8e56a43373bb1f2d14714 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 1 Nov 2024 12:11:33 +0200 Subject: [PATCH 16/25] mmc: sdhci-acpi: Remove not so useful error message First of all, this error message is just informative and doesn't prevent driver from going on. Second, the ioremap() on many architectures just works on page size granularity, which is higher than 256 bytes. Last, but not lease, this is an impediment for furhter cleanups, hence remove it. Signed-off-by: Andy Shevchenko Acked-by: Adrian Hunter Message-ID: <20241101101441.3518612-4-andriy.shevchenko@linux.intel.com> Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-acpi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index d1ce9193ece93..d577c6515b86b 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -849,9 +849,6 @@ static int sdhci_acpi_probe(struct platform_device *pdev) return -ENOMEM; len = resource_size(iomem); - if (len < 0x100) - dev_err(dev, "Invalid iomem size!\n"); - if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev))) return -ENOMEM; From ecfe4926dcdc68e9dde8150df583703b32bc9833 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 1 Nov 2024 12:11:34 +0200 Subject: [PATCH 17/25] mmc: sdhci-acpi: Use devm_platform_ioremap_resource() The struct resource is not used for anything else, so we can simplify the code a bit by using the helper function. Signed-off-by: Andy Shevchenko Acked-by: Adrian Hunter Message-ID: <20241101101441.3518612-5-andriy.shevchenko@linux.intel.com> Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-acpi.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index d577c6515b86b..e6c5c82f64faa 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -822,8 +822,6 @@ static int sdhci_acpi_probe(struct platform_device *pdev) struct acpi_device *device; struct sdhci_acpi_host *c; struct sdhci_host *host; - struct resource *iomem; - resource_size_t len; size_t priv_size; int quirks = 0; int err; @@ -844,14 +842,6 @@ static int sdhci_acpi_probe(struct platform_device *pdev) if (sdhci_acpi_byt_defer(dev)) return -EPROBE_DEFER; - iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!iomem) - return -ENOMEM; - - len = resource_size(iomem); - if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev))) - return -ENOMEM; - priv_size = slot ? slot->priv_size : 0; host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size); if (IS_ERR(host)) @@ -873,10 +863,9 @@ static int sdhci_acpi_probe(struct platform_device *pdev) goto err_free; } - host->ioaddr = devm_ioremap(dev, iomem->start, - resource_size(iomem)); - if (host->ioaddr == NULL) { - err = -ENOMEM; + host->ioaddr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(host->ioaddr)) { + err = PTR_ERR(host->ioaddr); goto err_free; } From 6af057a8a5f60512ea49af028e5cf4042cb70de3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 10 Dec 2024 15:32:10 +0800 Subject: [PATCH 18/25] dt-bindings: mmc: mtk-sd: Document compatibles that need two register ranges Besides the MT8183's MMC controller and all its compatible derivatives, the recently added MT7986 and MT8196 also require two register ranges. This is based on the actual device trees. Properly enforce this in the binding. Fixes: 4a8bd2b07d88 ("dt-bindings: mmc: mtk-sd: Add mt7988 SoC") Fixes: 58927c9dc4ab ("dt-bindings: mmc: mtk-sd: Add support for MT8196") Cc: Frank Wunderlich Cc: Andy-ld Lu Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Message-ID: <20241210073212.3917912-2-wenst@chromium.org> Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index f86ebd81f5a56..0debccbd6519c 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -235,11 +235,19 @@ allOf: properties: compatible: contains: - const: mediatek,mt8183-mmc + enum: + - mediatek,mt7986-mmc + - mediatek,mt7988-mmc + - mediatek,mt8183-mmc + - mediatek,mt8196-mmc then: properties: reg: minItems: 2 + else: + properties: + reg: + maxItems: 1 - if: properties: From 6ee5233a4c91fd0299c439b06d2d79bae54db4a3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 10 Dec 2024 15:32:11 +0800 Subject: [PATCH 19/25] mmc: mtk-sd: Limit getting top_base to SoCs that require it Currently the mtk-sd driver tries to get and map the second register base, named top_base in the code, regardless of whether the SoC model actually has it or not. This produces confusing big error messages on the platforms that don't need it: mtk-msdc 11260000.mmc: error -EINVAL: invalid resource (null) Limit it to the platforms that actually require it, based on their device tree entries, and properly fail if it is missing. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Message-ID: <20241210073212.3917912-3-wenst@chromium.org> Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 9a727d839d197..4b6e913725260 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -414,6 +414,7 @@ struct mtk_mmc_compatible { u8 clk_div_bits; bool recheck_sdio_irq; bool hs400_tune; /* only used for MT8173 */ + bool needs_top_base; u32 pad_tune_reg; bool async_fifo; bool data_tune; @@ -587,6 +588,7 @@ static const struct mtk_mmc_compatible mt7986_compat = { .clk_div_bits = 12, .recheck_sdio_irq = true, .hs400_tune = false, + .needs_top_base = true, .pad_tune_reg = MSDC_PAD_TUNE0, .async_fifo = true, .data_tune = true, @@ -627,6 +629,7 @@ static const struct mtk_mmc_compatible mt8183_compat = { .clk_div_bits = 12, .recheck_sdio_irq = false, .hs400_tune = false, + .needs_top_base = true, .pad_tune_reg = MSDC_PAD_TUNE0, .async_fifo = true, .data_tune = true, @@ -653,6 +656,7 @@ static const struct mtk_mmc_compatible mt8196_compat = { .clk_div_bits = 12, .recheck_sdio_irq = false, .hs400_tune = false, + .needs_top_base = true, .pad_tune_reg = MSDC_PAD_TUNE0, .async_fifo = true, .data_tune = true, @@ -2887,9 +2891,13 @@ static int msdc_drv_probe(struct platform_device *pdev) if (IS_ERR(host->base)) return PTR_ERR(host->base); - host->top_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(host->top_base)) - host->top_base = NULL; + host->dev_comp = of_device_get_match_data(&pdev->dev); + + if (host->dev_comp->needs_top_base) { + host->top_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(host->top_base)) + return PTR_ERR(host->top_base); + } ret = mmc_regulator_get_supply(mmc); if (ret) @@ -2951,7 +2959,6 @@ static int msdc_drv_probe(struct platform_device *pdev) msdc_of_property_parse(pdev, host); host->dev = &pdev->dev; - host->dev_comp = of_device_get_match_data(&pdev->dev); host->src_clk_freq = clk_get_rate(host->src_clk); /* Set host parameters to mmc */ mmc->ops = &mt_msdc_ops; From 08a7ead3242f70f4415232800104ae458fd96d17 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 12 Dec 2024 20:19:49 -0800 Subject: [PATCH 20/25] mmc: crypto: add mmc_from_crypto_profile() Add a helper function that encapsulates a container_of expression. For now there is just one user but soon there will be more. Signed-off-by: Eric Biggers Message-ID: <20241213041958.202565-7-ebiggers@kernel.org> Signed-off-by: Ulf Hansson --- drivers/mmc/host/cqhci-crypto.c | 5 +---- include/linux/mmc/host.h | 8 ++++++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c index d5f4b6972f63e..2951911d3f780 100644 --- a/drivers/mmc/host/cqhci-crypto.c +++ b/drivers/mmc/host/cqhci-crypto.c @@ -25,10 +25,7 @@ static const struct cqhci_crypto_alg_entry { static inline struct cqhci_host * cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile) { - struct mmc_host *mmc = - container_of(profile, struct mmc_host, crypto_profile); - - return mmc->cqe_private; + return mmc_from_crypto_profile(profile)->cqe_private; } static int cqhci_crypto_program_key(struct cqhci_host *cq_host, diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index f166d6611ddb9..68f09a955a902 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -590,6 +590,14 @@ static inline struct mmc_host *mmc_from_priv(void *priv) return container_of(priv, struct mmc_host, private); } +#ifdef CONFIG_MMC_CRYPTO +static inline struct mmc_host * +mmc_from_crypto_profile(struct blk_crypto_profile *profile) +{ + return container_of(profile, struct mmc_host, crypto_profile); +} +#endif + #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) #define mmc_dev(x) ((x)->parent) From 741521fa273fdd119f149dd208d7b60fc9400bb5 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 12 Dec 2024 20:19:50 -0800 Subject: [PATCH 21/25] mmc: sdhci-msm: convert to use custom crypto profile As is being done in ufs-qcom, make the sdhci-msm driver override the full crypto profile rather than "just" key programming and eviction. This makes it much more straightforward to add support for hardware-wrapped inline encryption keys. It also makes it easy to pass the original blk_crypto_key down to qcom_ice_program_key() once it is updated to require the key in that form. Signed-off-by: Eric Biggers Message-ID: <20241213041958.202565-8-ebiggers@kernel.org> Signed-off-by: Ulf Hansson --- drivers/mmc/host/cqhci-crypto.c | 33 ++++++------ drivers/mmc/host/cqhci.h | 8 ++- drivers/mmc/host/sdhci-msm.c | 94 ++++++++++++++++++++++++++------- 3 files changed, 94 insertions(+), 41 deletions(-) diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c index 2951911d3f780..cb80440934022 100644 --- a/drivers/mmc/host/cqhci-crypto.c +++ b/drivers/mmc/host/cqhci-crypto.c @@ -28,16 +28,13 @@ cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile) return mmc_from_crypto_profile(profile)->cqe_private; } -static int cqhci_crypto_program_key(struct cqhci_host *cq_host, - const union cqhci_crypto_cfg_entry *cfg, - int slot) +static void cqhci_crypto_program_key(struct cqhci_host *cq_host, + const union cqhci_crypto_cfg_entry *cfg, + int slot) { u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); int i; - if (cq_host->ops->program_key) - return cq_host->ops->program_key(cq_host, cfg, slot); - /* Clear CFGE */ cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); @@ -52,7 +49,6 @@ static int cqhci_crypto_program_key(struct cqhci_host *cq_host, /* Write dword 16, which includes the new value of CFGE */ cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]), slot_offset + 16 * sizeof(cfg->reg_val[0])); - return 0; } static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile, @@ -69,7 +65,6 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile, int i; int cap_idx = -1; union cqhci_crypto_cfg_entry cfg = {}; - int err; BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0); for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) { @@ -96,10 +91,10 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile, memcpy(cfg.crypto_key, key->raw, key->size); } - err = cqhci_crypto_program_key(cq_host, &cfg, slot); + cqhci_crypto_program_key(cq_host, &cfg, slot); memzero_explicit(&cfg, sizeof(cfg)); - return err; + return 0; } static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot) @@ -110,7 +105,8 @@ static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot) */ union cqhci_crypto_cfg_entry cfg = {}; - return cqhci_crypto_program_key(cq_host, &cfg, slot); + cqhci_crypto_program_key(cq_host, &cfg, slot); + return 0; } static int cqhci_crypto_keyslot_evict(struct blk_crypto_profile *profile, @@ -167,7 +163,6 @@ int cqhci_crypto_init(struct cqhci_host *cq_host) struct mmc_host *mmc = cq_host->mmc; struct device *dev = mmc_dev(mmc); struct blk_crypto_profile *profile = &mmc->crypto_profile; - unsigned int num_keyslots; unsigned int cap_idx; enum blk_crypto_mode_num blk_mode_num; unsigned int slot; @@ -177,6 +172,9 @@ int cqhci_crypto_init(struct cqhci_host *cq_host) !(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS)) goto out; + if (cq_host->ops->uses_custom_crypto_profile) + goto profile_initialized; + cq_host->crypto_capabilities.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP)); @@ -195,9 +193,8 @@ int cqhci_crypto_init(struct cqhci_host *cq_host) * CCAP.CFGC is off by one, so the actual number of crypto * configurations (a.k.a. keyslots) is CCAP.CFGC + 1. */ - num_keyslots = cq_host->crypto_capabilities.config_count + 1; - - err = devm_blk_crypto_profile_init(dev, profile, num_keyslots); + err = devm_blk_crypto_profile_init( + dev, profile, cq_host->crypto_capabilities.config_count + 1); if (err) goto out; @@ -225,9 +222,11 @@ int cqhci_crypto_init(struct cqhci_host *cq_host) cq_host->crypto_cap_array[cap_idx].sdus_mask * 512; } +profile_initialized: + /* Clear all the keyslots so that we start in a known state. */ - for (slot = 0; slot < num_keyslots; slot++) - cqhci_crypto_clear_keyslot(cq_host, slot); + for (slot = 0; slot < profile->num_slots; slot++) + profile->ll_ops.keyslot_evict(profile, NULL, slot); /* CQHCI crypto requires the use of 128-bit task descriptors. */ cq_host->caps |= CQHCI_TASK_DESC_SZ_128; diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index fab9d74445ba7..ce189a1866b9d 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -289,13 +289,11 @@ struct cqhci_host_ops { u64 *data); void (*pre_enable)(struct mmc_host *mmc); void (*post_disable)(struct mmc_host *mmc); -#ifdef CONFIG_MMC_CRYPTO - int (*program_key)(struct cqhci_host *cq_host, - const union cqhci_crypto_cfg_entry *cfg, int slot); -#endif void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc, dma_addr_t addr, int len, bool end, bool dma64); - +#ifdef CONFIG_MMC_CRYPTO + bool uses_custom_crypto_profile; +#endif }; static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 319f0ebbe652d..4610f067faca4 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1807,12 +1807,19 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) #ifdef CONFIG_MMC_CRYPTO +static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */ + static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, struct cqhci_host *cq_host) { struct mmc_host *mmc = msm_host->mmc; + struct blk_crypto_profile *profile = &mmc->crypto_profile; struct device *dev = mmc_dev(mmc); struct qcom_ice *ice; + union cqhci_crypto_capabilities caps; + union cqhci_crypto_cap_entry cap; + int err; + int i; if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS)) return 0; @@ -1827,8 +1834,37 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, return PTR_ERR_OR_ZERO(ice); msm_host->ice = ice; - mmc->caps2 |= MMC_CAP2_CRYPTO; + /* Initialize the blk_crypto_profile */ + + caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP)); + + /* The number of keyslots supported is (CFGC+1) */ + err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); + if (err) + return err; + + profile->ll_ops = sdhci_msm_crypto_ops; + profile->max_dun_bytes_supported = 4; + profile->dev = dev; + + /* + * Currently this driver only supports AES-256-XTS. All known versions + * of ICE support it, but to be safe make sure it is really declared in + * the crypto capability registers. The crypto capability registers + * also give the supported data unit size(s). + */ + for (i = 0; i < caps.num_crypto_cap; i++) { + cap.reg_val = cpu_to_le32(cqhci_readl(cq_host, + CQHCI_CRYPTOCAP + + i * sizeof(__le32))); + if (cap.algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS && + cap.key_size == CQHCI_CRYPTO_KEY_SIZE_256) + profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= + cap.sdus_mask * 512; + } + + mmc->caps2 |= MMC_CAP2_CRYPTO; return 0; } @@ -1854,35 +1890,55 @@ static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host) return 0; } -/* - * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires - * vendor-specific SCM calls for this; it doesn't support the standard way. - */ -static int sdhci_msm_program_key(struct cqhci_host *cq_host, - const union cqhci_crypto_cfg_entry *cfg, - int slot) +static inline struct sdhci_msm_host * +sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile) { - struct sdhci_host *host = mmc_priv(cq_host->mmc); + struct mmc_host *mmc = mmc_from_crypto_profile(profile); + struct sdhci_host *host = mmc_priv(mmc); struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); - union cqhci_crypto_cap_entry cap; - if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) - return qcom_ice_evict_key(msm_host->ice, slot); + return msm_host; +} + +/* + * Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call + * for this; it doesn't support the standard way. + */ +static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile *profile, + const struct blk_crypto_key *key, + unsigned int slot) +{ + struct sdhci_msm_host *msm_host = + sdhci_msm_host_from_crypto_profile(profile); /* Only AES-256-XTS has been tested so far. */ - cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; - if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS || - cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) - return -EINVAL; + if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS) + return -EOPNOTSUPP; return qcom_ice_program_key(msm_host->ice, QCOM_ICE_CRYPTO_ALG_AES_XTS, QCOM_ICE_CRYPTO_KEY_SIZE_256, - cfg->crypto_key, - cfg->data_unit_size, slot); + key->raw, + key->crypto_cfg.data_unit_size / 512, + slot); } +static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile, + const struct blk_crypto_key *key, + unsigned int slot) +{ + struct sdhci_msm_host *msm_host = + sdhci_msm_host_from_crypto_profile(profile); + + return qcom_ice_evict_key(msm_host->ice, slot); +} + +static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = { + .keyslot_program = sdhci_msm_ice_keyslot_program, + .keyslot_evict = sdhci_msm_ice_keyslot_evict, +}; + #else /* CONFIG_MMC_CRYPTO */ static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, @@ -1988,7 +2044,7 @@ static const struct cqhci_host_ops sdhci_msm_cqhci_ops = { .enable = sdhci_msm_cqe_enable, .disable = sdhci_msm_cqe_disable, #ifdef CONFIG_MMC_CRYPTO - .program_key = sdhci_msm_program_key, + .uses_custom_crypto_profile = true, #endif }; From 285035a8dac5777422268176e373161618ec00b3 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 5 Jan 2025 18:13:39 +0200 Subject: [PATCH 22/25] dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatible for exynos8895 Add samsung,exynos8895-dw-mshc-smu specific compatible to the bindings documentation. Since Samsung, as usual, likes reusing devices from older designs, use the samsung,exynos7-dw-mshc-smu compatible. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20250105161344.420749-2-ivo.ivanov.ivanov1@gmail.com/ Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index 5fe65795f7963..ef2d1d7c92fc8 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -29,6 +29,7 @@ properties: - samsung,exynos5433-dw-mshc-smu - samsung,exynos7885-dw-mshc-smu - samsung,exynos850-dw-mshc-smu + - samsung,exynos8895-dw-mshc-smu - const: samsung,exynos7-dw-mshc-smu reg: From 57a217f193f3b77161a307dd9963ac19d66a17d1 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 9 Jan 2025 09:52:54 -0600 Subject: [PATCH 23/25] mmc: Use of_property_present() for non-boolean properties The use of of_property_read_bool() for non-boolean properties is deprecated in favor of of_property_present() when testing for property presence. Reviewed-by: Haibo Chen Reviewed-by: Dragan Simic Acked-by: Adrian Hunter Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/all/20250109155255.3438450-1-robh@kernel.org/ Signed-off-by: Ulf Hansson --- drivers/mmc/host/mxcmmc.c | 8 ++++---- drivers/mmc/host/sdhci-esdhc-imx.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index e7a286c3216fd..0a9affd125320 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -995,7 +995,7 @@ static int mxcmci_probe(struct platform_device *pdev) struct mxcmci_host *host; struct resource *res; int ret = 0, irq; - bool dat3_card_detect = false; + bool dat3_card_detect; dma_cap_mask_t mask; struct imxmmc_platform_data *pdata = pdev->dev.platform_data; @@ -1048,9 +1048,9 @@ static int mxcmci_probe(struct platform_device *pdev) if (pdata) dat3_card_detect = pdata->dat3_card_detect; - else if (mmc_card_is_removable(mmc) - && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) - dat3_card_detect = true; + else + dat3_card_detect = mmc_card_is_removable(mmc) && + !of_property_present(pdev->dev.of_node, "cd-gpios"); ret = mmc_regulator_get_supply(mmc); if (ret) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index e23177ea9d916..ff78a7c6a04c9 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -1648,7 +1648,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, * Retrieving and requesting the actual WP GPIO will happen * in the call to mmc_of_parse(). */ - if (of_property_read_bool(np, "wp-gpios")) + if (of_property_present(np, "wp-gpios")) boarddata->wp_type = ESDHC_WP_GPIO; of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); From 1931cd769a087cfea2f2e1f74769001a7a3be9f1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Jan 2025 19:54:09 +0100 Subject: [PATCH 24/25] mmc: hi3798mv200: Use syscon_regmap_lookup_by_phandle_args Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over syscon_regmap_lookup_by_phandle() combined with getting the syscon argument. Except simpler code this annotates within one line that given phandle has arguments, so grepping for code would be easier. There is also no real benefit in printing errors on missing syscon argument, because this is done just too late: runtime check on static/build-time data. Dtschema and Devicetree bindings offer the static/build-time check for this already. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20250111185410.183896-1-krzysztof.kozlowski@linaro.org>/ Signed-off-by: Ulf Hansson --- drivers/mmc/host/dw_mmc-hi3798mv200.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-hi3798mv200.c b/drivers/mmc/host/dw_mmc-hi3798mv200.c index cce174b5249bb..5791a975a944d 100644 --- a/drivers/mmc/host/dw_mmc-hi3798mv200.c +++ b/drivers/mmc/host/dw_mmc-hi3798mv200.c @@ -181,7 +181,6 @@ static int dw_mci_hi3798mv200_init(struct dw_mci *host) { struct dw_mci_hi3798mv200_priv *priv; struct device_node *np = host->dev->of_node; - int ret; priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -199,15 +198,12 @@ static int dw_mci_hi3798mv200_init(struct dw_mci *host) return dev_err_probe(host->dev, PTR_ERR(priv->drive_clk), "failed to get enabled ciu-drive clock\n"); - priv->crg_reg = syscon_regmap_lookup_by_phandle(np, "hisilicon,sap-dll-reg"); + priv->crg_reg = syscon_regmap_lookup_by_phandle_args(np, "hisilicon,sap-dll-reg", + 1, &priv->sap_dll_offset); if (IS_ERR(priv->crg_reg)) return dev_err_probe(host->dev, PTR_ERR(priv->crg_reg), "failed to get CRG reg\n"); - ret = of_property_read_u32_index(np, "hisilicon,sap-dll-reg", 1, &priv->sap_dll_offset); - if (ret) - return dev_err_probe(host->dev, ret, "failed to get sample DLL register offset\n"); - host->priv = priv; return 0; } From 20a0c37e44063997391430c4ae09973e9cbc3911 Mon Sep 17 00:00:00 2001 From: Yuanjie Yang Date: Tue, 14 Jan 2025 16:35:14 +0800 Subject: [PATCH 25/25] mmc: sdhci-msm: Correctly set the load for the regulator Qualcomm regulator supports two power supply modes: HPM and LPM. Currently, the sdhci-msm.c driver does not set the load to adjust the current for eMMC and SD. If the regulator dont't set correct load in LPM state, it will lead to the inability to properly initialize eMMC and SD. Set the correct regulator current for eMMC and SD to ensure that the device can work normally even when the regulator is in LPM. Signed-off-by: Yuanjie Yang Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250114083514.258379-1-quic_yuanjiey@quicinc.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 53 ++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4610f067faca4..e3d39311fdc75 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -134,9 +134,18 @@ /* Timeout value to avoid infinite waiting for pwr_irq */ #define MSM_PWR_IRQ_TIMEOUT_MS 5000 +/* Max load for eMMC Vdd supply */ +#define MMC_VMMC_MAX_LOAD_UA 570000 + /* Max load for eMMC Vdd-io supply */ #define MMC_VQMMC_MAX_LOAD_UA 325000 +/* Max load for SD Vdd supply */ +#define SD_VMMC_MAX_LOAD_UA 800000 + +/* Max load for SD Vdd-io supply */ +#define SD_VQMMC_MAX_LOAD_UA 22000 + #define msm_host_readl(msm_host, host, offset) \ msm_host->var_ops->msm_readl_relaxed(host, offset) @@ -1403,11 +1412,48 @@ static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level) return ret; } -static int sdhci_msm_set_vmmc(struct mmc_host *mmc) +static void msm_config_vmmc_regulator(struct mmc_host *mmc, bool hpm) +{ + int load; + + if (!hpm) + load = 0; + else if (!mmc->card) + load = max(MMC_VMMC_MAX_LOAD_UA, SD_VMMC_MAX_LOAD_UA); + else if (mmc_card_mmc(mmc->card)) + load = MMC_VMMC_MAX_LOAD_UA; + else if (mmc_card_sd(mmc->card)) + load = SD_VMMC_MAX_LOAD_UA; + else + return; + + regulator_set_load(mmc->supply.vmmc, load); +} + +static void msm_config_vqmmc_regulator(struct mmc_host *mmc, bool hpm) +{ + int load; + + if (!hpm) + load = 0; + else if (!mmc->card) + load = max(MMC_VQMMC_MAX_LOAD_UA, SD_VQMMC_MAX_LOAD_UA); + else if (mmc_card_sd(mmc->card)) + load = SD_VQMMC_MAX_LOAD_UA; + else + return; + + regulator_set_load(mmc->supply.vqmmc, load); +} + +static int sdhci_msm_set_vmmc(struct sdhci_msm_host *msm_host, + struct mmc_host *mmc, bool hpm) { if (IS_ERR(mmc->supply.vmmc)) return 0; + msm_config_vmmc_regulator(mmc, hpm); + return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); } @@ -1420,6 +1466,8 @@ static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host, if (msm_host->vqmmc_enabled == level) return 0; + msm_config_vqmmc_regulator(mmc, level); + if (level) { /* Set the IO voltage regulator to default voltage level */ if (msm_host->caps_0 & CORE_3_0V_SUPPORT) @@ -1642,7 +1690,8 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) } if (pwr_state) { - ret = sdhci_msm_set_vmmc(mmc); + ret = sdhci_msm_set_vmmc(msm_host, mmc, + pwr_state & REQ_BUS_ON); if (!ret) ret = sdhci_msm_set_vqmmc(msm_host, mmc, pwr_state & REQ_BUS_ON);