From 53367bd28f3bf143355e66f20cb6cb83b70e9122 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 4 Mar 2022 14:32:41 +0000 Subject: [PATCH 01/66] clk: renesas: rzg2l: Remove unused notifiers notifiers is not used. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220304143241.8523-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 486d0656c58ac..b3a1533970e56 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -76,7 +76,6 @@ struct sd_hw_data { * @num_mod_clks: Number of Module Clocks in clks[] * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT - * @notifiers: Notifier chain to save/restore clock state for system resume * @info: Pointer to platform data */ struct rzg2l_cpg_priv { @@ -91,7 +90,6 @@ struct rzg2l_cpg_priv { unsigned int num_resets; unsigned int last_dt_core_clk; - struct raw_notifier_head notifiers; const struct rzg2l_cpg_info *info; }; From 3733db1f77130588c9a2c1596937294998bd7d27 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 14:29:15 +0000 Subject: [PATCH 02/66] dt-bindings: clock: renesas: Document RZ/G2UL SoC Document the device tree binding for the Renesas RZ/G2UL Type-1 and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1 SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index bd3af8fc616b7..311a935905973 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -10,7 +10,7 @@ maintainers: - Geert Uytterhoeven description: | - On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module + On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module Standby Mode share the same register block. They provide the following functionalities: @@ -23,8 +23,9 @@ description: | properties: compatible: enum: - - renesas,r9a07g044-cpg # RZ/G2{L,LC} - - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g044-cpg # RZ/G2{L,LC} + - renesas,r9a07g054-cpg # RZ/V2L reg: maxItems: 1 From 2a214607e4a335f9ebfb08ae3bf7f2c905a0c9c9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 11:44:25 +0200 Subject: [PATCH 03/66] clk: renesas: r8a77990: Add RPC clocks Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/3295013f27f1e4b8fbf3f79b950d65157ea95ef2.1648546700.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index d34d97baab35f..a5c95e0021f82 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -44,6 +44,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, CLK_OCO, @@ -74,6 +75,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -107,6 +110,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), + DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77990_CLK_RPC), + DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), @@ -215,6 +223,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), From 9d18f81b35355f63a39b04869d0a013194925d1a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 11:44:26 +0200 Subject: [PATCH 04/66] clk: renesas: r8a77995: Add RPC clocks Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a77995-cpg-mssr.c | 9 +++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 5 ++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 525eef197fd9a..22e7bf0de9fe1 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -42,6 +42,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_RINT, CLK_OCO, @@ -70,6 +71,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -106,6 +109,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268), DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268), + DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77995_CLK_RPC), + DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), @@ -174,6 +182,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 2bc0afadf6041..9028bf4295ce0 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -25,7 +25,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPCSRC, - CLK_TYPE_GEN3_E3_RPCSRC, + CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */ CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, @@ -62,6 +62,9 @@ enum rcar_gen3_clk_types { #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ (_parent0) << 16 | (_parent1), .div = 8) +#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ + (_parent0) << 16 | (_parent1), .div = 5) struct rcar_gen3_cpg_pll_config { u8 extal_div; From eb2789785428e2dbc3d5f413b16c67ff90d828c1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:30:34 +0100 Subject: [PATCH 05/66] dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev. 0.51, Nov. 2021). Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220402073037.23947-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g043-cpg.h | 184 ++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 include/dt-bindings/clock/r9a07g043-cpg.h diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h new file mode 100644 index 0000000000000..27e2327330967 --- /dev/null +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ + +#include + +/* R9A07G043 CPG Core Clocks */ +#define R9A07G043_CLK_I 0 +#define R9A07G043_CLK_I2 1 +#define R9A07G043_CLK_S0 2 +#define R9A07G043_CLK_SPI0 3 +#define R9A07G043_CLK_SPI1 4 +#define R9A07G043_CLK_SD0 5 +#define R9A07G043_CLK_SD1 6 +#define R9A07G043_CLK_M0 7 +#define R9A07G043_CLK_M2 8 +#define R9A07G043_CLK_M3 9 +#define R9A07G043_CLK_HP 10 +#define R9A07G043_CLK_TSU 11 +#define R9A07G043_CLK_ZT 12 +#define R9A07G043_CLK_P0 13 +#define R9A07G043_CLK_P1 14 +#define R9A07G043_CLK_P2 15 +#define R9A07G043_CLK_AT 16 +#define R9A07G043_OSCCLK 17 +#define R9A07G043_CLK_P0_DIV2 18 + +/* R9A07G043 Module Clocks */ +#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */ +#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */ +#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */ +#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */ +#define R9A07G043_SYC_CNT_CLK 11 +#define R9A07G043_DMAC_ACLK 12 +#define R9A07G043_DMAC_PCLK 13 +#define R9A07G043_OSTM0_PCLK 14 +#define R9A07G043_OSTM1_PCLK 15 +#define R9A07G043_OSTM2_PCLK 16 +#define R9A07G043_MTU_X_MCK_MTU3 17 +#define R9A07G043_POE3_CLKM_POE 18 +#define R9A07G043_WDT0_PCLK 19 +#define R9A07G043_WDT0_CLK 20 +#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */ +#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */ +#define R9A07G043_SPI_CLK2 23 +#define R9A07G043_SPI_CLK 24 +#define R9A07G043_SDHI0_IMCLK 25 +#define R9A07G043_SDHI0_IMCLK2 26 +#define R9A07G043_SDHI0_CLK_HS 27 +#define R9A07G043_SDHI0_ACLK 28 +#define R9A07G043_SDHI1_IMCLK 29 +#define R9A07G043_SDHI1_IMCLK2 30 +#define R9A07G043_SDHI1_CLK_HS 31 +#define R9A07G043_SDHI1_ACLK 32 +#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */ +#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */ +#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_PCLK2 42 +#define R9A07G043_SSI0_PCLK_SFR 43 +#define R9A07G043_SSI1_PCLK2 44 +#define R9A07G043_SSI1_PCLK_SFR 45 +#define R9A07G043_SSI2_PCLK2 46 +#define R9A07G043_SSI2_PCLK_SFR 47 +#define R9A07G043_SSI3_PCLK2 48 +#define R9A07G043_SSI3_PCLK_SFR 49 +#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HCLK 51 +#define R9A07G043_USB_U2H1_HCLK 52 +#define R9A07G043_USB_U2P_EXR_CPUCLK 53 +#define R9A07G043_USB_PCLK 54 +#define R9A07G043_ETH0_CLK_AXI 55 +#define R9A07G043_ETH0_CLK_CHI 56 +#define R9A07G043_ETH1_CLK_AXI 57 +#define R9A07G043_ETH1_CLK_CHI 58 +#define R9A07G043_I2C0_PCLK 59 +#define R9A07G043_I2C1_PCLK 60 +#define R9A07G043_I2C2_PCLK 61 +#define R9A07G043_I2C3_PCLK 62 +#define R9A07G043_SCIF0_CLK_PCK 63 +#define R9A07G043_SCIF1_CLK_PCK 64 +#define R9A07G043_SCIF2_CLK_PCK 65 +#define R9A07G043_SCIF3_CLK_PCK 66 +#define R9A07G043_SCIF4_CLK_PCK 67 +#define R9A07G043_SCI0_CLKP 68 +#define R9A07G043_SCI1_CLKP 69 +#define R9A07G043_IRDA_CLKP 70 +#define R9A07G043_RSPI0_CLKB 71 +#define R9A07G043_RSPI1_CLKB 72 +#define R9A07G043_RSPI2_CLKB 73 +#define R9A07G043_CANFD_PCLK 74 +#define R9A07G043_GPIO_HCLK 75 +#define R9A07G043_ADC_ADCLK 76 +#define R9A07G043_ADC_PCLK 77 +#define R9A07G043_TSU_PCLK 78 + +/* R9A07G043 Resets */ +#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */ +#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */ +#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */ +#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */ +#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */ +#define R9A07G043_DMAC_ARESETN 17 +#define R9A07G043_DMAC_RST_ASYNC 18 +#define R9A07G043_SYC_RESETN 19 +#define R9A07G043_OSTM0_PRESETZ 20 +#define R9A07G043_OSTM1_PRESETZ 21 +#define R9A07G043_OSTM2_PRESETZ 22 +#define R9A07G043_MTU_X_PRESET_MTU3 23 +#define R9A07G043_POE3_RST_M_REG 24 +#define R9A07G043_WDT0_PRESETN 25 +#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */ +#define R9A07G043_SPI_RST 27 +#define R9A07G043_SDHI0_IXRST 28 +#define R9A07G043_SDHI1_IXRST 29 +#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */ +#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */ +#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */ +#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */ +#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */ +#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */ +#define R9A07G043_SSI0_RST_M2_REG 36 +#define R9A07G043_SSI1_RST_M2_REG 37 +#define R9A07G043_SSI2_RST_M2_REG 38 +#define R9A07G043_SSI3_RST_M2_REG 39 +#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */ +#define R9A07G043_USB_U2H0_HRESETN 41 +#define R9A07G043_USB_U2H1_HRESETN 42 +#define R9A07G043_USB_U2P_EXL_SYSRST 43 +#define R9A07G043_USB_PRESETN 44 +#define R9A07G043_ETH0_RST_HW_N 45 +#define R9A07G043_ETH1_RST_HW_N 46 +#define R9A07G043_I2C0_MRST 47 +#define R9A07G043_I2C1_MRST 48 +#define R9A07G043_I2C2_MRST 49 +#define R9A07G043_I2C3_MRST 50 +#define R9A07G043_SCIF0_RST_SYSTEM_N 51 +#define R9A07G043_SCIF1_RST_SYSTEM_N 52 +#define R9A07G043_SCIF2_RST_SYSTEM_N 53 +#define R9A07G043_SCIF3_RST_SYSTEM_N 54 +#define R9A07G043_SCIF4_RST_SYSTEM_N 55 +#define R9A07G043_SCI0_RST 56 +#define R9A07G043_SCI1_RST 57 +#define R9A07G043_IRDA_RST 58 +#define R9A07G043_RSPI0_RST 59 +#define R9A07G043_RSPI1_RST 60 +#define R9A07G043_RSPI2_RST 61 +#define R9A07G043_CANFD_RSTP_N 62 +#define R9A07G043_CANFD_RSTC_N 63 +#define R9A07G043_GPIO_RSTN 64 +#define R9A07G043_GPIO_PORT_RESETN 65 +#define R9A07G043_GPIO_SPARE_RESETN 66 +#define R9A07G043_ADC_PRESETN 67 +#define R9A07G043_ADC_ADRST_N 68 +#define R9A07G043_TSU_PRESETN 69 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ From 29db30c45f07c929c86c40a5b85f18b69c89c638 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Feb 2022 17:25:20 +0100 Subject: [PATCH 06/66] clk: renesas: rzg2l: Simplify multiplication/shift logic "a * (1 << b)" == "a << b". No change in generated code. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b3a1533970e56..f626d27044771 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) * (1 << SDIV(val2)); + div = PDIV(val1) << SDIV(val2); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); } From 880c3fa319b24c1a8ccb4dfc171a3329ad14943a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Apr 2022 14:59:44 +0200 Subject: [PATCH 07/66] clk: renesas: Move RPC core clocks The RPC and RPCD2 core clocks were added to the sections for internal core clocks, while they are core clock outputs, visible from DT. Move them to the correct sections. Rename the ".rpc" clock on R-Car S4 to "rpc". Fixup nearby whitespace to increase uniformity. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 9 ++++----- drivers/clk/renesas/r8a774b1-cpg-mssr.c | 9 ++++----- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 8 +++----- drivers/clk/renesas/r8a774e1-cpg-mssr.c | 9 ++++----- drivers/clk/renesas/r8a7795-cpg-mssr.c | 9 ++++----- drivers/clk/renesas/r8a7796-cpg-mssr.c | 9 ++++----- drivers/clk/renesas/r8a77965-cpg-mssr.c | 9 ++++----- drivers/clk/renesas/r8a77980-cpg-mssr.c | 10 +++++----- drivers/clk/renesas/r8a77990-cpg-mssr.c | 6 ++---- drivers/clk/renesas/r8a77995-cpg-mssr.c | 10 ++++------ drivers/clk/renesas/r8a779a0-cpg-mssr.c | 11 +++++++---- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 9 ++++++--- 12 files changed, 51 insertions(+), 57 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 95dd56b64d640..ad03c09ebc1f9 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774A1_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), + DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC), + DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A774A1_CLK_CPEX, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index 56061b9b8437d..ab087b02ef90e 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -66,12 +66,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774B1_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -106,6 +102,9 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), + DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC), + DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index b5eb5dc45d62e..c9c8fde0f0a6c 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), - DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774C0_CLK_RPC), - DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -108,6 +103,9 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1), + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC), + DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074), DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078), DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c), diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index 2950f0db90aeb..a790061db877c 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774E1_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c), + DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC), + DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 991a44315d715..301475c74f500 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -71,12 +71,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A7795_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -113,6 +109,9 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), + DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC), + DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 7950313611efa..c4969318508eb 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -73,12 +73,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A7796_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -115,6 +111,9 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), + DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC), + DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index d687c29efa3ce..78f6e530848ec 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -69,12 +69,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77965_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -110,6 +106,9 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c), + DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC), + DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index f3cd64de4dc6e..06f925aff407b 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -66,13 +66,10 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_RATE(".oco", CLK_OCO, 32768), - DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77980_CLK_RPC), + DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), @@ -99,6 +96,9 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074), DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074), + DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC), + DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1), diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index a5c95e0021f82..b666d099365ef 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -110,10 +110,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), - DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77990_CLK_RPC), + DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 22e7bf0de9fe1..24ba9093a72f7 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -106,13 +106,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), - DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268), + DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268), - DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77995_CLK_RPC), + DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC), DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index fadd8a1718c66..fb84f7b51f61c 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -85,11 +85,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), + DEF_RATE(".oco", CLK_OCO, 32768), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), - DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), - DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, - R8A779A0_CLK_RPC), + + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), /* Core Clock Outputs */ DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0), @@ -120,6 +119,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), + DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, + R8A779A0_CLK_RPC), + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 76b4419650377..08e8d95ce5e7e 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -70,12 +70,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), DEF_RATE(".oco", CLK_OCO, 32768), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), - DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), - DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), /* Core Clock Outputs */ DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), @@ -108,6 +107,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870), + + DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), From c8b088224c25ef4f5270f9de6a3516181b63f38c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 12 Apr 2022 17:13:12 +0100 Subject: [PATCH 08/66] clk: renesas: Add support for RZ/G2UL SoC The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g043-cpg.c | 157 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 ++ drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a07g043-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index c281f3af57169..a95ed8f310da6 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -33,6 +33,7 @@ config CLK_RENESAS select CLK_R8A779A0 if ARCH_R8A779A0 select CLK_R8A779F0 if ARCH_R8A779F0 select CLK_R9A06G032 if ARCH_R9A06G032 + select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_SH73A0 if ARCH_SH73A0 @@ -160,6 +161,10 @@ config CLK_R8A779F0 config CLK_R9A06G032 bool "RZ/N1D clock support" if COMPILE_TEST +config CLK_R9A07G043 + bool "RZ/G2UL clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_R9A07G044 bool "RZ/G2L clock support" if COMPILE_TEST select CLK_RZG2L @@ -200,7 +205,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector config CLK_RZG2L - bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST + bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER # Generic diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d5e571699a306..ca3a9bbcf27ac 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o +obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c new file mode 100644 index 0000000000000..81409ff37e2ea --- /dev/null +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G2UL CPG driver + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_OSC_DIV1000, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL2_DIV2_8, + CLK_PLL3, + CLK_PLL3_DIV2, + CLK_PLL3_DIV2_4, + CLK_PLL3_DIV2_4_2, + CLK_PLL5, + CLK_PLL6, + CLK_P1_DIV2, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_1_8[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + +static const struct clk_div_table dtable_1_32[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {4, 32}, + {0, 0}, +}; + +static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), + DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + + /* Core output clk */ + DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, + dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, + DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), + DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, + DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), +}; + +static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { + DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, + 0x514, 0), + DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, + 0x518, 0), + DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, + 0x518, 1), + DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, + 0x52c, 0), + DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, + 0x52c, 1), + DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, + 0x584, 0), + DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, + 0x584, 1), + DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, + 0x584, 2), + DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, + 0x584, 3), + DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, + 0x584, 4), + DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, + 0x588, 0), + DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, + 0x588, 1), +}; + +static struct rzg2l_reset r9a07g043_resets[] = { + DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), + DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), + DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), + DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), + DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), + DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), + DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), + DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), +}; + +static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, + MOD_CLK_BASE + R9A07G043_IA55_CLK, + MOD_CLK_BASE + R9A07G043_DMAC_ACLK, +}; + +const struct rzg2l_cpg_info r9a07g043_cpg_info = { + /* Core Clocks */ + .core_clks = r9a07g043_core_clks, + .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a07g043_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a07g043_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), + .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, + + /* Resets */ + .resets = r9a07g043_resets, + .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index f626d27044771..1ce35f65682b4 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -945,6 +945,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) } static const struct of_device_id rzg2l_cpg_match[] = { +#ifdef CONFIG_CLK_R9A07G043 + { + .compatible = "renesas,r9a07g043-cpg", + .data = &r9a07g043_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A07G044 { .compatible = "renesas,r9a07g044-cpg", diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index ce657beaf1601..92c88f42ca7fa 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -202,6 +202,7 @@ struct rzg2l_cpg_info { unsigned int num_crit_mod_clks; }; +extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; From 6c185664b3d481292c41fbfe66ea19c84cb0237a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:46:23 +0100 Subject: [PATCH 09/66] clk: renesas: r9a07g043: Add GPIO clock and reset entries Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 81409ff37e2ea..0c574e153d4d7 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -112,6 +112,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x588, 0), DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 0x588, 1), + DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, + 0x598, 0), }; static struct rzg2l_reset r9a07g043_resets[] = { @@ -127,6 +129,9 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), + DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { From f201eb84450f98decb1834e73409bb2271441dd7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:46:24 +0100 Subject: [PATCH 10/66] clk: renesas: r9a07g043: Add ethernet clock sources Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 0c574e153d4d7..b9011bc7fe491 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -32,7 +32,10 @@ enum clk_ids { CLK_PLL3_DIV2_4, CLK_PLL3_DIV2_4_2, CLK_PLL5, + CLK_PLL5_500, + CLK_PLL5_250, CLK_PLL6, + CLK_PLL6_250, CLK_P1_DIV2, /* Module Clocks */ @@ -57,6 +60,9 @@ static const struct clk_div_table dtable_1_32[] = { {0, 0}, }; +/* Mux clock tables */ +static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; + static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -73,7 +79,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), + DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), + DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), /* Core output clk */ DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, @@ -85,6 +94,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), + DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), }; static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { From e11f804afc12e1c622f0a6f966fafd05b7022f8a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:46:25 +0100 Subject: [PATCH 11/66] clk: renesas: r9a07g043: Add GbEthernet clock/reset Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index b9011bc7fe491..03a00ec5ebf3a 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -111,6 +111,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), + DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, + 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, + 0x57c, 0), + DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, + 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, + 0x57c, 1), DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 0x584, 0), DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, @@ -135,6 +143,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), + DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), From 59086e4193f4fc920a23d2045a473f62450b4269 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 08:46:26 +0100 Subject: [PATCH 12/66] clk: renesas: r9a07g043: Add SDHI clock and reset entries Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 03a00ec5ebf3a..2d6c96789f5c2 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -37,6 +37,12 @@ enum clk_ids { CLK_PLL6, CLK_PLL6_250, CLK_P1_DIV2, + CLK_PLL2_800, + CLK_PLL2_SDHI_533, + CLK_PLL2_SDHI_400, + CLK_PLL2_SDHI_266, + CLK_SD0_DIV4, + CLK_SD1_DIV4, /* Module Clocks */ MOD_CLK_BASE, @@ -62,6 +68,7 @@ static const struct clk_div_table dtable_1_32[] = { /* Mux clock tables */ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; +static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { /* External Clock Inputs */ @@ -73,6 +80,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), + DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), + DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), @@ -98,6 +109,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), + DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, + sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, + sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), + DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), }; static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { @@ -111,6 +128,22 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), + DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, + 0x554, 0), + DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, + 0x554, 1), + DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, + 0x554, 2), + DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, + 0x554, 3), + DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, + 0x554, 4), + DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, + 0x554, 5), + DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, + 0x554, 6), + DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, + 0x554, 7), DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 0x57c, 0), DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, @@ -143,6 +176,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), From bab79506fd16dd36e3b9012ed0d882c15a3a0eb8 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 18 Apr 2022 15:15:37 +0100 Subject: [PATCH 13/66] clk: actions: remove redundant assignment after a mask operation The assignment operation after a & mask operation is redundant, the &= operator can be replaced with just the & operator. Cleans up a clang-scan warning: drivers/clk/actions/owl-pll.c:28:9: warning: Although the value stored to 'mul' is used in the enclosing expression, the value is never actually read from 'mul' [deadcode.DeadStores] Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20220418141537.83994-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd --- drivers/clk/actions/owl-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c index 02437bdedf4db..155f313986b40 100644 --- a/drivers/clk/actions/owl-pll.c +++ b/drivers/clk/actions/owl-pll.c @@ -25,7 +25,7 @@ static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) else if (mul > pll_hw->max_mul) mul = pll_hw->max_mul; - return mul &= mul_mask(pll_hw); + return mul & mul_mask(pll_hw); } static unsigned long _get_table_rate(const struct clk_pll_table *table, From 3196a605659dcf7ea2a4442edf704aa0edc6e559 Mon Sep 17 00:00:00 2001 From: Minghao Chi Date: Mon, 18 Apr 2022 11:04:55 +0000 Subject: [PATCH 14/66] clk: using pm_runtime_resume_and_get instead of pm_runtime_get_sync Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by: Zeal Robot Signed-off-by: Minghao Chi Link: https://lore.kernel.org/r/20220418110455.2559264-1-chi.minghao@zte.com.cn [sboyd@kernel.org: Drop local ret variable too] Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ed119182aa1be..f00d4c1158d72 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -108,17 +108,10 @@ struct clk { /*** runtime pm ***/ static int clk_pm_runtime_get(struct clk_core *core) { - int ret; - if (!core->rpm_enabled) return 0; - ret = pm_runtime_get_sync(core->dev); - if (ret < 0) { - pm_runtime_put_noidle(core->dev); - return ret; - } - return 0; + return pm_runtime_resume_and_get(core->dev); } static void clk_pm_runtime_put(struct clk_core *core) From 038010bb30684c0219fa4f93a13149038f28291a Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 14 Mar 2022 09:44:03 +0100 Subject: [PATCH 15/66] dt-bindings: Add en7523-scu device tree binding documentation Adds device tree binding documentation for clocks in the EN7523 SOC. Reviewed-by: Rob Herring Signed-off-by: John Crispin Signed-off-by: Felix Fietkau Link: https://lore.kernel.org/r/20220314084409.84394-2-nbd@nbd.name Signed-off-by: Stephen Boyd --- .../bindings/clock/airoha,en7523-scu.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/en7523-clk.h | 17 ++++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 include/dt-bindings/clock/en7523-clk.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml new file mode 100644 index 0000000000000..d60e746548097 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EN7523 Clock Device Tree Bindings + +maintainers: + - Felix Fietkau + - John Crispin + +description: | + This node defines the System Control Unit of the EN7523 SoC, + a collection of registers configuring many different aspects of the SoC. + + The clock driver uses it to read and configure settings of the + PLL controller, which provides clocks for the CPU, the bus and + other SoC internal peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify which clock they consume. + + All these identifiers can be found in: + [1]: . + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: airoha,en7523-scu + + reg: + maxItems: 2 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h new file mode 100644 index 0000000000000..717d23a5e5aef --- /dev/null +++ b/include/dt-bindings/clock/en7523-clk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ +#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ + +#define EN7523_CLK_GSW 0 +#define EN7523_CLK_EMI 1 +#define EN7523_CLK_BUS 2 +#define EN7523_CLK_SLIC 3 +#define EN7523_CLK_SPI 4 +#define EN7523_CLK_NPU 5 +#define EN7523_CLK_CRYPTO 6 +#define EN7523_CLK_PCIE 7 + +#define EN7523_NUM_CLOCKS 8 + +#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ From 1e627317919066386d089aaca1aab77bc5200c02 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 14 Mar 2022 09:44:04 +0100 Subject: [PATCH 16/66] clk: en7523: Add clock driver for Airoha EN7523 SoC This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau Link: https://lore.kernel.org/r/20220314084409.84394-3-nbd@nbd.name Reviewed-by: Matthias Brugger Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/clk-en7523.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5d596e778ff49..3148d14702df7 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -210,6 +210,15 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_EN7523 + bool "Clock driver for Airoha EN7523 SoC system clocks" + depends on OF + depends on ARCH_AIROHA || COMPILE_TEST + default ARCH_AIROHA + help + This driver provides the fixed clocks and gates present on Airoha + ARM silicon. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2bd5ffd595bf3..594d8b32c4573 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c new file mode 100644 index 0000000000000..076a70c2e1738 --- /dev/null +++ b/drivers/clk/clk-en7523.c @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +#define REG_PCI_CONTROL 0x88 +#define REG_PCI_CONTROL_PERSTOUT BIT(29) +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) +#define REG_GSW_CLK_DIV_SEL 0x1b4 +#define REG_EMI_CLK_DIV_SEL 0x1b8 +#define REG_BUS_CLK_DIV_SEL 0x1bc +#define REG_SPI_CLK_DIV_SEL 0x1c4 +#define REG_SPI_CLK_FREQ_SEL 0x1c8 +#define REG_NPU_CLK_DIV_SEL 0x1fc +#define REG_CRYPTO_CLKSRC 0x200 +#define REG_RESET_CONTROL 0x834 +#define REG_RESET_CONTROL_PCIEHB BIT(29) +#define REG_RESET_CONTROL_PCIE1 BIT(27) +#define REG_RESET_CONTROL_PCIE2 BIT(26) + +struct en_clk_desc { + int id; + const char *name; + u32 base_reg; + u8 base_bits; + u8 base_shift; + union { + const unsigned int *base_values; + unsigned int base_value; + }; + size_t n_base_values; + + u16 div_reg; + u8 div_bits; + u8 div_shift; + u16 div_val0; + u8 div_step; +}; + +struct en_clk_gate { + void __iomem *base; + struct clk_hw hw; +}; + +static const u32 gsw_base[] = { 400000000, 500000000 }; +static const u32 emi_base[] = { 333000000, 400000000 }; +static const u32 bus_base[] = { 500000000, 540000000 }; +static const u32 slic_base[] = { 100000000, 3125000 }; +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; + +static const struct en_clk_desc en7523_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu_base, + .n_base_values = ARRAY_SIZE(npu_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + } +}; + +static const struct of_device_id of_match_clk_en7523[] = { + { .compatible = "airoha,en7523-scu", }, + { /* sentinel */ } +}; + +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val; + + if (!desc->base_bits) + return desc->base_value; + + val = readl(base + desc->base_reg); + val >>= desc->base_shift; + val &= (1 << desc->base_bits) - 1; + + if (val >= desc->n_base_values) + return 0; + + return desc->base_values[val]; +} + +static u32 en7523_get_div(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg, val; + + if (!desc->div_bits) + return 1; + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + val = readl(base + reg); + val >>= desc->div_shift; + val &= (1 << desc->div_bits) - 1; + + if (!val && desc->div_val0) + return desc->div_val0; + + return (val + 1) * desc->div_step; +} + +static int en7523_pci_is_enabled(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); +} + +static int en7523_pci_prepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val, mask; + + /* Need to pull device low before reset */ + val = readl(np_base + REG_PCI_CONTROL); + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Enable PCIe port 1 */ + val |= REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Reset to default */ + val = readl(np_base + REG_RESET_CONTROL); + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | + REG_RESET_CONTROL_PCIEHB; + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_RESET_CONTROL); + msleep(100); + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(5000, 10000); + + /* Release device */ + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; + val = readl(np_base + REG_PCI_CONTROL); + writel(val & ~mask, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_PCI_CONTROL); + msleep(250); + + return 0; +} + +static void en7523_pci_unprepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val; + + val = readl(np_base + REG_PCI_CONTROL); + val &= ~REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); +} + +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, + void __iomem *np_base) +{ + static const struct clk_ops pcie_gate_ops = { + .is_enabled = en7523_pci_is_enabled, + .prepare = en7523_pci_prepare, + .unprepare = en7523_pci_unprepare, + }; + struct clk_init_data init = { + .name = "pcie", + .ops = &pcie_gate_ops, + }; + struct en_clk_gate *cg; + + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); + if (!cg) + return NULL; + + cg->base = np_base; + cg->hw.init = &init; + en7523_pci_unprepare(&cg->hw); + + if (clk_hw_register(dev, &cg->hw)) + return NULL; + + return &cg->hw; +} + +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + void __iomem *base, void __iomem *np_base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + + rate = en7523_get_base_rate(base, i); + rate /= en7523_get_div(base, i); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, np_base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + +static int en7523_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + void __iomem *base, *np_base; + int r; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return PTR_ERR(np_base); + + clk_data = devm_kzalloc(&pdev->dev, + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_en7523_drv = { + .probe = en7523_clk_probe, + .driver = { + .name = "clk-en7523", + .of_match_table = of_match_clk_en7523, + .suppress_bind_attrs = true, + }, +}; + +static int __init clk_en7523_init(void) +{ + return platform_driver_register(&clk_en7523_drv); +} + +arch_initcall(clk_en7523_init); From f9edf134d75d78d3e54f3a13d9d493e86c0599fa Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:22 +0200 Subject: [PATCH 17/66] clk: cdce706: use simple i2c probe function The i2c probe function here doesn't use the id information provided in its second argument, so the single-parameter i2c probe function ("probe_new") can be used instead. This avoids scanning the identifier tables during probes. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-2-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-cdce706.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-cdce706.c b/drivers/clk/clk-cdce706.c index c91e9096b070e..5467d941ddfd0 100644 --- a/drivers/clk/clk-cdce706.c +++ b/drivers/clk/clk-cdce706.c @@ -627,8 +627,7 @@ of_clk_cdce_get(struct of_phandle_args *clkspec, void *data) return &cdce->clkout[idx].hw; } -static int cdce706_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int cdce706_probe(struct i2c_client *client) { struct i2c_adapter *adapter = client->adapter; struct cdce706_dev_data *cdce; @@ -692,7 +691,7 @@ static struct i2c_driver cdce706_i2c_driver = { .name = "cdce706", .of_match_table = of_match_ptr(cdce706_dt_match), }, - .probe = cdce706_probe, + .probe_new = cdce706_probe, .remove = cdce706_remove, .id_table = cdce706_id, }; From df221682075d174e04cbbded27a25c64fedc3526 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:23 +0200 Subject: [PATCH 18/66] clk: cdce925: use i2c_match_id and simple i2c probe As part of the ongoing i2c transition to the simple probe ("probe_new"), this patch uses i2c_match_id to retrieve the driver_data for the probed device. The id parameter is thus no longer necessary and the simple probe can be used instead. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-3-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-cdce925.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c index 308b353815e17..ef9a2d44e40c3 100644 --- a/drivers/clk/clk-cdce925.c +++ b/drivers/clk/clk-cdce925.c @@ -634,11 +634,20 @@ static struct regmap_bus regmap_cdce925_bus = { .read = cdce925_regmap_i2c_read, }; -static int cdce925_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static const struct i2c_device_id cdce925_id[] = { + { "cdce913", CDCE913 }, + { "cdce925", CDCE925 }, + { "cdce937", CDCE937 }, + { "cdce949", CDCE949 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, cdce925_id); + +static int cdce925_probe(struct i2c_client *client) { struct clk_cdce925_chip *data; struct device_node *node = client->dev.of_node; + const struct i2c_device_id *id = i2c_match_id(cdce925_id, client); const char *parent_name; const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,}; struct clk_init_data init; @@ -814,15 +823,6 @@ static int cdce925_probe(struct i2c_client *client, return err; } -static const struct i2c_device_id cdce925_id[] = { - { "cdce913", CDCE913 }, - { "cdce925", CDCE925 }, - { "cdce937", CDCE937 }, - { "cdce949", CDCE949 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, cdce925_id); - static const struct of_device_id clk_cdce925_of_match[] = { { .compatible = "ti,cdce913" }, { .compatible = "ti,cdce925" }, @@ -837,7 +837,7 @@ static struct i2c_driver cdce925_driver = { .name = "cdce925", .of_match_table = of_match_ptr(clk_cdce925_of_match), }, - .probe = cdce925_probe, + .probe_new = cdce925_probe, .id_table = cdce925_id, }; module_i2c_driver(cdce925_driver); From eb5f909ac9e7a1e0c77b6a3b1514a4941efdefb5 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:24 +0200 Subject: [PATCH 19/66] clk: cs2000-cp: use simple i2c probe function The i2c probe function here doesn't use the id information provided in its second argument, so the single-parameter i2c probe function ("probe_new") can be used instead. This avoids scanning the identifier tables during probes. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-4-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-cs2000-cp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index dc5040a84dcc9..aa5c72bab83ea 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -570,8 +570,7 @@ static int cs2000_remove(struct i2c_client *client) return 0; } -static int cs2000_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int cs2000_probe(struct i2c_client *client) { struct cs2000_priv *priv; struct device *dev = &client->dev; @@ -625,7 +624,7 @@ static struct i2c_driver cs2000_driver = { .pm = &cs2000_pm_ops, .of_match_table = cs2000_of_match, }, - .probe = cs2000_probe, + .probe_new = cs2000_probe, .remove = cs2000_remove, .id_table = cs2000_id, }; From 55349aedb5daa5ca8f14e485d069b0bb6ea483d5 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:25 +0200 Subject: [PATCH 20/66] clk: max9485: use simple i2c probe function The i2c probe function here doesn't use the id information provided in its second argument, so the single-parameter i2c probe function ("probe_new") can be used instead. This avoids scanning the identifier tables during probes. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-5-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-max9485.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-max9485.c b/drivers/clk/clk-max9485.c index 5e80f3d090f34..5f85b0a32872a 100644 --- a/drivers/clk/clk-max9485.c +++ b/drivers/clk/clk-max9485.c @@ -254,8 +254,7 @@ max9485_of_clk_get(struct of_phandle_args *clkspec, void *data) return &drvdata->hw[idx].hw; } -static int max9485_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int max9485_i2c_probe(struct i2c_client *client) { struct max9485_driver_data *drvdata; struct device *dev = &client->dev; @@ -377,7 +376,7 @@ static struct i2c_driver max9485_driver = { .pm = &max9485_pm_ops, .of_match_table = max9485_dt_ids, }, - .probe = max9485_i2c_probe, + .probe_new = max9485_i2c_probe, .id_table = max9485_i2c_ids, }; module_i2c_driver(max9485_driver); From d8703ce85e7c7afbb9df736e75138a32e1cba164 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:26 +0200 Subject: [PATCH 21/66] clk: si514: use simple i2c probe function The i2c probe function here doesn't use the id information provided in its second argument, so the single-parameter i2c probe function ("probe_new") can be used instead. This avoids scanning the identifier tables during probes. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-6-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-si514.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-si514.c b/drivers/clk/clk-si514.c index 364b62b9928d3..4481c4303534f 100644 --- a/drivers/clk/clk-si514.c +++ b/drivers/clk/clk-si514.c @@ -327,8 +327,7 @@ static const struct regmap_config si514_regmap_config = { .volatile_reg = si514_regmap_is_volatile, }; -static int si514_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int si514_probe(struct i2c_client *client) { struct clk_si514 *data; struct clk_init_data init; @@ -394,7 +393,7 @@ static struct i2c_driver si514_driver = { .name = "si514", .of_match_table = clk_si514_of_match, }, - .probe = si514_probe, + .probe_new = si514_probe, .remove = si514_remove, .id_table = si514_id, }; From adc00f60c829b1d759b16f4f928764c92286d399 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:27 +0200 Subject: [PATCH 22/66] clk: si5341: use simple i2c probe function The i2c probe function here doesn't use the id information provided in its second argument, so the single-parameter i2c probe function ("probe_new") can be used instead. This avoids scanning the identifier tables during probes. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-7-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-si5341.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c index 41851f41b6821..4bca732126628 100644 --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c @@ -1547,8 +1547,7 @@ static const struct attribute *si5341_attributes[] = { NULL }; -static int si5341_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int si5341_probe(struct i2c_client *client) { struct clk_si5341 *data; struct clk_init_data init; @@ -1837,7 +1836,7 @@ static struct i2c_driver si5341_driver = { .name = "si5341", .of_match_table = clk_si5341_of_match, }, - .probe = si5341_probe, + .probe_new = si5341_probe, .remove = si5341_remove, .id_table = si5341_id, }; From ca3ebd20d956951e4b0633b9ee5342271728e840 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:28 +0200 Subject: [PATCH 23/66] clk: si5351: use i2c_match_id and simple i2c probe As part of the ongoing i2c transition to the simple probe ("probe_new"), this patch uses i2c_match_id to retrieve the driver_data for the probed device. The id parameter is thus no longer necessary and the simple probe can be used instead. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-8-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-si5351.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 93fa8c9e11be0..b9f088c4ba2f5 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -1367,9 +1367,18 @@ si53351_of_clk_get(struct of_phandle_args *clkspec, void *data) } #endif /* CONFIG_OF */ -static int si5351_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static const struct i2c_device_id si5351_i2c_ids[] = { + { "si5351a", SI5351_VARIANT_A }, + { "si5351a-msop", SI5351_VARIANT_A3 }, + { "si5351b", SI5351_VARIANT_B }, + { "si5351c", SI5351_VARIANT_C }, + { } +}; +MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids); + +static int si5351_i2c_probe(struct i2c_client *client) { + const struct i2c_device_id *id = i2c_match_id(si5351_i2c_ids, client); enum si5351_variant variant = (enum si5351_variant)id->driver_data; struct si5351_platform_data *pdata; struct si5351_driver_data *drvdata; @@ -1649,21 +1658,12 @@ static int si5351_i2c_remove(struct i2c_client *client) return 0; } -static const struct i2c_device_id si5351_i2c_ids[] = { - { "si5351a", SI5351_VARIANT_A }, - { "si5351a-msop", SI5351_VARIANT_A3 }, - { "si5351b", SI5351_VARIANT_B }, - { "si5351c", SI5351_VARIANT_C }, - { } -}; -MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids); - static struct i2c_driver si5351_driver = { .driver = { .name = "si5351", .of_match_table = of_match_ptr(si5351_dt_ids), }, - .probe = si5351_i2c_probe, + .probe_new = si5351_i2c_probe, .remove = si5351_i2c_remove, .id_table = si5351_i2c_ids, }; From 32a5c1d383780f4ad4455f0d79ab999377f06a48 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:29 +0200 Subject: [PATCH 24/66] clk: si544: use i2c_match_id and simple i2c probe As part of the ongoing i2c transition to the simple probe ("probe_new"), this patch uses i2c_match_id to retrieve the driver_data for the probed device. The id parameter is thus no longer necessary and the simple probe can be used instead. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-9-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-si544.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c index d9ec9086184df..089786907641e 100644 --- a/drivers/clk/clk-si544.c +++ b/drivers/clk/clk-si544.c @@ -451,11 +451,19 @@ static const struct regmap_config si544_regmap_config = { .volatile_reg = si544_regmap_is_volatile, }; -static int si544_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static const struct i2c_device_id si544_id[] = { + { "si544a", si544a }, + { "si544b", si544b }, + { "si544c", si544c }, + { } +}; +MODULE_DEVICE_TABLE(i2c, si544_id); + +static int si544_probe(struct i2c_client *client) { struct clk_si544 *data; struct clk_init_data init; + const struct i2c_device_id *id = i2c_match_id(si544_id, client); int err; data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); @@ -499,14 +507,6 @@ static int si544_probe(struct i2c_client *client, return 0; } -static const struct i2c_device_id si544_id[] = { - { "si544a", si544a }, - { "si544b", si544b }, - { "si544c", si544c }, - { } -}; -MODULE_DEVICE_TABLE(i2c, si544_id); - static const struct of_device_id clk_si544_of_match[] = { { .compatible = "silabs,si544a" }, { .compatible = "silabs,si544b" }, @@ -520,7 +520,7 @@ static struct i2c_driver si544_driver = { .name = "si544", .of_match_table = clk_si544_of_match, }, - .probe = si544_probe, + .probe_new = si544_probe, .id_table = si544_id, }; module_i2c_driver(si544_driver); From 2b349b893def67fd3146055d720597d9cbef26be Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:30 +0200 Subject: [PATCH 25/66] clk: si570: use i2c_match_id and simple i2c probe As part of the ongoing i2c transition to the simple probe ("probe_new"), this patch uses i2c_match_id to retrieve the driver_data for the probed device. The id parameter is thus no longer necessary and the simple probe can be used instead. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-10-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-si570.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c index eea50121718a6..1ff8f32f734dc 100644 --- a/drivers/clk/clk-si570.c +++ b/drivers/clk/clk-si570.c @@ -398,11 +398,20 @@ static const struct regmap_config si570_regmap_config = { .volatile_reg = si570_regmap_is_volatile, }; -static int si570_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static const struct i2c_device_id si570_id[] = { + { "si570", si57x }, + { "si571", si57x }, + { "si598", si59x }, + { "si599", si59x }, + { } +}; +MODULE_DEVICE_TABLE(i2c, si570_id); + +static int si570_probe(struct i2c_client *client) { struct clk_si570 *data; struct clk_init_data init; + const struct i2c_device_id *id = i2c_match_id(si570_id, client); u32 initial_fout, factory_fout, stability; bool skip_recall; int err; @@ -495,15 +504,6 @@ static int si570_remove(struct i2c_client *client) return 0; } -static const struct i2c_device_id si570_id[] = { - { "si570", si57x }, - { "si571", si57x }, - { "si598", si59x }, - { "si599", si59x }, - { } -}; -MODULE_DEVICE_TABLE(i2c, si570_id); - static const struct of_device_id clk_si570_of_match[] = { { .compatible = "silabs,si570" }, { .compatible = "silabs,si571" }, @@ -518,7 +518,7 @@ static struct i2c_driver si570_driver = { .name = "si570", .of_match_table = clk_si570_of_match, }, - .probe = si570_probe, + .probe_new = si570_probe, .remove = si570_remove, .id_table = si570_id, }; From 5baa12cfc433ff514b05e289ef59b06a4de1ac16 Mon Sep 17 00:00:00 2001 From: Stephen Kitt Date: Thu, 7 Apr 2022 17:18:31 +0200 Subject: [PATCH 26/66] clk: renesas-pcie: use simple i2c probe function The i2c probe function here doesn't use the id information provided in its second argument, so the single-parameter i2c probe function ("probe_new") can be used instead. This avoids scanning the identifier tables during probes. Signed-off-by: Stephen Kitt Link: https://lore.kernel.org/r/20220407151831.2371706-11-steve@sk2.org Reviewed-by: Wolfram Sang Signed-off-by: Stephen Boyd --- drivers/clk/clk-renesas-pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 59d9cf0053ebb..4f5df1fc74b46 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -213,7 +213,7 @@ rs9_of_clk_get(struct of_phandle_args *clkspec, void *data) return rs9->clk_dif[idx]; } -static int rs9_probe(struct i2c_client *client, const struct i2c_device_id *id) +static int rs9_probe(struct i2c_client *client) { unsigned char name[5] = "DIF0"; struct rs9_driver_data *rs9; @@ -312,7 +312,7 @@ static struct i2c_driver rs9_driver = { .pm = &rs9_pm_ops, .of_match_table = clk_rs9_of_match, }, - .probe = rs9_probe, + .probe_new = rs9_probe, .id_table = rs9_id, }; module_i2c_driver(rs9_driver); From 90715507cb899df6c726494c0225d30130ad0cc5 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 25 Apr 2022 15:41:55 +0900 Subject: [PATCH 27/66] dt-bindings: power: Add r8a779g0 SYSC power domain definitions Add power domain indices for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/power/r8a779g0-sysc.h | 45 +++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h new file mode 100644 index 0000000000000..7daa70f1814e8 --- /dev/null +++ b/include/dt-bindings/power/r8a779g0-sysc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779G0_PD_A1E0D0C0 0 +#define R8A779G0_PD_A1E0D0C1 1 +#define R8A779G0_PD_A1E0D1C0 2 +#define R8A779G0_PD_A1E0D1C1 3 +#define R8A779G0_PD_A2E0D0 16 +#define R8A779G0_PD_A2E0D1 17 +#define R8A779G0_PD_A3E0 20 +#define R8A779G0_PD_A33DGA 24 +#define R8A779G0_PD_A23DGB 25 +#define R8A779G0_PD_A1DSP0 33 +#define R8A779G0_PD_A2IMP01 34 +#define R8A779G0_PD_A2PSC 35 +#define R8A779G0_PD_A2CV0 36 +#define R8A779G0_PD_A2CV1 37 +#define R8A779G0_PD_A1CNN0 41 +#define R8A779G0_PD_A2CN0 42 +#define R8A779G0_PD_A3IR 43 +#define R8A779G0_PD_A1DSP1 45 +#define R8A779G0_PD_A2IMP23 46 +#define R8A779G0_PD_A2DMA 47 +#define R8A779G0_PD_A2CV2 48 +#define R8A779G0_PD_A2CV3 49 +#define R8A779G0_PD_A1DSP2 53 +#define R8A779G0_PD_A1DSP3 54 +#define R8A779G0_PD_A3VIP0 56 +#define R8A779G0_PD_A3VIP1 57 +#define R8A779G0_PD_A3VIP2 58 +#define R8A779G0_PD_A3ISP0 60 +#define R8A779G0_PD_A3ISP1 61 + +/* Always-on power area */ +#define R8A779G0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/ From f2afa78d5a0c0b0b2461a5c532d7a84214a1b633 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 25 Apr 2022 15:41:56 +0900 Subject: [PATCH 28/66] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h new file mode 100644 index 0000000000000..754c54a6eb06a --- /dev/null +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ + +#include + +/* r8a779g0 CPG Core Clocks */ + +#define R8A779G0_CLK_ZX 0 +#define R8A779G0_CLK_ZS 1 +#define R8A779G0_CLK_ZT 2 +#define R8A779G0_CLK_ZTR 3 +#define R8A779G0_CLK_S0D2 4 +#define R8A779G0_CLK_S0D3 5 +#define R8A779G0_CLK_S0D4 6 +#define R8A779G0_CLK_S0D1_VIO 7 +#define R8A779G0_CLK_S0D2_VIO 8 +#define R8A779G0_CLK_S0D4_VIO 9 +#define R8A779G0_CLK_S0D8_VIO 10 +#define R8A779G0_CLK_S0D1_VC 11 +#define R8A779G0_CLK_S0D2_VC 12 +#define R8A779G0_CLK_S0D4_VC 13 +#define R8A779G0_CLK_S0D2_MM 14 +#define R8A779G0_CLK_S0D4_MM 15 +#define R8A779G0_CLK_S0D2_U3DG 16 +#define R8A779G0_CLK_S0D4_U3DG 17 +#define R8A779G0_CLK_S0D2_RT 18 +#define R8A779G0_CLK_S0D3_RT 19 +#define R8A779G0_CLK_S0D4_RT 20 +#define R8A779G0_CLK_S0D6_RT 21 +#define R8A779G0_CLK_S0D24_RT 22 +#define R8A779G0_CLK_S0D2_PER 23 +#define R8A779G0_CLK_S0D3_PER 24 +#define R8A779G0_CLK_S0D4_PER 25 +#define R8A779G0_CLK_S0D6_PER 26 +#define R8A779G0_CLK_S0D12_PER 27 +#define R8A779G0_CLK_S0D24_PER 28 +#define R8A779G0_CLK_S0D1_HSC 29 +#define R8A779G0_CLK_S0D2_HSC 30 +#define R8A779G0_CLK_S0D4_HSC 31 +#define R8A779G0_CLK_S0D2_CC 32 +#define R8A779G0_CLK_SVD1_IR 33 +#define R8A779G0_CLK_SVD2_IR 34 +#define R8A779G0_CLK_SVD1_VIP 35 +#define R8A779G0_CLK_SVD2_VIP 36 +#define R8A779G0_CLK_CL 37 +#define R8A779G0_CLK_CL16M 38 +#define R8A779G0_CLK_CL16M_MM 39 +#define R8A779G0_CLK_CL16M_RT 40 +#define R8A779G0_CLK_CL16M_PER 41 +#define R8A779G0_CLK_CL16M_HSC 42 +#define R8A779G0_CLK_Z0 43 +#define R8A779G0_CLK_ZB3 44 +#define R8A779G0_CLK_ZB3D2 45 +#define R8A779G0_CLK_ZB3D4 46 +#define R8A779G0_CLK_ZG 47 +#define R8A779G0_CLK_SD0H 48 +#define R8A779G0_CLK_SD0 49 +#define R8A779G0_CLK_RPC 50 +#define R8A779G0_CLK_RPCD2 51 +#define R8A779G0_CLK_MSO 52 +#define R8A779G0_CLK_CANFD 53 +#define R8A779G0_CLK_CSI 54 +#define R8A779G0_CLK_FRAY 55 +#define R8A779G0_CLK_IPC 56 +#define R8A779G0_CLK_SASYNCRT 57 +#define R8A779G0_CLK_SASYNCPERD1 58 +#define R8A779G0_CLK_SASYNCPERD2 59 +#define R8A779G0_CLK_SASYNCPERD4 60 +#define R8A779G0_CLK_VIOBUS 61 +#define R8A779G0_CLK_VIOBUSD2 62 +#define R8A779G0_CLK_VCBUS 63 +#define R8A779G0_CLK_VCBUSD2 64 +#define R8A779G0_CLK_DSIEXT 65 +#define R8A779G0_CLK_DSIREF 66 +#define R8A779G0_CLK_ADGH 67 +#define R8A779G0_CLK_OSC 68 +#define R8A779G0_CLK_ZR0 69 +#define R8A779G0_CLK_ZR1 70 +#define R8A779G0_CLK_ZR2 71 +#define R8A779G0_CLK_IMPA 72 +#define R8A779G0_CLK_IMPAD4 73 +#define R8A779G0_CLK_CPEX 74 +#define R8A779G0_CLK_CBFUSA 75 +#define R8A779G0_CLK_R 76 + +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ From b243a358b31338d4b8068c6c17c32d255c89ee4a Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 11 Apr 2022 21:49:32 +0900 Subject: [PATCH 29/66] clk: renesas: r8a779f0: Add UFS clock Add the module clock used by the UFS host controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220411124932.3765571-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 08e8d95ce5e7e..5ed5dab16a2d9 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -132,6 +132,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), + DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), }; static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { From 13b4d179c6641f66f3385c5ed6f2715f5b99f003 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 20 Apr 2022 17:42:46 +0900 Subject: [PATCH 30/66] dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0 Add binding documentation for the R-Car V4H (R8A779G0) Clock Pulse Generator. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220420084255.375700-7-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml index e0b86214f0f54..e57bc40d307a2 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -49,6 +49,7 @@ properties: - renesas,r8a77995-cpg-mssr # R-Car D3 - renesas,r8a779a0-cpg-mssr # R-Car V3U - renesas,r8a779f0-cpg-mssr # R-Car S4-8 + - renesas,r8a779g0-cpg-mssr # R-Car V4H reg: maxItems: 1 From 14364fca21208d0954d594e1eccb4ad239881081 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Sun, 24 Apr 2022 19:22:27 +0100 Subject: [PATCH 31/66] clk: mux: remove redundant initialization of variable width Variable width is being ininitialized with a value that is never read. The ininitializtion is redundant and can be removed. Move the variable to the scope it is required. Cleans up cppcheck warning: Variable 'width' is assigned a value that is never used. Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20220424182227.1364966-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-mux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 214045f6e9895..fa817c317c2a9 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -157,11 +157,11 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, struct clk_mux *mux; struct clk_hw *hw; struct clk_init_data init = {}; - u8 width = 0; int ret = -EINVAL; if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { - width = fls(mask) - ffs(mask) + 1; + u8 width = fls(mask) - ffs(mask) + 1; + if (width + shift > 16) { pr_err("mux value exceeds LOWORD field\n"); return ERR_PTR(-EINVAL); From c6b61d48b369f92edc71a0c5dd0a9b98ea0b5397 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Tue, 26 Apr 2022 21:15:39 +0800 Subject: [PATCH 32/66] clk: en7523: fix wrong pointer check in en7523_clk_probe() Check the real return value of devm_platform_ioremap_resource() in en7523_clk_probe(). Fixes: 1e6273179190 ("clk: en7523: Add clock driver for Airoha EN7523 SoC") Reported-by: Hulk Robot Signed-off-by: Yang Yingliang Link: https://lore.kernel.org/r/20220426131539.388382-1-yangyingliang@huawei.com Acked-by: Felix Fietkau Signed-off-by: Stephen Boyd --- drivers/clk/clk-en7523.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 076a70c2e1738..29f0126cbd05b 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -314,7 +314,7 @@ static int en7523_clk_probe(struct platform_device *pdev) return PTR_ERR(base); np_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(base)) + if (IS_ERR(np_base)) return PTR_ERR(np_base); clk_data = devm_kzalloc(&pdev->dev, From 2a6da4a11f47f2530413fdca0b11dde33608a723 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 21 Apr 2022 11:00:11 +0200 Subject: [PATCH 33/66] clk: renesas: r9a06g032: Fix the RTC hclock description It needs to be un-gated, but also a reset must be released and an idle flag should also be disabled. The driver already supports all these operations, so update the description of the RTC hclock to fit these requirements. Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Miquel Raynal Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20220421090016.79517-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a06g032-clocks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index c99942f0e4d4c..1826aa73b713b 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -256,7 +256,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302), D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2), D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0), - D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0), + D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0), D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82), D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662), D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0), From a9391e019015e96d4ed40587ce0f648edf1c32d3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 10:52:39 +0100 Subject: [PATCH 34/66] clk: renesas: r9a07g043: Add I2C clocks/resets Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 2d6c96789f5c2..961216d55e0bb 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -152,6 +152,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x57c, 1), DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 0x57c, 1), + DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, + 0x580, 0), + DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, + 0x580, 1), + DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, + 0x580, 2), + DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, + 0x580, 3), DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 0x584, 0), DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, @@ -180,6 +188,10 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), + DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), + DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), + DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), + DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), From be5b5fcbc779f04a6ad38e9d4772712fe05b6f15 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 10:52:40 +0100 Subject: [PATCH 35/66] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 961216d55e0bb..d54bccf7b61b5 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -144,6 +144,22 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x554, 6), DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 0x554, 7), + DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, + 0x570, 0), + DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, + 0x570, 1), + DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, + 0x570, 2), + DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, + 0x570, 3), + DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, + 0x570, 4), + DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, + 0x570, 5), + DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, + 0x570, 6), + DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, + 0x570, 7), DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 0x57c, 0), DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, @@ -186,6 +202,10 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), + DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), + DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), + DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), From 666b5a010ef1e8d08227f5aa6e5b431ce0feca07 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 10:52:41 +0100 Subject: [PATCH 36/66] clk: renesas: r9a07g043: Add USB clocks/resets Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index d54bccf7b61b5..ea826f000d8da 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -160,6 +160,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x570, 6), DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 0x570, 7), + DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, + 0x578, 0), + DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, + 0x578, 1), + DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, + 0x578, 2), + DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, + 0x578, 3), DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 0x57c, 0), DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, @@ -206,6 +214,10 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), + DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), + DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), + DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), + DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), From 1cbda37757ab5581a18214b62e83a914acfcf3e8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 10:52:42 +0100 Subject: [PATCH 37/66] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index ea826f000d8da..59d5405474a59 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -100,6 +100,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { CLK_DIVIDER_HIWORD_MASK), DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), @@ -198,6 +199,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x588, 0), DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 0x588, 1), + DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, + 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 0x598, 0), }; @@ -231,6 +234,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), + DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), + DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), From 6c05648b57aba4c677eaf9c6c4c10bf4e713c1c0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 10:52:43 +0100 Subject: [PATCH 38/66] clk: renesas: r9a07g043: Add OSTM clock and reset entries Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 59d5405474a59..d0721bef5c146 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), + DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, + 0x534, 0), + DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, + 0x534, 1), + DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, + 0x534, 2), DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, @@ -211,6 +217,9 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), + DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), + DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), From 5d33481f54758eb050473af0692a043c084ad581 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 10:52:44 +0100 Subject: [PATCH 39/66] clk: renesas: r9a07g043: Add WDT clock and reset entries Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index d0721bef5c146..3f3c5d1b7fec1 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -135,6 +135,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 0x534, 2), + DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, + 0x548, 0), + DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, + 0x548, 1), + DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, + 0x548, 4), + DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, + 0x548, 5), DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, @@ -220,6 +228,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), + DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), From 7f906eaa95f38fae24957e0bf61878d5cb3f8847 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 25 Apr 2022 15:41:58 +0900 Subject: [PATCH 40/66] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 12 ++++++------ drivers/clk/renesas/r8a779f0-cpg-mssr.c | 20 ++++++++++---------- drivers/clk/renesas/rcar-gen4-cpg.c | 5 +++++ drivers/clk/renesas/rcar-gen4-cpg.h | 3 +++ 4 files changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index fb84f7b51f61c..d74d46833012f 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -244,7 +244,7 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { /* * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC * 14 13 (MHz) 21 31 - * -------------------------------------------------------- + * ---------------------------------------------------------------- * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 * 1 0 Prohibited setting @@ -253,11 +253,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { - /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ - { 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, }, - { 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, }, + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, }, + { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, }, }; diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 5ed5dab16a2d9..c17ebe6b59921 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -143,23 +143,23 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { * CPG Clock Data */ /* - * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC * 14 13 (MHz) - * ---------------------------------------------------------------- - * 0 0 16 / 1 x200 x150 x200 x200 x134 /15 - * 0 1 20 / 1 x160 x120 x160 x160 x106 /19 + * ------------------------------------------------------------------------ + * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15 + * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19 * 1 0 Prohibited setting - * 1 1 40 / 2 x160 x120 x160 x160 x106 /38 + * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { - /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ - { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, }, - { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, - { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, }, + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, }, + { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, }, }; static int __init r8a779f0_cpg_mssr_init(struct device *dev) diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index 54ebf4b3c1284..c7ed43d6aa67d 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -215,6 +215,11 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, div = cpg_pll_config->pll3_div; break; + case CLK_TYPE_GEN4_PLL4: + mult = cpg_pll_config->pll4_mult; + div = cpg_pll_config->pll4_div; + break; + case CLK_TYPE_GEN4_PLL5: mult = cpg_pll_config->pll5_mult; div = cpg_pll_config->pll5_div; diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h index afc8c024d538a..0b15dcfdca7b5 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.h +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -16,6 +16,7 @@ enum rcar_gen4_clk_types { CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */ CLK_TYPE_GEN4_PLL3, CLK_TYPE_GEN4_PLL5, + CLK_TYPE_GEN4_PLL4, CLK_TYPE_GEN4_PLL6, CLK_TYPE_GEN4_SDSRC, CLK_TYPE_GEN4_SDH, @@ -56,6 +57,8 @@ struct rcar_gen4_cpg_pll_config { u8 pll2_div; u8 pll3_mult; u8 pll3_div; + u8 pll4_mult; + u8 pll4_div; u8 pll5_mult; u8 pll5_div; u8 pll6_mult; From 0ab55cf1834177a2162757fee2ac3cb6730beb20 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 28 Apr 2022 22:50:56 +0900 Subject: [PATCH 41/66] clk: renesas: cpg-mssr: Add support for R-Car V4H Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a779g0-cpg-mssr.c | 218 ++++++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 5 files changed, 231 insertions(+) create mode 100644 drivers/clk/renesas/r8a779g0-cpg-mssr.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index a95ed8f310da6..7e9b9a5bb5b7b 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -32,6 +32,7 @@ config CLK_RENESAS select CLK_R8A77995 if ARCH_R8A77995 select CLK_R8A779A0 if ARCH_R8A779A0 select CLK_R8A779F0 if ARCH_R8A779F0 + select CLK_R8A779G0 if ARCH_R8A779G0 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 @@ -158,6 +159,10 @@ config CLK_R8A779F0 bool "R-Car S4-8 clock support" if COMPILE_TEST select CLK_RCAR_GEN4_CPG +config CLK_R8A779G0 + bool "R-Car V4H clock support" if COMPILE_TEST + select CLK_RCAR_GEN4_CPG + config CLK_R9A06G032 bool "RZ/N1D clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index ca3a9bbcf27ac..b83062af090c8 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c new file mode 100644 index 0000000000000..3fc4233b1ead8 --- /dev/null +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + * Based on r8a779f0-cpg-mssr.c + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen4-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A779G0_CLK_R, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL5, + CLK_PLL6, + CLK_PLL1_DIV2, + CLK_PLL2_DIV2, + CLK_PLL3_DIV2, + CLK_PLL4_DIV2, + CLK_PLL5_DIV2, + CLK_PLL5_DIV4, + CLK_PLL6_DIV2, + CLK_S0, + CLK_S0_VIO, + CLK_S0_VC, + CLK_S0_HSC, + CLK_SV_VIP, + CLK_SV_IR, + CLK_SDSRC, + CLK_RPCSRC, + CLK_VIO, + CLK_VC, + CLK_OCO, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), + DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1), + DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1), + DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), + DEF_RATE(".oco", CLK_OCO, 32768), + + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), + DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1), + DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1), + + /* Core Clock Outputs */ + DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1), + DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1), + DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1), + DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1), + DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1), + DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1), + DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1), + DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1), + DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1), + DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1), + DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1), + DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1), + DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1), + DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1), + DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1), + DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1), + DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1), + DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1), + DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1), + DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1), + DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1), + DEF_FIXED("s0d4_per", R8A779G0_CLK_S0D4_PER, CLK_S0, 4, 1), + DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1), + DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1), + DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1), + DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1), + DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1), + DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1), + DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1), + DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1), + DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1), + DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1), + DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1), + DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1), + DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1), + DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1), + DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1), + DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), + DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), + DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), + + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + + DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC), + + DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8), + DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), +}; + +static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { + DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER), + DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER), + DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER), + DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER), +}; + +/* + * CPG Clock Data + */ +/* + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC + * 14 13 (MHz) + * ------------------------------------------------------------------------ + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /15 + * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19 + * 1 0 Prohibited setting + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /38 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 15, }, + { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 38, }, +}; + +static int __init r8a779g0_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen4_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a779g0_core_clks, + .num_core_clks = ARRAY_SIZE(r8a779g0_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a779g0_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks), + .num_hw_mod_clks = 30 * 32, + + /* Callbacks */ + .init = r8a779g0_cpg_mssr_init, + .cpg_clk_register = rcar_gen4_cpg_clk_register, + + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 5d2c3edbaa142..1a0cdf001b2f2 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -853,6 +853,12 @@ static const struct of_device_id cpg_mssr_match[] = { .compatible = "renesas,r8a779f0-cpg-mssr", .data = &r8a779f0_cpg_mssr_info, }, +#endif +#ifdef CONFIG_CLK_R8A779G0 + { + .compatible = "renesas,r8a779g0-cpg-mssr", + .data = &r8a779g0_cpg_mssr_info, + }, #endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 16810dd4e6acf..1c3c057d17f53 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -179,6 +179,7 @@ extern const struct cpg_mssr_info r8a77990_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info; extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info; +extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info; void __init cpg_mssr_early_init(struct device_node *np, const struct cpg_mssr_info *info); From 96055bf71ab1629cdedff15bcbc04609cfa1f198 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:47 +0100 Subject: [PATCH 42/66] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's Manual (Rev. 1.10, Sep. 2021). Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a09g011-cpg.h | 352 ++++++++++++++++++++++ 1 file changed, 352 insertions(+) create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h new file mode 100644 index 0000000000000..41dd585d7115b --- /dev/null +++ b/include/dt-bindings/clock/r9a09g011-cpg.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ + +#include + +/* Module Clocks */ +#define R9A09G011_SYS_CLK 0 +#define R9A09G011_PFC_PCLK 1 +#define R9A09G011_PMC_CORE_CLOCK 2 +#define R9A09G011_GIC_CLK 3 +#define R9A09G011_RAMA_ACLK 4 +#define R9A09G011_ROMA_ACLK 5 +#define R9A09G011_SEC_ACLK 6 +#define R9A09G011_SEC_PCLK 7 +#define R9A09G011_SEC_TCLK 8 +#define R9A09G011_DMAA_ACLK 9 +#define R9A09G011_TSU0_PCLK 10 +#define R9A09G011_TSU1_PCLK 11 + +#define R9A09G011_CST_TRACECLK 12 +#define R9A09G011_CST_SB_CLK 13 +#define R9A09G011_CST_AHB_CLK 14 +#define R9A09G011_CST_ATB_SB_CLK 15 +#define R9A09G011_CST_TS_SB_CLK 16 + +#define R9A09G011_SDI0_ACLK 17 +#define R9A09G011_SDI0_IMCLK 18 +#define R9A09G011_SDI0_IMCLK2 19 +#define R9A09G011_SDI0_CLK_HS 20 +#define R9A09G011_SDI1_ACLK 21 +#define R9A09G011_SDI1_IMCLK 22 +#define R9A09G011_SDI1_IMCLK2 23 +#define R9A09G011_SDI1_CLK_HS 24 +#define R9A09G011_EMM_ACLK 25 +#define R9A09G011_EMM_IMCLK 26 +#define R9A09G011_EMM_IMCLK2 27 +#define R9A09G011_EMM_CLK_HS 28 +#define R9A09G011_NFI_ACLK 29 +#define R9A09G011_NFI_NF_CLK 30 + +#define R9A09G011_PCI_ACLK 31 +#define R9A09G011_PCI_CLK_PMU 32 +#define R9A09G011_PCI_APB_CLK 33 +#define R9A09G011_USB_ACLK_H 34 +#define R9A09G011_USB_ACLK_P 35 +#define R9A09G011_USB_PCLK 36 +#define R9A09G011_ETH0_CLK_AXI 37 +#define R9A09G011_ETH0_CLK_CHI 38 +#define R9A09G011_ETH0_GPTP_EXT 39 + +#define R9A09G011_SDT_CLK 40 +#define R9A09G011_SDT_CLKAPB 41 +#define R9A09G011_SDT_CLK48 42 +#define R9A09G011_GRP_CLK 43 +#define R9A09G011_CIF_P0_CLK 44 +#define R9A09G011_CIF_P1_CLK 45 +#define R9A09G011_CIF_APB_CLK 46 +#define R9A09G011_DCI_CLKAXI 47 +#define R9A09G011_DCI_CLKAPB 48 +#define R9A09G011_DCI_CLKDCI2 49 + +#define R9A09G011_HMI_PCLK 50 +#define R9A09G011_LCI_PCLK 51 +#define R9A09G011_LCI_ACLK 52 +#define R9A09G011_LCI_VCLK 53 +#define R9A09G011_LCI_LPCLK 54 + +#define R9A09G011_AUI_CLK 55 +#define R9A09G011_AUI_CLKAXI 56 +#define R9A09G011_AUI_CLKAPB 57 +#define R9A09G011_AUMCLK 58 +#define R9A09G011_GMCLK0 59 +#define R9A09G011_GMCLK1 60 +#define R9A09G011_MTR_CLK0 61 +#define R9A09G011_MTR_CLK1 62 +#define R9A09G011_MTR_CLKAPB 63 +#define R9A09G011_GFT_CLK 64 +#define R9A09G011_GFT_CLKAPB 65 +#define R9A09G011_GFT_MCLK 66 + +#define R9A09G011_ATGA_CLK 67 +#define R9A09G011_ATGA_CLKAPB 68 +#define R9A09G011_ATGB_CLK 69 +#define R9A09G011_ATGB_CLKAPB 70 +#define R9A09G011_SYC_CNT_CLK 71 + +#define R9A09G011_CPERI_GRPA_PCLK 72 +#define R9A09G011_TIM0_CLK 73 +#define R9A09G011_TIM1_CLK 74 +#define R9A09G011_TIM2_CLK 75 +#define R9A09G011_TIM3_CLK 76 +#define R9A09G011_TIM4_CLK 77 +#define R9A09G011_TIM5_CLK 78 +#define R9A09G011_TIM6_CLK 79 +#define R9A09G011_TIM7_CLK 80 +#define R9A09G011_IIC_PCLK0 81 + +#define R9A09G011_CPERI_GRPB_PCLK 82 +#define R9A09G011_TIM8_CLK 83 +#define R9A09G011_TIM9_CLK 84 +#define R9A09G011_TIM10_CLK 85 +#define R9A09G011_TIM11_CLK 86 +#define R9A09G011_TIM12_CLK 87 +#define R9A09G011_TIM13_CLK 88 +#define R9A09G011_TIM14_CLK 89 +#define R9A09G011_TIM15_CLK 90 +#define R9A09G011_IIC_PCLK1 91 + +#define R9A09G011_CPERI_GRPC_PCLK 92 +#define R9A09G011_TIM16_CLK 93 +#define R9A09G011_TIM17_CLK 94 +#define R9A09G011_TIM18_CLK 95 +#define R9A09G011_TIM19_CLK 96 +#define R9A09G011_TIM20_CLK 97 +#define R9A09G011_TIM21_CLK 98 +#define R9A09G011_TIM22_CLK 99 +#define R9A09G011_TIM23_CLK 100 +#define R9A09G011_WDT0_PCLK 101 +#define R9A09G011_WDT0_CLK 102 +#define R9A09G011_WDT1_PCLK 103 +#define R9A09G011_WDT1_CLK 104 + +#define R9A09G011_CPERI_GRPD_PCLK 105 +#define R9A09G011_TIM24_CLK 106 +#define R9A09G011_TIM25_CLK 107 +#define R9A09G011_TIM26_CLK 108 +#define R9A09G011_TIM27_CLK 109 +#define R9A09G011_TIM28_CLK 110 +#define R9A09G011_TIM29_CLK 111 +#define R9A09G011_TIM30_CLK 112 +#define R9A09G011_TIM31_CLK 113 + +#define R9A09G011_CPERI_GRPE_PCLK 114 +#define R9A09G011_PWM0_CLK 115 +#define R9A09G011_PWM1_CLK 116 +#define R9A09G011_PWM2_CLK 117 +#define R9A09G011_PWM3_CLK 118 +#define R9A09G011_PWM4_CLK 119 +#define R9A09G011_PWM5_CLK 120 +#define R9A09G011_PWM6_CLK 121 +#define R9A09G011_PWM7_CLK 122 + +#define R9A09G011_CPERI_GRPF_PCLK 123 +#define R9A09G011_PWM8_CLK 124 +#define R9A09G011_PWM9_CLK 125 +#define R9A09G011_PWM10_CLK 126 +#define R9A09G011_PWM11_CLK 127 +#define R9A09G011_PWM12_CLK 128 +#define R9A09G011_PWM13_CLK 129 +#define R9A09G011_PWM14_CLK 130 +#define R9A09G011_PWM15_CLK 131 + +#define R9A09G011_CPERI_GRPG_PCLK 132 +#define R9A09G011_CPERI_GRPH_PCLK 133 +#define R9A09G011_URT_PCLK 134 +#define R9A09G011_URT0_CLK 135 +#define R9A09G011_URT1_CLK 136 +#define R9A09G011_CSI0_CLK 137 +#define R9A09G011_CSI1_CLK 138 +#define R9A09G011_CSI2_CLK 139 +#define R9A09G011_CSI3_CLK 140 +#define R9A09G011_CSI4_CLK 141 +#define R9A09G011_CSI5_CLK 142 + +#define R9A09G011_ICB_ACLK1 143 +#define R9A09G011_ICB_GIC_CLK 144 +#define R9A09G011_ICB_MPCLK1 145 +#define R9A09G011_ICB_SPCLK1 146 +#define R9A09G011_ICB_CLK48 147 +#define R9A09G011_ICB_CLK48_2 148 +#define R9A09G011_ICB_CLK48_3 149 +#define R9A09G011_ICB_CLK48_4L 150 +#define R9A09G011_ICB_CLK48_4R 151 +#define R9A09G011_ICB_CLK48_5 152 +#define R9A09G011_ICB_CST_ATB_SB_CLK 153 +#define R9A09G011_ICB_CST_CS_CLK 154 +#define R9A09G011_ICB_CLK100_1 155 +#define R9A09G011_ICB_ETH0_CLK_AXI 156 +#define R9A09G011_ICB_DCI_CLKAXI 157 +#define R9A09G011_ICB_SYC_CNT_CLK 158 + +#define R9A09G011_ICB_DRPA_ACLK 159 +#define R9A09G011_ICB_RFX_ACLK 160 +#define R9A09G011_ICB_RFX_PCLK5 161 +#define R9A09G011_ICB_MMC_ACLK 162 + +#define R9A09G011_ICB_MPCLK3 163 +#define R9A09G011_ICB_CIMA_CLK 164 +#define R9A09G011_ICB_CIMB_CLK 165 +#define R9A09G011_ICB_BIMA_CLK 166 +#define R9A09G011_ICB_FCD_CLKAXI 167 +#define R9A09G011_ICB_VD_ACLK4 168 +#define R9A09G011_ICB_MPCLK4 169 +#define R9A09G011_ICB_VCD_PCLK4 170 + +#define R9A09G011_CA53_CLK 171 +#define R9A09G011_CA53_ACLK 172 +#define R9A09G011_CA53_APCLK_DBG 173 +#define R9A09G011_CST_APB_CA53_CLK 174 +#define R9A09G011_CA53_ATCLK 175 +#define R9A09G011_CST_CS_CLK 176 +#define R9A09G011_CA53_TSCLK 177 +#define R9A09G011_CST_TS_CLK 178 +#define R9A09G011_CA53_APCLK_REG 179 + +#define R9A09G011_DRPA_ACLK 180 +#define R9A09G011_DRPA_DCLK 181 +#define R9A09G011_DRPA_INITCLK 182 + +#define R9A09G011_RAMB0_ACLK 183 +#define R9A09G011_RAMB1_ACLK 184 +#define R9A09G011_RAMB2_ACLK 185 +#define R9A09G011_RAMB3_ACLK 186 + +#define R9A09G011_CIMA_CLKAPB 187 +#define R9A09G011_CIMA_CLK 188 +#define R9A09G011_CIMB_CLK 189 +#define R9A09G011_FAFA_CLK 190 +#define R9A09G011_STG_CLKAXI 191 +#define R9A09G011_STG_CLK0 192 + +#define R9A09G011_BIMA_CLKAPB 193 +#define R9A09G011_BIMA_CLK 194 +#define R9A09G011_FAFB_CLK 195 +#define R9A09G011_FCD_CLK 196 +#define R9A09G011_FCD_CLKAXI 197 + +#define R9A09G011_RIM_CLK 198 +#define R9A09G011_VCD_ACLK 199 +#define R9A09G011_VCD_PCLK 200 +#define R9A09G011_JPG0_CLK 201 +#define R9A09G011_JPG0_ACLK 202 + +#define R9A09G011_MMC_CORE_DDRC_CLK 203 +#define R9A09G011_MMC_ACLK 204 +#define R9A09G011_MMC_PCLK 205 +#define R9A09G011_DDI_APBCLK 206 + +/* Resets */ +#define R9A09G011_SYS_RST_N 0 +#define R9A09G011_PFC_PRESETN 1 +#define R9A09G011_RAMA_ARESETN 2 +#define R9A09G011_ROM_ARESETN 3 +#define R9A09G011_DMAA_ARESETN 4 +#define R9A09G011_SEC_ARESETN 5 +#define R9A09G011_SEC_PRESETN 6 +#define R9A09G011_SEC_RSTB 7 +#define R9A09G011_TSU0_RESETN 8 +#define R9A09G011_TSU1_RESETN 9 +#define R9A09G011_PMC_RESET_N 10 + +#define R9A09G011_CST_NTRST 11 +#define R9A09G011_CST_NPOTRST 12 +#define R9A09G011_CST_NTRST2 13 +#define R9A09G011_CST_CS_RESETN 14 +#define R9A09G011_CST_TS_RESETN 15 +#define R9A09G011_CST_TRESETN 16 +#define R9A09G011_CST_SB_RESETN 17 +#define R9A09G011_CST_AHB_RESETN 18 +#define R9A09G011_CST_TS_SB_RESETN 19 +#define R9A09G011_CST_APB_CA53_RESETN 20 +#define R9A09G011_CST_ATB_SB_RESETN 21 + +#define R9A09G011_SDI0_IXRST 22 +#define R9A09G011_SDI1_IXRST 23 +#define R9A09G011_EMM_IXRST 24 +#define R9A09G011_NFI_MARESETN 25 +#define R9A09G011_NFI_REG_RST_N 26 +#define R9A09G011_USB_PRESET_N 27 +#define R9A09G011_USB_DRD_RESET 28 +#define R9A09G011_USB_ARESETN_P 29 +#define R9A09G011_USB_ARESETN_H 30 +#define R9A09G011_ETH0_RST_HW_N 31 +#define R9A09G011_PCI_ARESETN 32 + +#define R9A09G011_SDT_RSTSYSAX 33 +#define R9A09G011_GRP_RESETN 34 +#define R9A09G011_CIF_RST_N 35 +#define R9A09G011_DCU_RSTSYSAX 36 +#define R9A09G011_HMI_RST_N 37 +#define R9A09G011_HMI_PRESETN 38 +#define R9A09G011_LCI_PRESETN 39 +#define R9A09G011_LCI_ARESETN 40 + +#define R9A09G011_AUI_RSTSYSAX 41 +#define R9A09G011_MTR_RSTSYSAX 42 +#define R9A09G011_GFT_RSTSYSAX 43 +#define R9A09G011_ATGA_RSTSYSAX 44 +#define R9A09G011_ATGB_RSTSYSAX 45 +#define R9A09G011_SYC_RST_N 46 + +#define R9A09G011_TIM_GPA_PRESETN 47 +#define R9A09G011_TIM_GPB_PRESETN 48 +#define R9A09G011_TIM_GPC_PRESETN 49 +#define R9A09G011_TIM_GPD_PRESETN 50 +#define R9A09G011_PWM_GPE_PRESETN 51 +#define R9A09G011_PWM_GPF_PRESETN 52 +#define R9A09G011_CSI_GPG_PRESETN 53 +#define R9A09G011_CSI_GPH_PRESETN 54 +#define R9A09G011_IIC_GPA_PRESETN 55 +#define R9A09G011_IIC_GPB_PRESETN 56 +#define R9A09G011_URT_PRESETN 57 +#define R9A09G011_WDT0_PRESETN 58 +#define R9A09G011_WDT1_PRESETN 59 + +#define R9A09G011_ICB_PD_AWO_RST_N 60 +#define R9A09G011_ICB_PD_MMC_RST_N 61 +#define R9A09G011_ICB_PD_VD0_RST_N 62 +#define R9A09G011_ICB_PD_VD1_RST_N 63 +#define R9A09G011_ICB_PD_RFX_RST_N 64 + +#define R9A09G011_CA53_NCPUPORESET0 65 +#define R9A09G011_CA53_NCPUPORESET1 66 +#define R9A09G011_CA53_NCORERESET0 67 +#define R9A09G011_CA53_NCORERESET1 68 +#define R9A09G011_CA53_NPRESETDBG 69 +#define R9A09G011_CA53_L2RESET 70 +#define R9A09G011_CA53_NMISCRESET_HM 71 +#define R9A09G011_CA53_NMISCRESET_SM 72 +#define R9A09G011_CA53_NARESET 73 + +#define R9A09G011_DRPA_ARESETN 74 + +#define R9A09G011_RAMB0_ARESETN 75 +#define R9A09G011_RAMB1_ARESETN 76 +#define R9A09G011_RAMB2_ARESETN 77 +#define R9A09G011_RAMB3_ARESETN 78 + +#define R9A09G011_CIMA_RSTSYSAX 79 +#define R9A09G011_CIMB_RSTSYSAX 80 +#define R9A09G011_FAFA_RSTSYSAX 81 +#define R9A09G011_STG_RSTSYSAX 82 + +#define R9A09G011_BIMA_RSTSYSAX 83 +#define R9A09G011_FAFB_RSTSYSAX 84 +#define R9A09G011_FCD_RSTSYSAX 85 +#define R9A09G011_RIM_RSTSYSAX 86 +#define R9A09G011_VCD_RESETN 87 +#define R9A09G011_JPG_XRESET 88 + +#define R9A09G011_MMC_CORE_DDRC_RSTN 89 +#define R9A09G011_MMC_ARESETN_N 90 +#define R9A09G011_MMC_PRESETN 91 +#define R9A09G011_DDI_PWROK 92 +#define R9A09G011_DDI_RESET 93 +#define R9A09G011_DDI_RESETN_APB 94 + +#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */ From 1561380ee72f55e3a86856ee046532c18d3e9855 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:48 +0100 Subject: [PATCH 43/66] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules. The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced from DSI divider which is connected to PLL5_4 MUX. This patch adds support for generating FOUTPOSTDIV clk. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 212 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 23 ++++ 2 files changed, 235 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 1ce35f65682b4..d1ede40b52104 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -27,6 +27,7 @@ #include #include #include +#include #include @@ -64,6 +65,21 @@ struct sd_hw_data { #define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw) +struct rzg2l_pll5_param { + u32 pl5_fracin; + u8 pl5_refdiv; + u8 pl5_intin; + u8 pl5_postdiv1; + u8 pl5_postdiv2; + u8 pl5_spread; +}; + +struct rzg2l_pll5_mux_dsi_div_param { + u8 clksrc; + u8 dsi_div_a; + u8 dsi_div_b; +}; + /** * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data * @@ -77,6 +93,7 @@ struct sd_hw_data { * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data + * @pll5_mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { struct reset_controller_dev rcdev; @@ -91,6 +108,8 @@ struct rzg2l_cpg_priv { unsigned int last_dt_core_clk; const struct rzg2l_cpg_info *info; + + struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; }; static void rzg2l_cpg_del_clk_provider(void *data) @@ -264,6 +283,196 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, return clk_hw->clk; } +static unsigned long +rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, + unsigned long rate) +{ + unsigned long foutpostdiv_rate; + + params->pl5_intin = rate / MEGA; + params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA); + params->pl5_refdiv = 2; + params->pl5_postdiv1 = 1; + params->pl5_postdiv2 = 1; + params->pl5_spread = 0x16; + + foutpostdiv_rate = + EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv * + ((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) / + (params->pl5_postdiv1 * params->pl5_postdiv2); + + return foutpostdiv_rate; +} + +struct sipll5 { + struct clk_hw hw; + u32 conf; + unsigned long foutpostdiv_rate; + struct rzg2l_cpg_priv *priv; +}; + +#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw) + +static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw, + unsigned long rate) +{ + struct sipll5 *sipll5 = to_sipll5(hw); + struct rzg2l_cpg_priv *priv = sipll5->priv; + unsigned long vclk; + + vclk = rate / ((1 << priv->mux_dsi_div_params.dsi_div_a) * + (priv->mux_dsi_div_params.dsi_div_b + 1)); + + if (priv->mux_dsi_div_params.clksrc) + vclk /= 2; + + return vclk; +} + +static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sipll5 *sipll5 = to_sipll5(hw); + unsigned long pll5_rate = sipll5->foutpostdiv_rate; + + if (!pll5_rate) + pll5_rate = parent_rate; + + return pll5_rate; +} + +static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + +static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct sipll5 *sipll5 = to_sipll5(hw); + struct rzg2l_cpg_priv *priv = sipll5->priv; + struct rzg2l_pll5_param params; + unsigned long vclk_rate; + int ret; + u32 val; + + /* + * OSC --> PLL5 --> FOUTPOSTDIV-->| + * | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK + * |--FOUT1PH0-->| + * + * Based on the dot clock, the DSI divider clock calculates the parent + * rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates + * that info to sipll5 which sets parameters for generating FOUTPOSTDIV. + * + * OSC --> PLL5 --> FOUTPOSTDIV + */ + + if (!rate) + return -EINVAL; + + vclk_rate = rzg2l_cpg_get_vclk_rate(hw, rate); + sipll5->foutpostdiv_rate = + rzg2l_cpg_get_foutpostdiv_rate(¶ms, vclk_rate); + + /* Put PLL5 into standby mode */ + writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY); + ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val, + !(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000); + if (ret) { + dev_err(priv->dev, "failed to release pll5 lock"); + return ret; + } + + /* Output clock setting 1 */ + writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN | + CPG_SIPLL5_CLK1_REFDIV_WEN | (params.pl5_postdiv1 << 0) | + (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8), + priv->base + CPG_SIPLL5_CLK1); + + /* Output clock setting, SSCG modulation value setting 3 */ + writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3); + + /* Output clock setting 4 */ + writel(CPG_SIPLL5_CLK4_RESV_LSB | (params.pl5_intin << 16), + priv->base + CPG_SIPLL5_CLK4); + + /* Output clock setting 5 */ + writel(params.pl5_spread, priv->base + CPG_SIPLL5_CLK5); + + /* PLL normal mode setting */ + writel(CPG_SIPLL5_STBY_DOWNSPREAD_WEN | CPG_SIPLL5_STBY_SSCG_EN_WEN | + CPG_SIPLL5_STBY_RESETB_WEN | CPG_SIPLL5_STBY_RESETB, + priv->base + CPG_SIPLL5_STBY); + + /* PLL normal mode transition, output clock stability check */ + ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val, + (val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000); + if (ret) { + dev_err(priv->dev, "failed to lock pll5"); + return ret; + } + + return 0; +} + +static const struct clk_ops rzg2l_cpg_sipll5_ops = { + .recalc_rate = rzg2l_cpg_sipll5_recalc_rate, + .round_rate = rzg2l_cpg_sipll5_round_rate, + .set_rate = rzg2l_cpg_sipll5_set_rate, +}; + +static struct clk * __init +rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core, + struct clk **clks, + struct rzg2l_cpg_priv *priv) +{ + const struct clk *parent; + struct clk_init_data init; + const char *parent_name; + struct sipll5 *sipll5; + struct clk_hw *clk_hw; + int ret; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + sipll5 = devm_kzalloc(priv->dev, sizeof(*sipll5), GFP_KERNEL); + if (!sipll5) + return ERR_PTR(-ENOMEM); + + init.name = core->name; + parent_name = __clk_get_name(parent); + init.ops = &rzg2l_cpg_sipll5_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + sipll5->hw.init = &init; + sipll5->conf = core->conf; + sipll5->priv = priv; + + writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN | + CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY); + + clk_hw = &sipll5->hw; + clk_hw->init = &init; + + ret = devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */ + priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */ + priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */ + + return clk_hw->clk; +} + struct pll_clk { struct clk_hw hw; unsigned int conf; @@ -418,6 +627,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv); break; + case CLK_TYPE_SIPLL5: + clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv); + break; case CLK_TYPE_DIV: clk = rzg2l_cpg_div_clk_register(core, priv->clks, priv->base, priv); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 92c88f42ca7fa..c39c0ca8d1550 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -9,6 +9,12 @@ #ifndef __RENESAS_RZG2L_CPG_H__ #define __RENESAS_RZG2L_CPG_H__ +#define CPG_SIPLL5_STBY (0x140) +#define CPG_SIPLL5_CLK1 (0x144) +#define CPG_SIPLL5_CLK3 (0x14C) +#define CPG_SIPLL5_CLK4 (0x150) +#define CPG_SIPLL5_CLK5 (0x154) +#define CPG_SIPLL5_MON (0x15C) #define CPG_PL1_DDIV (0x200) #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) @@ -19,6 +25,16 @@ #define CPG_PL6_SSEL (0x414) #define CPG_PL6_ETH_SSEL (0x418) +#define CPG_SIPLL5_STBY_RESETB BIT(0) +#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) +#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) +#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) +#define CPG_SIPLL5_CLK1_POSTDIV1_WEN BIT(16) +#define CPG_SIPLL5_CLK1_POSTDIV2_WEN BIT(20) +#define CPG_SIPLL5_CLK1_REFDIV_WEN BIT(24) +#define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) +#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) + #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) @@ -49,6 +65,8 @@ #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) +#define EXTAL_FREQ_IN_MEGA_HZ (24) + /** * Definitions of CPG Core Clocks * @@ -86,6 +104,9 @@ enum clk_types { /* Clock with SD clock source selector */ CLK_TYPE_SD_MUX, + + /* Clock for SIPLL5 */ + CLK_TYPE_SIPLL5, }; #define DEF_TYPE(_name, _id, _type...) \ @@ -109,6 +130,8 @@ enum clk_types { #define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ .parent_names = _parent_names, .num_parents = _num_parents) +#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ + DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) /** * struct rzg2l_mod_clk - Module Clocks definitions From 6cc859cae9aa8c42e8347e2806232bdffeb1b33d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:49 +0100 Subject: [PATCH 44/66] clk: renesas: rzg2l: Add PLL5_4 clk mux support Add PLL5_4 clk mux support to select clock from clock sources FOUTPOSTDIV and FOUT1PH0. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 93 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 10 ++++ 2 files changed, 103 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index d1ede40b52104..ec2ccfd316f97 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -304,6 +304,96 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, return foutpostdiv_rate; } +struct pll5_mux_hw_data { + struct clk_hw hw; + u32 conf; + unsigned long rate; + struct rzg2l_cpg_priv *priv; +}; + +#define to_pll5_mux_hw_data(_hw) container_of(_hw, struct pll5_mux_hw_data, hw) + +static int rzg2l_cpg_pll5_4_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *parent; + struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw); + struct rzg2l_cpg_priv *priv = hwdata->priv; + + parent = clk_hw_get_parent_by_index(hw, priv->mux_dsi_div_params.clksrc); + req->best_parent_hw = parent; + req->best_parent_rate = req->rate; + + return 0; +} + +static int rzg2l_cpg_pll5_4_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw); + struct rzg2l_cpg_priv *priv = hwdata->priv; + + /* + * FOUTPOSTDIV--->| + * | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK + * |--FOUT1PH0-->| + * + * Based on the dot clock, the DSI divider clock calculates the parent + * rate and clk source for the MUX. It propagates that info to + * pll5_4_clk_mux which sets the clock source for DSI divider clock. + */ + + writel(CPG_OTHERFUNC1_REG_RES0_ON_WEN | index, + priv->base + CPG_OTHERFUNC1_REG); + + return 0; +} + +static u8 rzg2l_cpg_pll5_4_clk_mux_get_parent(struct clk_hw *hw) +{ + struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw); + struct rzg2l_cpg_priv *priv = hwdata->priv; + + return readl(priv->base + GET_REG_OFFSET(hwdata->conf)); +} + +static const struct clk_ops rzg2l_cpg_pll5_4_clk_mux_ops = { + .determine_rate = rzg2l_cpg_pll5_4_clk_mux_determine_rate, + .set_parent = rzg2l_cpg_pll5_4_clk_mux_set_parent, + .get_parent = rzg2l_cpg_pll5_4_clk_mux_get_parent, +}; + +static struct clk * __init +rzg2l_cpg_pll5_4_mux_clk_register(const struct cpg_core_clk *core, + struct rzg2l_cpg_priv *priv) +{ + struct pll5_mux_hw_data *clk_hw_data; + struct clk_init_data init; + struct clk_hw *clk_hw; + int ret; + + clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->priv = priv; + clk_hw_data->conf = core->conf; + + init.name = core->name; + init.ops = &rzg2l_cpg_pll5_4_clk_mux_ops; + init.flags = CLK_SET_RATE_PARENT; + init.num_parents = core->num_parents; + init.parent_names = core->parent_names; + + clk_hw = &clk_hw_data->hw; + clk_hw->init = &init; + + ret = devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + return clk_hw->clk; +} + struct sipll5 { struct clk_hw hw; u32 conf; @@ -640,6 +730,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, case CLK_TYPE_SD_MUX: clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv); break; + case CLK_TYPE_PLL5_4_MUX: + clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv); + break; default: goto fail; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index c39c0ca8d1550..2503251cb18f8 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -24,6 +24,7 @@ #define CPG_PL3_SSEL (0x408) #define CPG_PL6_SSEL (0x414) #define CPG_PL6_ETH_SSEL (0x418) +#define CPG_OTHERFUNC1_REG (0xBE8) #define CPG_SIPLL5_STBY_RESETB BIT(0) #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) @@ -35,6 +36,8 @@ #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) +#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) + #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) @@ -59,6 +62,7 @@ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) +#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) @@ -107,6 +111,9 @@ enum clk_types { /* Clock for SIPLL5 */ CLK_TYPE_SIPLL5, + + /* Clock for PLL5_4 clock source selector */ + CLK_TYPE_PLL5_4_MUX, }; #define DEF_TYPE(_name, _id, _type...) \ @@ -132,6 +139,9 @@ enum clk_types { .parent_names = _parent_names, .num_parents = _num_parents) #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) +#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names, _num_parents) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ + .parent_names = _parent_names, .num_parents = _num_parents) /** * struct rzg2l_mod_clk - Module Clocks definitions From 46bb3e15e8c7e6c045f619e91b380ff090669b83 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:50 +0100 Subject: [PATCH 45/66] clk: renesas: rzg2l: Add DSI divider clk support M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB) This patch add support for DSI divider clk by combining DSIDIVA and DSIDIVB. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 125 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 11 +++ 2 files changed, 136 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index ec2ccfd316f97..a1e1fee9f4832 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -57,6 +57,8 @@ #define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff) #define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff) +#define MAX_VCLK_FREQ (148500000) + struct sd_hw_data { struct clk_hw hw; u32 conf; @@ -304,6 +306,126 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, return foutpostdiv_rate; } +struct dsi_div_hw_data { + struct clk_hw hw; + u32 conf; + unsigned long rate; + struct rzg2l_cpg_priv *priv; +}; + +#define to_dsi_div_hw_data(_hw) container_of(_hw, struct dsi_div_hw_data, hw) + +static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw); + unsigned long rate = dsi_div->rate; + + if (!rate) + rate = parent_rate; + + return rate; +} + +static unsigned long rzg2l_cpg_get_vclk_parent_rate(struct clk_hw *hw, + unsigned long rate) +{ + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw); + struct rzg2l_cpg_priv *priv = dsi_div->priv; + struct rzg2l_pll5_param params; + unsigned long parent_rate; + + parent_rate = rzg2l_cpg_get_foutpostdiv_rate(¶ms, rate); + + if (priv->mux_dsi_div_params.clksrc) + parent_rate /= 2; + + return parent_rate; +} + +static int rzg2l_cpg_dsi_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + if (req->rate > MAX_VCLK_FREQ) + req->rate = MAX_VCLK_FREQ; + + req->best_parent_rate = rzg2l_cpg_get_vclk_parent_rate(hw, req->rate); + + return 0; +} + +static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw); + struct rzg2l_cpg_priv *priv = dsi_div->priv; + + /* + * MUX -->DIV_DSI_{A,B} -->M3 -->VCLK + * + * Based on the dot clock, the DSI divider clock sets the divider value, + * calculates the pll parameters for generating FOUTPOSTDIV and the clk + * source for the MUX and propagates that info to the parents. + */ + + if (!rate || rate > MAX_VCLK_FREQ) + return -EINVAL; + + dsi_div->rate = rate; + writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN | + (priv->mux_dsi_div_params.dsi_div_a << 0) | + (priv->mux_dsi_div_params.dsi_div_b << 8), + priv->base + CPG_PL5_SDIV); + + return 0; +} + +static const struct clk_ops rzg2l_cpg_dsi_div_ops = { + .recalc_rate = rzg2l_cpg_dsi_div_recalc_rate, + .determine_rate = rzg2l_cpg_dsi_div_determine_rate, + .set_rate = rzg2l_cpg_dsi_div_set_rate, +}; + +static struct clk * __init +rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core, + struct clk **clks, + struct rzg2l_cpg_priv *priv) +{ + struct dsi_div_hw_data *clk_hw_data; + const struct clk *parent; + const char *parent_name; + struct clk_init_data init; + struct clk_hw *clk_hw; + int ret; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->priv = priv; + + parent_name = __clk_get_name(parent); + init.name = core->name; + init.ops = &rzg2l_cpg_dsi_div_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = &parent_name; + init.num_parents = 1; + + clk_hw = &clk_hw_data->hw; + clk_hw->init = &init; + + ret = devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + return clk_hw->clk; +} + struct pll5_mux_hw_data { struct clk_hw hw; u32 conf; @@ -733,6 +855,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, case CLK_TYPE_PLL5_4_MUX: clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv); break; + case CLK_TYPE_DSI_DIV: + clk = rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv); + break; default: goto fail; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 2503251cb18f8..1be29cec0cb2d 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -24,6 +24,7 @@ #define CPG_PL3_SSEL (0x408) #define CPG_PL6_SSEL (0x414) #define CPG_PL6_ETH_SSEL (0x418) +#define CPG_PL5_SDIV (0x420) #define CPG_OTHERFUNC1_REG (0xBE8) #define CPG_SIPLL5_STBY_RESETB BIT(0) @@ -38,6 +39,9 @@ #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) +#define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) +#define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) + #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) @@ -53,6 +57,7 @@ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) +#define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) @@ -114,6 +119,10 @@ enum clk_types { /* Clock for PLL5_4 clock source selector */ CLK_TYPE_PLL5_4_MUX, + + /* Clock for DSI divider */ + CLK_TYPE_DSI_DIV, + }; #define DEF_TYPE(_name, _id, _type...) \ @@ -142,6 +151,8 @@ enum clk_types { #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names, _num_parents) \ DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ .parent_names = _parent_names, .num_parents = _num_parents) +#define DEF_DSI_DIV(_name, _id, _parent, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) /** * struct rzg2l_mod_clk - Module Clocks definitions From 60191843db7812dba4fdd2790a2d646721e13b21 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:51 +0100 Subject: [PATCH 46/66] clk: renesas: r9a07g044: Add M1 clock support Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index bdfabb992a207..0c9fa1f705af3 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -40,6 +40,8 @@ enum clk_ids { CLK_DIV_PLL3_C, CLK_PLL4, CLK_PLL5, + CLK_PLL5_FOUTPOSTDIV, + CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUT3, CLK_PLL5_250, CLK_PLL6, @@ -52,6 +54,7 @@ enum clk_ids { CLK_SD0_DIV4, CLK_SD1_DIV4, CLK_SEL_GPU2, + CLK_SEL_PLL5_4, /* Module Clocks */ MOD_CLK_BASE, @@ -77,12 +80,13 @@ static const struct clk_div_table dtable_1_32[] = { /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; +static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct { - struct cpg_core_clk common[44]; + struct cpg_core_clk common[48]; #ifdef CONFIG_CLK_R9A07G054 struct cpg_core_clk drp[0]; #endif @@ -127,6 +131,10 @@ static const struct { DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), + DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), + DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), + DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, + sel_pll5_4, ARRAY_SIZE(sel_pll5_4)), /* Core output clk */ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, @@ -154,6 +162,7 @@ static const struct { DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), }, #ifdef CONFIG_CLK_R9A07G054 .drp = { From 300d95c5bbb4cb59a149e436ed162a0ca09cdca1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:52 +0100 Subject: [PATCH 47/66] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 0c9fa1f705af3..d350d6dce4b19 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -32,6 +32,7 @@ enum clk_ids { CLK_PLL3, CLK_PLL3_400, CLK_PLL3_533, + CLK_M2_DIV2, CLK_PLL3_DIV2, CLK_PLL3_DIV2_2, CLK_PLL3_DIV2_4, @@ -86,7 +87,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct { - struct cpg_core_clk common[48]; + struct cpg_core_clk common[50]; #ifdef CONFIG_CLK_R9A07G054 struct cpg_core_clk drp[0]; #endif @@ -163,6 +164,8 @@ static const struct { DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), + DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), + DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), }, #ifdef CONFIG_CLK_R9A07G054 .drp = { From 359f10c1b02d3c65c7eba6146e5b7962f0abbd93 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:53 +0100 Subject: [PATCH 48/66] clk: renesas: r9a07g044: Add M3 Clock support Add support for M3 clock which is sourced from DSI divider connected to PLL5_4 mux. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index d350d6dce4b19..cee552bdf3cc7 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -56,6 +56,7 @@ enum clk_ids { CLK_SD1_DIV4, CLK_SEL_GPU2, CLK_SEL_PLL5_4, + CLK_DSI_DIV, /* Module Clocks */ MOD_CLK_BASE, @@ -87,7 +88,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct { - struct cpg_core_clk common[50]; + struct cpg_core_clk common[52]; #ifdef CONFIG_CLK_R9A07G054 struct cpg_core_clk drp[0]; #endif @@ -166,6 +167,8 @@ static const struct { DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), + DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT), + DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1), }, #ifdef CONFIG_CLK_R9A07G054 .drp = { From 31d5ef2f565d2378d9a615f89e4ff86d3d87eb80 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:54 +0100 Subject: [PATCH 49/66] clk: renesas: r9a07g044: Add M4 Clock support Add support for M4 clock which is sourced from pll2_533_div2. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index cee552bdf3cc7..66608696d2e23 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -57,6 +57,9 @@ enum clk_ids { CLK_SEL_GPU2, CLK_SEL_PLL5_4, CLK_DSI_DIV, + CLK_PLL2_533, + CLK_PLL2_533_DIV2, + CLK_DIV_DSI_LPCLK, /* Module Clocks */ MOD_CLK_BASE, @@ -80,6 +83,14 @@ static const struct clk_div_table dtable_1_32[] = { {0, 0}, }; +static const struct clk_div_table dtable_16_128[] = { + {0, 16}, + {1, 32}, + {2, 64}, + {3, 128}, + {0, 0}, +}; + /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; @@ -88,7 +99,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct { - struct cpg_core_clk common[52]; + struct cpg_core_clk common[56]; #ifdef CONFIG_CLK_R9A07G054 struct cpg_core_clk drp[0]; #endif @@ -102,6 +113,7 @@ static const struct { DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), @@ -120,6 +132,8 @@ static const struct { DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), + DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), @@ -137,6 +151,8 @@ static const struct { DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4, ARRAY_SIZE(sel_pll5_4)), + DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, + DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK), /* Core output clk */ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, @@ -169,6 +185,7 @@ static const struct { DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT), DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1), + DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1), }, #ifdef CONFIG_CLK_R9A07G054 .drp = { From 6f6178f1e1250d959ef19f408f0e392ea29de665 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:55 +0100 Subject: [PATCH 50/66] clk: renesas: r9a07g044: Add LCDC clock and reset entries Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 66608696d2e23..b5ddc50586700 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -194,7 +194,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[62]; + struct rzg2l_mod_clk common[65]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -254,6 +254,12 @@ static const struct { 0x558, 1), DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 0x558, 2), + DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, + 0x56c, 0), + DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, + 0x56c, 0), + DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, + 0x56c, 1), DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 0x570, 0), DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, @@ -349,6 +355,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), + DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), From 67f80edf8390fd8201bb285fe2b55df9e2e5edbe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 30 Apr 2022 12:41:56 +0100 Subject: [PATCH 51/66] clk: renesas: r9a07g044: Add DSI clock and reset entries Add DSI clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index b5ddc50586700..57ec50659bb33 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -194,7 +194,7 @@ static const struct { }; static const struct { - struct rzg2l_mod_clk common[65]; + struct rzg2l_mod_clk common[71]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif @@ -254,6 +254,18 @@ static const struct { 0x558, 1), DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 0x558, 2), + DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, + 0x568, 0), + DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, + 0x568, 1), + DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1, + 0x568, 2), + DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2, + 0x568, 3), + DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3, + 0x568, 4), + DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4, + 0x568, 5), DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, 0x56c, 0), DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, @@ -355,6 +367,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), + DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0), + DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1), + DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2), DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), From 4e683604cfc1322f609afcbe053e6821832d5f19 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 09:34:47 +0100 Subject: [PATCH 52/66] clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 3f3c5d1b7fec1..57b9eb9e0d2b7 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -28,9 +28,13 @@ enum clk_ids { CLK_PLL2_DIV2, CLK_PLL2_DIV2_8, CLK_PLL3, + CLK_PLL3_400, + CLK_PLL3_533, CLK_PLL3_DIV2, CLK_PLL3_DIV2_4, CLK_PLL3_DIV2_4_2, + CLK_SEL_PLL3_3, + CLK_DIV_PLL3_C, CLK_PLL5, CLK_PLL5_500, CLK_PLL5_250, @@ -67,6 +71,7 @@ static const struct clk_div_table dtable_1_32[] = { }; /* Mux clock tables */ +static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; @@ -89,6 +94,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), + DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), + DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), + DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, + sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), + DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, + DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), @@ -110,6 +121,8 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), + DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), + DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi, ARRAY_SIZE(sel_shdi)), DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, @@ -143,6 +156,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x548, 4), DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, 0x548, 5), + DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, + 0x550, 0), + DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, + 0x550, 1), DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, @@ -230,6 +247,7 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), + DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), From 14d8857d8266bce49dc4ee0d71e6cd79335d7c8c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 09:34:48 +0100 Subject: [PATCH 53/66] clk: renesas: r9a07g043: Add RSPI clock and reset entries Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 57b9eb9e0d2b7..21cf82ad7de3a 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -230,6 +230,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x588, 0), DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 0x588, 1), + DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, + 0x590, 0), + DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, + 0x590, 1), + DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, + 0x590, 2), DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, @@ -271,6 +277,9 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), + DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0), + DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1), + DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2), DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), From b67685300478ff768bde0d06a2a664a66223945f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 09:34:49 +0100 Subject: [PATCH 54/66] clk: renesas: r9a07g043: Add TSU clock and reset entry Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 21cf82ad7de3a..70b1226cf2947 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -27,6 +27,7 @@ enum clk_ids { CLK_PLL2, CLK_PLL2_DIV2, CLK_PLL2_DIV2_8, + CLK_PLL2_DIV2_10, CLK_PLL3, CLK_PLL3_400, CLK_PLL3_533, @@ -90,6 +91,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), @@ -112,6 +114,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), + DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), @@ -240,6 +243,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 0x598, 0), + DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, + 0x5ac, 0), }; static struct rzg2l_reset r9a07g043_resets[] = { @@ -285,6 +290,7 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { From 84c9829d16d86a09703d9f2c8dac3816c56bcdcd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 09:34:50 +0100 Subject: [PATCH 55/66] clk: renesas: r9a07g043: Add clock and reset entries for ADC Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 70b1226cf2947..7ef2c43ea8917 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -243,6 +243,10 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 0x598, 0), + DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, + 0x5a8, 1), DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 0x5ac, 0), }; @@ -290,6 +294,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), + DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), }; From 53c58c08b454aea3c9c9ceda600567436134e6a2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 14:35:02 +0200 Subject: [PATCH 56/66] clk: renesas: r9a07g044: Fix OSTM1 module clock name Fix a typo in the name of the "ostm1_pclk" clock. This change has no run-time impact. Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be --- drivers/clk/renesas/r9a07g044-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 57ec50659bb33..0a5c2265b842c 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -212,7 +212,7 @@ static const struct { 0x52c, 1), DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, 0x534, 0), - DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, + DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2), From 4a526957e6368597dea08175a67f0e15569f3958 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:48 +0100 Subject: [PATCH 57/66] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 311a935905973..8880b834f264c 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -4,14 +4,15 @@ $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode +title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode maintainers: - Geert Uytterhoeven description: | On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module - Standby Mode share the same register block. + Standby Mode share the same register block. On RZ/V2M, the functionality is + similar, but does not have Clock Monitor Registers. They provide the following functionalities: - The CPG block generates various core clocks, @@ -26,6 +27,7 @@ properties: - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a09g011-cpg # RZ/V2M reg: maxItems: 1 @@ -43,9 +45,10 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - + - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the . + a module number, as defined in the or + . const: 2 '#power-domain-cells': @@ -59,7 +62,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the . + the or . const: 1 required: From ceb3bfab2da49f804ec629a20f731611b9ece207 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:50 +0100 Subject: [PATCH 58/66] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro We only ever use ARRAY_SIZE() to populate the number of parents, so move this into the macro to always detect it automatically. This also makes the tables of clocks a little simpler. Similarly for the DEF_SD_MUX macro. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220503115557.53370-6-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 10 ++++------ drivers/clk/renesas/r9a07g044-cpg.c | 15 ++++++--------- drivers/clk/renesas/rzg2l-cpg.h | 16 +++++++++------- 3 files changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 7ef2c43ea8917..8241f5972de15 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -99,7 +99,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, - sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), + sel_pll3_3, 0, CLK_MUX_READ_ONLY), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), @@ -123,13 +123,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, - sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), + sel_pll6_2, 0, CLK_MUX_HIWORD_MASK), DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, - sel_shdi, ARRAY_SIZE(sel_shdi)), - DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, - sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), + DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 0a5c2265b842c..43c4d6b8ccf4c 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -139,18 +139,17 @@ static const struct { DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, - sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), + sel_pll3_3, 0, CLK_MUX_READ_ONLY), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, - sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), + sel_gpu2, 0, CLK_MUX_READ_ONLY), DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), - DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, - sel_pll5_4, ARRAY_SIZE(sel_pll5_4)), + DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK), @@ -169,13 +168,11 @@ static const struct { DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, - sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), + sel_pll6_2, 0, CLK_MUX_HIWORD_MASK), DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, - sel_shdi, ARRAY_SIZE(sel_shdi)), - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, - sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 1be29cec0cb2d..dfef1e2792fa2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -138,19 +138,21 @@ enum clk_types { #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, .flag = _flag) -#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \ - _mux_flags) \ +#define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ - .parent_names = _parent_names, .num_parents = _num_parents, \ + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names), \ .flag = _flag, .mux_flags = _mux_flags) -#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \ +#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ - .parent_names = _parent_names, .num_parents = _num_parents) + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names)) #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) -#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names, _num_parents) \ +#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ - .parent_names = _parent_names, .num_parents = _num_parents) + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names)) #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) From 8282fe0029e0db02fc21500790bfb621572fd28c Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:51 +0100 Subject: [PATCH 59/66] clk: renesas: rzg2l: Add read only versions of the clk macros This just makes the clk tables easier to read. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220503115557.53370-7-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 3 +-- drivers/clk/renesas/r9a07g044-cpg.c | 6 ++---- drivers/clk/renesas/rzg2l-cpg.h | 9 +++++++++ 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 8241f5972de15..fde934151b57c 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -98,8 +98,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), - DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, - sel_pll3_3, 0, CLK_MUX_READ_ONLY), + DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 43c4d6b8ccf4c..ee442684453b1 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -138,15 +138,13 @@ static const struct { DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), - DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, - sel_pll3_3, 0, CLK_MUX_READ_ONLY), + DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), - DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, - sel_gpu2, 0, CLK_MUX_READ_ONLY), + DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2), DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index dfef1e2792fa2..a6004f0b415a4 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -138,11 +138,20 @@ enum clk_types { #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, .flag = _flag) +#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ + .parent = _parent, .dtable = _dtable, \ + .flag = CLK_DIVIDER_READ_ONLY) #define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ .flag = _flag, .mux_flags = _mux_flags) +#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ + .parent_names = _parent_names, \ + .num_parents = ARRAY_SIZE(_parent_names), \ + .mux_flags = CLK_MUX_READ_ONLY) #define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ .parent_names = _parent_names, \ From 75b0ad42ccd9a87873e91598116471d9991b09ea Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:52 +0100 Subject: [PATCH 60/66] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers All of the muxes and dividers that can be modified require the HIWORD flags, so make the macros set them. It won't affect read only muxes and dividers. This will make the clock tables a little easier to read, particularly for new SoCs coming. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-8-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 18 ++++++------------ drivers/clk/renesas/r9a07g044-cpg.c | 23 ++++++++--------------- drivers/clk/renesas/rzg2l-cpg.h | 9 +++++---- 3 files changed, 19 insertions(+), 31 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index fde934151b57c..53a58034bef45 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -99,8 +99,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), - DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, - DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), @@ -108,21 +107,16 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), /* Core output clk */ - DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), - DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, - dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), + DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), - DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, - DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), - DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, - DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), - DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, - sel_pll6_2, 0, CLK_MUX_HIWORD_MASK), + DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index ee442684453b1..8255b39dc147c 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -139,8 +139,7 @@ static const struct { DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), - DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, - DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), @@ -149,32 +148,26 @@ static const struct { DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, - DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK), + DIVDSILPCLK, dtable_16_128), /* Core output clk */ - DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), - DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, - dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), + DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), - DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, - DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), - DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, - DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), - DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, - sel_pll6_2, 0, CLK_MUX_HIWORD_MASK), + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), - DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index a6004f0b415a4..59bbc8942e1db 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -135,18 +135,19 @@ enum clk_types { DEF_TYPE(_name, _id, CLK_TYPE_IN) #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) -#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ +#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ - .parent = _parent, .dtable = _dtable, .flag = _flag) + .parent = _parent, .dtable = _dtable, \ + .flag = CLK_DIVIDER_HIWORD_MASK) #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, \ .flag = CLK_DIVIDER_READ_ONLY) -#define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \ +#define DEF_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ - .flag = _flag, .mux_flags = _mux_flags) + .mux_flags = CLK_MUX_HIWORD_MASK) #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ .parent_names = _parent_names, \ From 63804400f2a5ababe596b4ec908321d6b54f45aa Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:53 +0100 Subject: [PATCH 61/66] clk: renesas: rzg2l: Make use of CLK_MON registers optional The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-9-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g043-cpg.c | 2 ++ drivers/clk/renesas/r9a07g044-cpg.c | 4 ++++ drivers/clk/renesas/rzg2l-cpg.c | 8 +++++++- drivers/clk/renesas/rzg2l-cpg.h | 3 +++ 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 53a58034bef45..33c2bd8df2e52 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -315,4 +315,6 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Resets */ .resets = r9a07g043_resets, .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 8255b39dc147c..b288897852c74 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -418,6 +418,8 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, }; #ifdef CONFIG_CLK_R9A07G054 @@ -440,5 +442,7 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = { /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, }; #endif diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index a1e1fee9f4832..48265276d1693 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -926,6 +926,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) if (!enable) return 0; + if (!priv->info->has_clk_mon_regs) + return 0; + for (i = 1000; i > 0; --i) { if (((readl(priv->base + CLK_MON_R(reg))) & bitmask)) break; @@ -996,7 +999,10 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw) if (clock->sibling) return clock->enabled; - value = readl(priv->base + CLK_MON_R(clock->off)); + if (priv->info->has_clk_mon_regs) + value = readl(priv->base + CLK_MON_R(clock->off)); + else + value = readl(priv->base + clock->off); return value & bitmask; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 59bbc8942e1db..43ce319a477f5 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -236,6 +236,7 @@ struct rzg2l_reset { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { /* Core Clocks */ @@ -256,6 +257,8 @@ struct rzg2l_cpg_info { /* Critical Module Clocks that should not be disabled */ const unsigned int *crit_mod_clks; unsigned int num_crit_mod_clks; + + bool has_clk_mon_regs; }; extern const struct rzg2l_cpg_info r9a07g043_cpg_info; From 8090bea32484d45b19b57577dee4519cbc28571c Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:54 +0100 Subject: [PATCH 62/66] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg The RZ/V2M doesn't have a matching set of reset monitor regs for each reset reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a single bit per module. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 10 +++++++++- drivers/clk/renesas/rzg2l-cpg.h | 10 ++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 48265276d1693..f8a68bbc76f29 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1177,8 +1177,16 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, const struct rzg2l_cpg_info *info = priv->info; unsigned int reg = info->resets[id].off; u32 bitmask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; - return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + if (info->has_clk_mon_regs) { + return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + } else if (monbit >= 0) { + u32 monbitmask = BIT(monbit); + + return !!(readl(priv->base + CPG_RST_MON) & monbitmask); + } + return -ENOTSUPP; } static const struct reset_control_ops rzg2l_cpg_reset_ops = { diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 43ce319a477f5..6fbb431fb3313 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -25,6 +25,7 @@ #define CPG_PL6_SSEL (0x414) #define CPG_PL6_ETH_SSEL (0x418) #define CPG_PL5_SDIV (0x420) +#define CPG_RST_MON (0x680) #define CPG_OTHERFUNC1_REG (0xBE8) #define CPG_SIPLL5_STBY_RESETB BIT(0) @@ -206,17 +207,22 @@ struct rzg2l_mod_clk { * * @off: register offset * @bit: reset bit + * @monbit: monitor bit in CPG_RST_MON register, -1 if none */ struct rzg2l_reset { u16 off; u8 bit; + s8 monbit; }; -#define DEF_RST(_id, _off, _bit) \ +#define DEF_RST_MON(_id, _off, _bit, _monbit) \ [_id] = { \ .off = (_off), \ - .bit = (_bit) \ + .bit = (_bit), \ + .monbit = (_monbit) \ } +#define DEF_RST(_id, _off, _bit) \ + DEF_RST_MON(_id, _off, _bit, -1) /** * struct rzg2l_cpg_info - SoC-specific CPG Description From 1dd65bb08604ad2906d839c243e1bede2b0efe53 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:55 +0100 Subject: [PATCH 63/66] clk: renesas: Add RZ/V2M support using the rzg2l driver The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g011-cpg.c | 168 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 + drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 181 insertions(+) create mode 100644 drivers/clk/renesas/r9a09g011-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 7e9b9a5bb5b7b..cacaf9b87d264 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -37,6 +37,7 @@ config CLK_RENESAS select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 + select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -178,6 +179,10 @@ config CLK_R9A07G054 bool "RZ/V2L clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A09G011 + bool "RZ/V2M clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index b83062af090c8..de907623fe3f8 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o +obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c new file mode 100644 index 0000000000000..b9f80c5318690 --- /dev/null +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + * Based on r9a07g044-cpg.c + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +#define RZV2M_SAMPLL4_CLK1 0x104 +#define RZV2M_SAMPLL4_CLK2 0x108 + +#define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12) + +#define DIV_A DDIV_PACK(0x200, 0, 3) +#define DIV_B DDIV_PACK(0x204, 0, 2) +#define DIV_E DDIV_PACK(0x204, 8, 1) +#define DIV_W DDIV_PACK(0x328, 0, 3) + +#define SEL_B SEL_PLL_PACK(0x214, 0, 1) +#define SEL_E SEL_PLL_PACK(0x214, 2, 1) +#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = 0, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_MAIN_24, + CLK_MAIN_2, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_800, + CLK_PLL2_400, + CLK_PLL2_200, + CLK_PLL2_100, + CLK_PLL4, + CLK_DIV_A, + CLK_DIV_B, + CLK_DIV_E, + CLK_DIV_W, + CLK_SEL_B, + CLK_SEL_B_D2, + CLK_SEL_E, + CLK_SEL_W0, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +/* Divider tables */ +static const struct clk_div_table dtable_diva[] = { + {0, 1}, + {1, 2}, + {2, 3}, + {3, 4}, + {4, 6}, + {5, 12}, + {6, 24}, + {0, 0}, +}; + +static const struct clk_div_table dtable_divb[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + +static const struct clk_div_table dtable_divw[] = { + {0, 6}, + {1, 7}, + {2, 8}, + {3, 9}, + {4, 10}, + {5, 11}, + {6, 12}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const sel_b[] = { ".main", ".divb" }; +static const char * const sel_e[] = { ".main", ".dive" }; +static const char * const sel_w[] = { ".main", ".divw" }; + +static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1), + DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2), + DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24), + DEF_FIXED(".pll1", CLK_PLL1, CLK_MAIN_2, 498, 1), + DEF_FIXED(".pll2", CLK_PLL2, CLK_MAIN_2, 800, 1), + DEF_FIXED(".pll2_800", CLK_PLL2_800, CLK_PLL2, 1, 2), + DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2), + DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4), + DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8), + DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF), + + DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva), + DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb), + DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL), + DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw), + + DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), + DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), + DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), + + DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), +}; + +static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { + DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), + DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), + DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), + DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), +}; + +static const struct rzg2l_reset r9a09g011_resets[] = { + DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), +}; + +static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + R9A09G011_CA53_CLK, + MOD_CLK_BASE + R9A09G011_GIC_CLK, + MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, + MOD_CLK_BASE + R9A09G011_URT_PCLK, +}; + +const struct rzg2l_cpg_info r9a09g011_cpg_info = { + /* Core Clocks */ + .core_clks = r9a09g011_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g011_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a09g011_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a09g011_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks), + .num_hw_mod_clks = R9A09G011_CA53_CLK + 1, + + /* Resets */ + .resets = r9a09g011_resets, + .num_resets = ARRAY_SIZE(r9a09g011_resets), + + .has_clk_mon_regs = false, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index f8a68bbc76f29..e2999ab2b53c4 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1406,6 +1406,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { .compatible = "renesas,r9a07g054-cpg", .data = &r9a07g054_cpg_info, }, +#endif +#ifdef CONFIG_CLK_R9A09G011 + { + .compatible = "renesas,r9a09g011-cpg", + .data = &r9a09g011_cpg_info, + }, #endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 6fbb431fb3313..cecbdf5e4f93a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -270,5 +270,6 @@ struct rzg2l_cpg_info { extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; +extern const struct rzg2l_cpg_info r9a09g011_cpg_info; #endif From 23426d1be3c20907b4f3d72bf95234d4ee254393 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 4 May 2022 15:54:46 +0100 Subject: [PATCH 64/66] clk: renesas: r9a09g011: Add eth clock and reset entries Add ethernet clock/reset entries to CPG driver. Note that the AXI and CHI clocks are both enabled and disabled using the same register bit. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g011-cpg.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index b9f80c5318690..40693bb85b801 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -126,14 +126,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { }; static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { - DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), - DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), - DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), - DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), - DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), + DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), + DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), + DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), + DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), + DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), + DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), + DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), }; static const struct rzg2l_reset r9a09g011_resets[] = { + DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), }; From b69b0adc71637d436883c5ed9bfadbfbb7e02fda Mon Sep 17 00:00:00 2001 From: Li Zhengyu Date: Mon, 9 May 2022 17:21:02 +0800 Subject: [PATCH 65/66] clk: fixed-rate: Remove redundant if statement (np) is always true when (dev || !np) is false, so just remove the check. Signed-off-by: Li Zhengyu Link: https://lore.kernel.org/r/20220509092102.140520-1-lizhengyu3@huawei.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-fixed-rate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index 45501637705c3..ac68a6b40f0e5 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -87,7 +87,7 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, hw = &fixed->hw; if (dev || !np) ret = clk_hw_register(dev, hw); - else if (np) + else ret = of_clk_hw_register(np, hw); if (ret) { kfree(fixed); From b7fa6242f3e035308a76284560e4f918dad9b017 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Fri, 20 May 2022 23:20:58 +0200 Subject: [PATCH 66/66] clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc() We should have 'n', then 'size', not the opposite. This is harmless because the 2 values are just multiplied, but having the correct order silence a (unpublished yet) smatch warning. Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/49d726d11964ca0e3757bdb5659e3b3eaa1572b5.1653081643.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-raspberrypi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c index 9d09621549b9b..73518009a0f20 100644 --- a/drivers/clk/bcm/clk-raspberrypi.c +++ b/drivers/clk/bcm/clk-raspberrypi.c @@ -345,7 +345,7 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi, int ret; clks = devm_kcalloc(rpi->dev, - sizeof(*clks), RPI_FIRMWARE_NUM_CLK_ID, + RPI_FIRMWARE_NUM_CLK_ID, sizeof(*clks), GFP_KERNEL); if (!clks) return -ENOMEM;