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MIPS: TXx9: Modernize printing of kernel messages
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- Convert from printk() to pr_*(),
  - Add missing continuations, to fix user-visible breakage,
  - Drop superfluous casts (u64 has been unsigned long long on all
    architectures for many years).

On rbtx4927, this restores the kernel output like:

    -TX4927 SDRAMC --
    - CR0:0000007e00000544
    - TR:32800030e
    +TX4927 SDRAMC -- CR0:0000007e00000544 TR:32800030e

and:

    -PCIC -- PCICLK:
    -Internal(33.3MHz)
    -
    +PCIC -- PCICLK:Internal(33.3MHz)

Fixes: 4bcc595 ("printk: reinstate KERN_CONT for printing continuation lines")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14646/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Geert Uytterhoeven authored and Ralf Baechle committed Jan 3, 2017
1 parent 2b58a76 commit 2cec11d
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Showing 12 changed files with 93 additions and 103 deletions.
22 changes: 11 additions & 11 deletions arch/mips/pci/pci-tx4927.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@ int __init tx4927_report_pciclk(void)
{
int pciclk = 0;

printk(KERN_INFO "PCIC --%s PCICLK:",
(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
" PCI66" : "");
pr_info("PCIC --%s PCICLK:",
(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
" PCI66" : "");
if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
switch ((unsigned long)ccfg &
Expand All @@ -37,14 +37,14 @@ int __init tx4927_report_pciclk(void)
case TX4927_CCFG_PCIDIVMODE_6:
pciclk = txx9_cpu_clock / 6; break;
}
printk("Internal(%u.%uMHz)",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
pr_cont("Internal(%u.%uMHz)",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
} else {
printk("External");
pr_cont("External");
pciclk = -1;
}
printk("\n");
pr_cont("\n");
return pciclk;
}

Expand Down Expand Up @@ -74,8 +74,8 @@ int __init tx4927_pciclk66_setup(void)
}
tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
pcidivmode);
printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
(unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
pr_debug("PCICLK: ccfg:%08lx\n",
(unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
} else
pciclk = -1;
return pciclk;
Expand All @@ -87,5 +87,5 @@ void __init tx4927_setup_pcierr_irq(void)
tx4927_pcierr_interrupt,
0, "PCI error",
(void *)TX4927_PCIC_REG))
printk(KERN_WARNING "Failed to request irq for PCIERR\n");
pr_warn("Failed to request irq for PCIERR\n");
}
30 changes: 15 additions & 15 deletions arch/mips/pci/pci-tx4938.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@ int __init tx4938_report_pciclk(void)
{
int pciclk = 0;

printk(KERN_INFO "PCIC --%s PCICLK:",
(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
" PCI66" : "");
pr_info("PCIC --%s PCICLK:",
(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
" PCI66" : "");
if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
switch ((unsigned long)ccfg &
Expand All @@ -45,14 +45,14 @@ int __init tx4938_report_pciclk(void)
case TX4938_CCFG_PCIDIVMODE_11:
pciclk = txx9_cpu_clock / 11; break;
}
printk("Internal(%u.%uMHz)",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
pr_cont("Internal(%u.%uMHz)",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
} else {
printk("External");
pr_cont("External");
pciclk = -1;
}
printk("\n");
pr_cont("\n");
return pciclk;
}

Expand All @@ -62,10 +62,10 @@ void __init tx4938_report_pci1clk(void)
unsigned int pciclk =
txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);

printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n",
(ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
pr_info("PCIC1 -- %sPCICLK:%u.%uMHz\n",
(ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
}

int __init tx4938_pciclk66_setup(void)
Expand Down Expand Up @@ -105,8 +105,8 @@ int __init tx4938_pciclk66_setup(void)
}
tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
pcidivmode);
printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
(unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
pr_debug("PCICLK: ccfg:%08lx\n",
(unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
} else
pciclk = -1;
return pciclk;
Expand Down Expand Up @@ -138,5 +138,5 @@ void __init tx4938_setup_pcierr_irq(void)
tx4927_pcierr_interrupt,
0, "PCI error",
(void *)TX4927_PCIC_REG))
printk(KERN_WARNING "Failed to request irq for PCIERR\n");
pr_warn("Failed to request irq for PCIERR\n");
}
10 changes: 5 additions & 5 deletions arch/mips/pci/pci-tx4939.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,14 +28,14 @@ int __init tx4939_report_pciclk(void)
pciclk = txx9_master_clock * 20 / 6;
if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
pciclk /= 2;
printk(KERN_CONT "Internal(%u.%uMHz)",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
pr_cont("Internal(%u.%uMHz)",
(pciclk + 50000) / 1000000,
((pciclk + 50000) / 100000) % 10);
} else {
printk(KERN_CONT "External");
pr_cont("External");
pciclk = -1;
}
printk(KERN_CONT "\n");
pr_cont("\n");
return pciclk;
}

Expand Down
28 changes: 13 additions & 15 deletions arch/mips/txx9/generic/pci.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
/* It seems SLC90E66 needs some time after PCI reset... */
mdelay(80);

printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
pr_info("PCI: Checking 66MHz capabilities...\n");

for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
if (PCI_FUNC(pci_devfn))
Expand All @@ -74,9 +74,8 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_STATUS, &stat);
if (!(stat & PCI_STATUS_66MHZ)) {
printk(KERN_DEBUG
"PCI: %02x:%02x not 66MHz capable.\n",
current_bus, pci_devfn);
pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
current_bus, pci_devfn);
cap66 = 0;
break;
}
Expand Down Expand Up @@ -209,8 +208,8 @@ txx9_alloc_pci_controller(struct pci_controller *pcic,

pcic->mem_offset = 0; /* busaddr == physaddr */

printk(KERN_INFO "PCI: IO %pR MEM %pR\n",
&pcic->mem_resource[1], &pcic->mem_resource[0]);
pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
&pcic->mem_resource[0]);

/* register_pci_controller() will request MEM resource */
release_resource(&pcic->mem_resource[0]);
Expand All @@ -219,7 +218,7 @@ txx9_alloc_pci_controller(struct pci_controller *pcic,
release_resource(&pcic->mem_resource[0]);
free_and_exit:
kfree(new);
printk(KERN_ERR "PCI: Failed to allocate resources.\n");
pr_err("PCI: Failed to allocate resources.\n");
return NULL;
}

Expand Down Expand Up @@ -260,7 +259,7 @@ static int txx9_i8259_irq_setup(int irq)
err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
"cascade(i8259)", (void *)(long)irq);
if (!err)
printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
return err;
}

Expand Down Expand Up @@ -308,13 +307,13 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
/* enable SMSC SLC90E66 IDE */
for (i = 0; i < ARRAY_SIZE(regs); i++) {
pci_read_config_byte(dev, regs[i], &dat);
pci_write_config_byte(dev, regs[i], dat | 0x80);
pci_read_config_byte(dev, regs[i], &dat);
printk(KERN_CONT " IDETIM%d %02x", i, dat);
pr_cont(" IDETIM%d %02x", i, dat);
}
pci_read_config_byte(dev, 0x5c, &dat);
/*
Expand All @@ -329,8 +328,7 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
dat |= 0x01;
pci_write_config_byte(dev, 0x5c, dat);
pci_read_config_byte(dev, 0x5c, &dat);
printk(KERN_CONT " REG5C %02x", dat);
printk(KERN_CONT "\n");
pr_cont(" REG5C %02x\n", dat);
}
#endif /* CONFIG_TOSHIBA_FPCIB0 */

Expand All @@ -352,7 +350,7 @@ static void final_fixup(struct pci_dev *dev)
(bist & PCI_BIST_CAPABLE)) {
unsigned long timeout;
pci_set_power_state(dev, PCI_D0);
printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
pr_info("PCI: %s BIST...", pci_name(dev));
pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
timeout = jiffies + HZ * 2; /* timeout after 2 sec */
do {
Expand All @@ -361,9 +359,9 @@ static void final_fixup(struct pci_dev *dev)
break;
} while (bist & PCI_BIST_START);
if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
printk(KERN_CONT "failed. (0x%x)\n", bist);
pr_cont("failed. (0x%x)\n", bist);
else
printk(KERN_CONT "OK.\n");
pr_cont("OK.\n");
}
}

Expand Down
6 changes: 3 additions & 3 deletions arch/mips/txx9/generic/setup_tx3927.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ void __init tx3927_setup(void)
/* do reset on watchdog */
tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;

printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
tx3927_ccfgptr->crir,
tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
pr_info("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg,
tx3927_ccfgptr->pcfg);

/* TMR */
for (i = 0; i < TX3927_NR_TMR; i++)
Expand Down
20 changes: 9 additions & 11 deletions arch/mips/txx9/generic/setup_tx4927.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -183,31 +183,29 @@ void __init tx4927_setup(void)
if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);

printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
txx9_pcode_str,
(cpuclk + 500000) / 1000000,
(txx9_master_clock + 500000) / 1000000,
(__u32)____raw_readq(&tx4927_ccfgptr->crir),
(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
(unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
txx9_pcode_str, (cpuclk + 500000) / 1000000,
(txx9_master_clock + 500000) / 1000000,
(__u32)____raw_readq(&tx4927_ccfgptr->crir),
____raw_readq(&tx4927_ccfgptr->ccfg),
____raw_readq(&tx4927_ccfgptr->pcfg));

printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
pr_info("%s SDRAMC --", txx9_pcode_str);
for (i = 0; i < 4; i++) {
__u64 cr = TX4927_SDRAMC_CR(i);
unsigned long base, size;
if (!((__u32)cr & 0x00000400))
continue; /* disabled */
base = (unsigned long)(cr >> 49) << 21;
size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
printk(" CR%d:%016llx", i, (unsigned long long)cr);
pr_cont(" CR%d:%016llx", i, cr);
tx4927_sdram_resource[i].name = "SDRAM";
tx4927_sdram_resource[i].start = base;
tx4927_sdram_resource[i].end = base + size - 1;
tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
}
printk(" TR:%09llx\n",
(unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
pr_cont(" TR:%09llx\n", ____raw_readq(&tx4927_sdramcptr->tr));

/* TMR */
/* disable all timers */
Expand Down
28 changes: 13 additions & 15 deletions arch/mips/txx9/generic/setup_tx4938.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -196,31 +196,29 @@ void __init tx4938_setup(void)
if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);

printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
txx9_pcode_str,
(cpuclk + 500000) / 1000000,
(txx9_master_clock + 500000) / 1000000,
(__u32)____raw_readq(&tx4938_ccfgptr->crir),
(unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
(unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));

printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
txx9_pcode_str, (cpuclk + 500000) / 1000000,
(txx9_master_clock + 500000) / 1000000,
(__u32)____raw_readq(&tx4938_ccfgptr->crir),
____raw_readq(&tx4938_ccfgptr->ccfg),
____raw_readq(&tx4938_ccfgptr->pcfg));

pr_info("%s SDRAMC --", txx9_pcode_str);
for (i = 0; i < 4; i++) {
__u64 cr = TX4938_SDRAMC_CR(i);
unsigned long base, size;
if (!((__u32)cr & 0x00000400))
continue; /* disabled */
base = (unsigned long)(cr >> 49) << 21;
size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
printk(" CR%d:%016llx", i, (unsigned long long)cr);
pr_cont(" CR%d:%016llx", i, cr);
tx4938_sdram_resource[i].name = "SDRAM";
tx4938_sdram_resource[i].start = base;
tx4938_sdram_resource[i].end = base + size - 1;
tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
}
printk(" TR:%09llx\n",
(unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
pr_cont(" TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));

/* SRAM */
if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
Expand Down Expand Up @@ -254,20 +252,20 @@ void __init tx4938_setup(void)
txx9_clear64(&tx4938_ccfgptr->clkctr,
TX4938_CLKCTR_PCIC1RST);
} else {
printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
pr_info("%s: stop PCIC1\n", txx9_pcode_str);
/* stop PCIC1 */
txx9_set64(&tx4938_ccfgptr->clkctr,
TX4938_CLKCTR_PCIC1CKD);
}
if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
pr_info("%s: stop ETH0\n", txx9_pcode_str);
txx9_set64(&tx4938_ccfgptr->clkctr,
TX4938_CLKCTR_ETH0RST);
txx9_set64(&tx4938_ccfgptr->clkctr,
TX4938_CLKCTR_ETH0CKD);
}
if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
pr_info("%s: stop ETH1\n", txx9_pcode_str);
txx9_set64(&tx4938_ccfgptr->clkctr,
TX4938_CLKCTR_ETH1RST);
txx9_set64(&tx4938_ccfgptr->clkctr,
Expand Down
8 changes: 4 additions & 4 deletions arch/mips/txx9/generic/setup_tx4939.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -221,16 +221,16 @@ void __init tx4939_setup(void)
(txx9_master_clock + 500000) / 1000000,
(txx9_gbus_clock + 500000) / 1000000,
(__u32)____raw_readq(&tx4939_ccfgptr->crir),
(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
(unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
____raw_readq(&tx4939_ccfgptr->ccfg),
____raw_readq(&tx4939_ccfgptr->pcfg));

pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
(__u32)____raw_readq(&tx4939_ddrcptr->winen));
for (i = 0; i < 4; i++) {
__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
continue; /* disabled */
printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
pr_cont(" #%d:%016llx", i, win);
tx4939_sdram_resource[i].name = "DDR SDRAM";
tx4939_sdram_resource[i].start =
(unsigned long)(win >> 48) << 20;
Expand All @@ -240,7 +240,7 @@ void __init tx4939_setup(void)
tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
}
printk(KERN_CONT "\n");
pr_cont("\n");

/* SRAM */
if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
Expand Down
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