From 32241e8c06f79df2b13f7aaf0277b6fccf81ff44 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sun, 25 Jun 2017 15:08:46 -0500 Subject: [PATCH] powerpc: Only do ERAT invalidate on radix context switch on P9 DD1 BugLink: http://bugs.launchpad.net/bugs/1700819 On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID register will implicitly invalidate the user space ERAT entries and leave the kernel ones alone. Thus the only thing needed is an isync() to synchronize this with subsequent uaccess's Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Ellerman (cherry picked from commit 74e27c6af56fe6898c3c8c451595746a992f0f0f linux-next) Signed-off-by: Breno Leitao Signed-off-by: Seth Forshee --- arch/powerpc/mm/mmu_context_book3s64.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c index a3edf813d4556..71de2c6d88f34 100644 --- a/arch/powerpc/mm/mmu_context_book3s64.c +++ b/arch/powerpc/mm/mmu_context_book3s64.c @@ -235,10 +235,15 @@ void destroy_context(struct mm_struct *mm) #ifdef CONFIG_PPC_RADIX_MMU void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) { - asm volatile("isync": : :"memory"); - mtspr(SPRN_PID, next->context.id); - asm volatile("isync \n" - PPC_SLBIA(0x7) - : : :"memory"); + + if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { + isync(); + mtspr(SPRN_PID, next->context.id); + isync(); + asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); + } else { + mtspr(SPRN_PID, next->context.id); + isync(); + } } #endif