From 54f1618b951fde7803bf5cbdc17412c5165c26fe Mon Sep 17 00:00:00 2001 From: "xianwei.zhao" Date: Mon, 11 Sep 2023 10:52:21 +0800 Subject: [PATCH 01/56] dt-bindings: power: add Amlogic T7 power domains Add devicetree binding document and related header file for Amlogic T7 secure power domains. Signed-off-by: xianwei.zhao Acked-by: Conor Dooley Tested-by: Lucas Tanure Link: https://lore.kernel.org/r/20230911025223.3433776-5-xianwei.zhao@amlogic.com Signed-off-by: Ulf Hansson --- .../power/amlogic,meson-sec-pwrc.yaml | 3 +- include/dt-bindings/power/amlogic,t7-pwrc.h | 63 +++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/power/amlogic,t7-pwrc.h diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index d80bbedfe3aaf..dab3d92bc2730 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -12,7 +12,7 @@ maintainers: - Jianxin Pan description: |+ - Secure Power Domains used in Meson A1/C1/S4 & C3 SoCs, and should be the child node + Secure Power Domains used in Meson A1/C1/S4 & C3/T7 SoCs, and should be the child node of secure-monitor. properties: @@ -21,6 +21,7 @@ properties: - amlogic,meson-a1-pwrc - amlogic,meson-s4-pwrc - amlogic,c3-pwrc + - amlogic,t7-pwrc "#power-domain-cells": const: 1 diff --git a/include/dt-bindings/power/amlogic,t7-pwrc.h b/include/dt-bindings/power/amlogic,t7-pwrc.h new file mode 100644 index 0000000000000..1f1f2739cc265 --- /dev/null +++ b/include/dt-bindings/power/amlogic,t7-pwrc.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. + * Author: Hongyu Chen + */ +#ifndef _DT_BINDINGS_AMLOGIC_T7_POWER_H +#define _DT_BINDINGS_AMLOGIC_T7_POWER_H + +#define PWRC_T7_DSPA_ID 0 +#define PWRC_T7_DSPB_ID 1 +#define PWRC_T7_DOS_HCODEC_ID 2 +#define PWRC_T7_DOS_HEVC_ID 3 +#define PWRC_T7_DOS_VDEC_ID 4 +#define PWRC_T7_DOS_WAVE_ID 5 +#define PWRC_T7_VPU_HDMI_ID 6 +#define PWRC_T7_USB_COMB_ID 7 +#define PWRC_T7_PCIE_ID 8 +#define PWRC_T7_GE2D_ID 9 +#define PWRC_T7_SRAMA_ID 10 +#define PWRC_T7_SRAMB_ID 11 +#define PWRC_T7_HDMIRX_ID 12 +#define PWRC_T7_VI_CLK1_ID 13 +#define PWRC_T7_VI_CLK2_ID 14 +#define PWRC_T7_ETH_ID 15 +#define PWRC_T7_ISP_ID 16 +#define PWRC_T7_MIPI_ISP_ID 17 +#define PWRC_T7_GDC_ID 18 +#define PWRC_T7_CVE_ID 18 +#define PWRC_T7_DEWARP_ID 19 +#define PWRC_T7_SDIO_A_ID 20 +#define PWRC_T7_SDIO_B_ID 21 +#define PWRC_T7_EMMC_ID 22 +#define PWRC_T7_MALI_SC0_ID 23 +#define PWRC_T7_MALI_SC1_ID 24 +#define PWRC_T7_MALI_SC2_ID 25 +#define PWRC_T7_MALI_SC3_ID 26 +#define PWRC_T7_MALI_TOP_ID 27 +#define PWRC_T7_NNA_CORE0_ID 28 +#define PWRC_T7_NNA_CORE1_ID 29 +#define PWRC_T7_NNA_CORE2_ID 30 +#define PWRC_T7_NNA_CORE3_ID 31 +#define PWRC_T7_NNA_TOP_ID 32 +#define PWRC_T7_DDR0_ID 33 +#define PWRC_T7_DDR1_ID 34 +#define PWRC_T7_DMC0_ID 35 +#define PWRC_T7_DMC1_ID 36 +#define PWRC_T7_NOC_ID 37 +#define PWRC_T7_NIC2_ID 38 +#define PWRC_T7_NIC3_ID 39 +#define PWRC_T7_CCI_ID 40 +#define PWRC_T7_MIPI_DSI0_ID 41 +#define PWRC_T7_SPICC0_ID 42 +#define PWRC_T7_SPICC1_ID 43 +#define PWRC_T7_SPICC2_ID 44 +#define PWRC_T7_SPICC3_ID 45 +#define PWRC_T7_SPICC4_ID 46 +#define PWRC_T7_SPICC5_ID 47 +#define PWRC_T7_EDP0_ID 48 +#define PWRC_T7_EDP1_ID 49 +#define PWRC_T7_MIPI_DSI1_ID 50 +#define PWRC_T7_AUDIO_ID 51 + +#endif From 278adec9392ee4dd5629fae43ce9f4a9825bdf9a Mon Sep 17 00:00:00 2001 From: "xianwei.zhao" Date: Mon, 11 Sep 2023 10:52:18 +0800 Subject: [PATCH 02/56] pmdomain: amlogic: modify some power domains property Some power domains for C3 can be using runtime PM, remove ALWAYS_ON property. And add some power domains description when ALWAYS_ON property. Signed-off-by: xianwei.zhao Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230911025223.3433776-2-xianwei.zhao@amlogic.com [Ulf: Re-based to fit the pmdomain subsystem] Signed-off-by: Ulf Hansson --- drivers/pmdomain/amlogic/meson-secure-pwrc.c | 25 ++++++++++---------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c index 89c881c56cd77..5ac2437ab8adb 100644 --- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c @@ -122,18 +122,19 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { }; static struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = { - SEC_PD(C3_NNA, 0), - SEC_PD(C3_AUDIO, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_SDIOA, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_EMMC, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_USB_COMB, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_SDCARD, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_ETH, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_GE2D, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_CVE, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_GDC_WRAP, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_ISP_TOP, GENPD_FLAG_ALWAYS_ON), - SEC_PD(C3_MIPI_ISP_WRAP, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_NNA, 0), + SEC_PD(C3_AUDIO, 0), + SEC_PD(C3_SDIOA, 0), + SEC_PD(C3_EMMC, 0), + SEC_PD(C3_USB_COMB, 0), + SEC_PD(C3_SDCARD, 0), + /* ETH is for ethernet online wakeup, and should be always on */ + SEC_PD(C3_ETH, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_GE2D, 0), + SEC_PD(C3_CVE, 0), + SEC_PD(C3_GDC_WRAP, 0), + SEC_PD(C3_ISP_TOP, 0), + SEC_PD(C3_MIPI_ISP_WRAP, 0), SEC_PD(C3_VCODEC, 0), }; From efa529b31afe50b88f26a529352c8213e82d61be Mon Sep 17 00:00:00 2001 From: "xianwei.zhao" Date: Mon, 11 Sep 2023 10:52:19 +0800 Subject: [PATCH 03/56] pmdomain: amlogic: add driver to support power parent node Some power domains depends on other domains, Such as Amlogic T7 SoC. Add parent node to support this case. Signed-off-by: xianwei.zhao Link: https://lore.kernel.org/r/20230911025223.3433776-3-xianwei.zhao@amlogic.com [Ulf: Re-based to fit the pmdomain subsystem] Signed-off-by: Ulf Hansson --- drivers/pmdomain/amlogic/meson-secure-pwrc.c | 26 +++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c index 5ac2437ab8adb..ecada537b19c9 100644 --- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c @@ -19,10 +19,12 @@ #define PWRC_ON 1 #define PWRC_OFF 0 +#define PWRC_NO_PARENT UINT_MAX struct meson_secure_pwrc_domain { struct generic_pm_domain base; unsigned int index; + unsigned int parent; struct meson_secure_pwrc *pwrc; }; @@ -34,6 +36,7 @@ struct meson_secure_pwrc { struct meson_secure_pwrc_domain_desc { unsigned int index; + unsigned int parent; unsigned int flags; char *name; bool (*is_off)(struct meson_secure_pwrc_domain *pwrc_domain); @@ -90,8 +93,19 @@ static int meson_secure_pwrc_on(struct generic_pm_domain *domain) { \ .name = #__name, \ .index = PWRC_##__name##_ID, \ - .is_off = pwrc_secure_is_off, \ + .is_off = pwrc_secure_is_off, \ .flags = __flag, \ + .parent = PWRC_NO_PARENT, \ +} + +#define TOP_PD(__name, __flag, __parent) \ +[PWRC_##__name##_ID] = \ +{ \ + .name = #__name, \ + .index = PWRC_##__name##_ID, \ + .is_off = pwrc_secure_is_off, \ + .flags = __flag, \ + .parent = __parent, \ } static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { @@ -202,6 +216,7 @@ static int meson_secure_pwrc_probe(struct platform_device *pdev) dom->pwrc = pwrc; dom->index = match->domains[i].index; + dom->parent = match->domains[i].parent; dom->base.name = match->domains[i].name; dom->base.flags = match->domains[i].flags; dom->base.power_on = meson_secure_pwrc_on; @@ -212,6 +227,15 @@ static int meson_secure_pwrc_probe(struct platform_device *pdev) pwrc->xlate.domains[i] = &dom->base; } + for (i = 0; i < match->count; i++) { + struct meson_secure_pwrc_domain *dom = pwrc->domains; + + if (!match->domains[i].name || match->domains[i].parent == PWRC_NO_PARENT) + continue; + + pm_genpd_add_subdomain(&dom[dom[i].parent].base, &dom[i].base); + } + return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate); } From 0a7bd33c996893cff1d1e680c9ea7f9c90b12560 Mon Sep 17 00:00:00 2001 From: "xianwei.zhao" Date: Mon, 11 Sep 2023 10:52:20 +0800 Subject: [PATCH 04/56] pmdomain: amlogic: init power domain state If initial power domain with 'AWAY_ON' property state is off, turn on the power. Signed-off-by: xianwei.zhao Link: https://lore.kernel.org/r/20230911025223.3433776-4-xianwei.zhao@amlogic.com [Ulf: Re-based to fit the pmdomain subsystem] Signed-off-by: Ulf Hansson --- drivers/pmdomain/amlogic/meson-secure-pwrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c index ecada537b19c9..d751c224048dc 100644 --- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c @@ -222,6 +222,9 @@ static int meson_secure_pwrc_probe(struct platform_device *pdev) dom->base.power_on = meson_secure_pwrc_on; dom->base.power_off = meson_secure_pwrc_off; + if (match->domains[i].is_off(dom) && (dom->base.flags & GENPD_FLAG_ALWAYS_ON)) + meson_secure_pwrc_on(&dom->base); + pm_genpd_init(&dom->base, NULL, match->domains[i].is_off(dom)); pwrc->xlate.domains[i] = &dom->base; From ca75e4b214c6614db666db7b5be6fe4d5e2e73b2 Mon Sep 17 00:00:00 2001 From: "xianwei.zhao" Date: Mon, 11 Sep 2023 10:52:22 +0800 Subject: [PATCH 05/56] pmdomain: amlogic: Add support for T7 power domains controller Add support for T7 power controller. T7 power control registers are in secure domain, and should be accessed by SMC. Signed-off-by: xianwei.zhao Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230911025223.3433776-6-xianwei.zhao@amlogic.com [Ulf: Re-based to fit the pmdomain subsystem] Signed-off-by: Ulf Hansson --- drivers/pmdomain/amlogic/meson-secure-pwrc.c | 73 ++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/pmdomain/amlogic/meson-secure-pwrc.c b/drivers/pmdomain/amlogic/meson-secure-pwrc.c index d751c224048dc..4d5bda0d60fc8 100644 --- a/drivers/pmdomain/amlogic/meson-secure-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-secure-pwrc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -164,6 +165,69 @@ static struct meson_secure_pwrc_domain_desc s4_pwrc_domains[] = { SEC_PD(S4_AUDIO, 0), }; +static struct meson_secure_pwrc_domain_desc t7_pwrc_domains[] = { + SEC_PD(T7_DSPA, 0), + SEC_PD(T7_DSPB, 0), + TOP_PD(T7_DOS_HCODEC, 0, PWRC_T7_NIC3_ID), + TOP_PD(T7_DOS_HEVC, 0, PWRC_T7_NIC3_ID), + TOP_PD(T7_DOS_VDEC, 0, PWRC_T7_NIC3_ID), + TOP_PD(T7_DOS_WAVE, 0, PWRC_T7_NIC3_ID), + SEC_PD(T7_VPU_HDMI, 0), + SEC_PD(T7_USB_COMB, 0), + SEC_PD(T7_PCIE, 0), + TOP_PD(T7_GE2D, 0, PWRC_T7_NIC3_ID), + /* SRAMA is used as ATF runtime memory, and should be always on */ + SEC_PD(T7_SRAMA, GENPD_FLAG_ALWAYS_ON), + /* SRAMB is used as ATF runtime memory, and should be always on */ + SEC_PD(T7_SRAMB, GENPD_FLAG_ALWAYS_ON), + SEC_PD(T7_HDMIRX, 0), + SEC_PD(T7_VI_CLK1, 0), + SEC_PD(T7_VI_CLK2, 0), + /* ETH is for ethernet online wakeup, and should be always on */ + SEC_PD(T7_ETH, GENPD_FLAG_ALWAYS_ON), + SEC_PD(T7_ISP, 0), + SEC_PD(T7_MIPI_ISP, 0), + TOP_PD(T7_GDC, 0, PWRC_T7_NIC3_ID), + TOP_PD(T7_DEWARP, 0, PWRC_T7_NIC3_ID), + SEC_PD(T7_SDIO_A, 0), + SEC_PD(T7_SDIO_B, 0), + SEC_PD(T7_EMMC, 0), + TOP_PD(T7_MALI_SC0, 0, PWRC_T7_NNA_TOP_ID), + TOP_PD(T7_MALI_SC1, 0, PWRC_T7_NNA_TOP_ID), + TOP_PD(T7_MALI_SC2, 0, PWRC_T7_NNA_TOP_ID), + TOP_PD(T7_MALI_SC3, 0, PWRC_T7_NNA_TOP_ID), + SEC_PD(T7_MALI_TOP, 0), + TOP_PD(T7_NNA_CORE0, 0, PWRC_T7_NNA_TOP_ID), + TOP_PD(T7_NNA_CORE1, 0, PWRC_T7_NNA_TOP_ID), + TOP_PD(T7_NNA_CORE2, 0, PWRC_T7_NNA_TOP_ID), + TOP_PD(T7_NNA_CORE3, 0, PWRC_T7_NNA_TOP_ID), + SEC_PD(T7_NNA_TOP, 0), + SEC_PD(T7_DDR0, GENPD_FLAG_ALWAYS_ON), + SEC_PD(T7_DDR1, GENPD_FLAG_ALWAYS_ON), + /* DMC0 is for DDR PHY ana/dig and DMC, and should be always on */ + SEC_PD(T7_DMC0, GENPD_FLAG_ALWAYS_ON), + /* DMC1 is for DDR PHY ana/dig and DMC, and should be always on */ + SEC_PD(T7_DMC1, GENPD_FLAG_ALWAYS_ON), + /* NOC is related to clk bus, and should be always on */ + SEC_PD(T7_NOC, GENPD_FLAG_ALWAYS_ON), + /* NIC is for the Arm NIC-400 interconnect, and should be always on */ + SEC_PD(T7_NIC2, GENPD_FLAG_ALWAYS_ON), + SEC_PD(T7_NIC3, 0), + /* CPU accesses the interleave data to the ddr need cci, and should be always on */ + SEC_PD(T7_CCI, GENPD_FLAG_ALWAYS_ON), + SEC_PD(T7_MIPI_DSI0, 0), + SEC_PD(T7_SPICC0, 0), + SEC_PD(T7_SPICC1, 0), + SEC_PD(T7_SPICC2, 0), + SEC_PD(T7_SPICC3, 0), + SEC_PD(T7_SPICC4, 0), + SEC_PD(T7_SPICC5, 0), + SEC_PD(T7_EDP0, 0), + SEC_PD(T7_EDP1, 0), + SEC_PD(T7_MIPI_DSI1, 0), + SEC_PD(T7_AUDIO, 0), +}; + static int meson_secure_pwrc_probe(struct platform_device *pdev) { int i; @@ -257,6 +321,11 @@ static struct meson_secure_pwrc_domain_data meson_secure_s4_pwrc_data = { .count = ARRAY_SIZE(s4_pwrc_domains), }; +static struct meson_secure_pwrc_domain_data amlogic_secure_t7_pwrc_data = { + .domains = t7_pwrc_domains, + .count = ARRAY_SIZE(t7_pwrc_domains), +}; + static const struct of_device_id meson_secure_pwrc_match_table[] = { { .compatible = "amlogic,meson-a1-pwrc", @@ -270,6 +339,10 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = { .compatible = "amlogic,meson-s4-pwrc", .data = &meson_secure_s4_pwrc_data, }, + { + .compatible = "amlogic,t7-pwrc", + .data = &amlogic_secure_t7_pwrc_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_secure_pwrc_match_table); From e925bcee7d8ddd6e8990c81c89d90a06014b8ba5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 13 Sep 2023 14:54:24 +0100 Subject: [PATCH 06/56] pmdomain: starfive: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230913-swooned-ecosphere-aff4a05c1556@spud Signed-off-by: Ulf Hansson --- drivers/pmdomain/starfive/jh71xx-pmu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pmdomain/starfive/jh71xx-pmu.c b/drivers/pmdomain/starfive/jh71xx-pmu.c index 7d5f50d71c0dd..d3b78a619d405 100644 --- a/drivers/pmdomain/starfive/jh71xx-pmu.c +++ b/drivers/pmdomain/starfive/jh71xx-pmu.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include From 41b66b54a72bd796988377bb78f5a0eae6fb5156 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Wed, 13 Sep 2023 14:54:25 +0100 Subject: [PATCH 07/56] dt-bindings: power: Add power-domain header for JH7110 Add power-domain header for JH7110 SoC, it can use to operate dphy power. Signed-off-by: Changhuang Liang Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230913-grumbly-rewrite-34c85539f2ed@spud Signed-off-by: Ulf Hansson --- include/dt-bindings/power/starfive,jh7110-pmu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h index 132bfe401fc89..341e2a0676ba0 100644 --- a/include/dt-bindings/power/starfive,jh7110-pmu.h +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: Walker Chen */ #ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ @@ -14,4 +14,7 @@ #define JH7110_PD_ISP 5 #define JH7110_PD_VENC 6 +#define JH7110_PD_DPHY_TX 0 +#define JH7110_PD_DPHY_RX 1 + #endif From 6238fda156b498269aa66917de0d1342e90cead1 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Wed, 13 Sep 2023 14:54:26 +0100 Subject: [PATCH 08/56] pmdomain: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Conor Dooley Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230913-legibly-treachery-567cffcb5604@spud Signed-off-by: Ulf Hansson --- drivers/soc/starfive/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index bdb96dc4c9891..1e9b0c414fec7 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -3,8 +3,8 @@ config JH71XX_PMU bool "Support PMU for StarFive JH71XX Soc" depends on PM - depends on SOC_STARFIVE || COMPILE_TEST - default SOC_STARFIVE + depends on ARCH_STARFIVE || COMPILE_TEST + default ARCH_STARFIVE select PM_GENERIC_DOMAINS help Say 'y' here to enable support power domain support. From 296eea56129bdb30680d97b5297b2e6c598976f1 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Wed, 13 Sep 2023 14:54:27 +0100 Subject: [PATCH 09/56] pmdomain: starfive: Extract JH7110 pmu private operations Move JH7110 private operation into private data of compatible. Convenient to add AON PMU which would not have interrupts property. Signed-off-by: Changhuang Liang Reviewed-by: Walker Chen Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230913-slideshow-luckiness-38ff17de84c6@spud Signed-off-by: Ulf Hansson --- drivers/pmdomain/starfive/jh71xx-pmu.c | 89 ++++++++++++++++++-------- 1 file changed, 62 insertions(+), 27 deletions(-) diff --git a/drivers/pmdomain/starfive/jh71xx-pmu.c b/drivers/pmdomain/starfive/jh71xx-pmu.c index d3b78a619d405..547cd3b9df114 100644 --- a/drivers/pmdomain/starfive/jh71xx-pmu.c +++ b/drivers/pmdomain/starfive/jh71xx-pmu.c @@ -50,9 +50,17 @@ struct jh71xx_domain_info { u8 bit; }; +struct jh71xx_pmu; +struct jh71xx_pmu_dev; + struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; + unsigned int pmu_status; + int (*pmu_parse_irq)(struct platform_device *pdev, + struct jh71xx_pmu *pmu); + int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd, + u32 mask, bool on); }; struct jh71xx_pmu { @@ -78,12 +86,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o if (!mask) return -EINVAL; - *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; + *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; return 0; } -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) { struct jh71xx_pmu *pmu = pmd->pmu; unsigned long flags; @@ -91,22 +99,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) u32 mode; u32 encourage_lo; u32 encourage_hi; - bool is_on; int ret; - ret = jh71xx_pmu_get_state(pmd, mask, &is_on); - if (ret) { - dev_dbg(pmu->dev, "unable to get current state for %s\n", - pmd->genpd.name); - return ret; - } - - if (is_on == on) { - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", - pmd->genpd.name, on ? "en" : "dis"); - return 0; - } - spin_lock_irqsave(&pmu->lock, flags); /* @@ -165,6 +159,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) return 0; } +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +{ + struct jh71xx_pmu *pmu = pmd->pmu; + const struct jh71xx_pmu_match_data *match_data = pmu->match_data; + bool is_on; + int ret; + + ret = jh71xx_pmu_get_state(pmd, mask, &is_on); + if (ret) { + dev_dbg(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + return ret; + } + + if (is_on == on) { + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", + pmd->genpd.name, on ? "en" : "dis"); + return 0; + } + + return match_data->pmu_set_state(pmd, mask, on); +} + static int jh71xx_pmu_on(struct generic_pm_domain *genpd) { struct jh71xx_pmu_dev *pmd = container_of(genpd, @@ -225,6 +242,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data) return IRQ_HANDLED; } +static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu) +{ + struct device *dev = &pdev->dev; + int ret; + + pmu->irq = platform_get_irq(pdev, 0); + if (pmu->irq < 0) + return pmu->irq; + + ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, + 0, pdev->name, pmu); + if (ret) + dev_err(dev, "failed to request irq\n"); + + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -274,19 +310,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) if (IS_ERR(pmu->base)) return PTR_ERR(pmu->base); - pmu->irq = platform_get_irq(pdev, 0); - if (pmu->irq < 0) - return pmu->irq; - - ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, - 0, pdev->name, pmu); - if (ret) - dev_err(dev, "failed to request irq\n"); + spin_lock_init(&pmu->lock); match_data = of_device_get_match_data(dev); if (!match_data) return -EINVAL; + ret = match_data->pmu_parse_irq(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse irq\n"); + return ret; + } + pmu->genpd = devm_kcalloc(dev, match_data->num_domains, sizeof(struct generic_pm_domain *), GFP_KERNEL); @@ -306,9 +341,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) } } - spin_lock_init(&pmu->lock); - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); - ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data); if (ret) { dev_err(dev, "failed to register genpd driver: %d\n", ret); @@ -356,6 +388,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = { static const struct jh71xx_pmu_match_data jh7110_pmu = { .num_domains = ARRAY_SIZE(jh7110_power_domains), .domain_info = jh7110_power_domains, + .pmu_status = JH71XX_PMU_CURR_POWER_MODE, + .pmu_parse_irq = jh7110_pmu_parse_irq, + .pmu_set_state = jh7110_pmu_set_state, }; static const struct of_device_id jh71xx_pmu_of_match[] = { From ae3a94e4adee4429f364a0761233a928c865f3f8 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Wed, 13 Sep 2023 14:54:28 +0100 Subject: [PATCH 10/56] pmdomain: starfive: Add JH7110 AON PMU support Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the dphy rx/tx power switch. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230913-dude-imprecise-fc32622bc947@spud Signed-off-by: Ulf Hansson --- MAINTAINERS | 1 + drivers/pmdomain/starfive/jh71xx-pmu.c | 57 +++++++++++++++++++++++--- 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4d9e7d42412f0..f1c34484c9b23 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20512,6 +20512,7 @@ F: drivers/usb/cdns3/cdns3-starfive.c STARFIVE JH71XX PMU CONTROLLER DRIVER M: Walker Chen +M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/power/starfive* F: drivers/pmdomain/starfive/jh71xx-pmu.c diff --git a/drivers/pmdomain/starfive/jh71xx-pmu.c b/drivers/pmdomain/starfive/jh71xx-pmu.c index 547cd3b9df114..2724bee7e85f2 100644 --- a/drivers/pmdomain/starfive/jh71xx-pmu.c +++ b/drivers/pmdomain/starfive/jh71xx-pmu.c @@ -2,7 +2,7 @@ /* * StarFive JH71XX PMU (Power Management Unit) Controller Driver * - * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. */ #include @@ -23,6 +23,9 @@ #define JH71XX_PMU_EVENT_STATUS 0x88 #define JH71XX_PMU_INT_STATUS 0x8C +/* aon pmu register offset */ +#define JH71XX_AON_PMU_SWITCH 0x00 + /* sw encourage cfg */ #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 @@ -159,6 +162,26 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) return 0; } +static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +{ + struct jh71xx_pmu *pmu = pmd->pmu; + unsigned long flags; + u32 val; + + spin_lock_irqsave(&pmu->lock, flags); + val = readl(pmu->base + JH71XX_AON_PMU_SWITCH); + + if (on) + val |= mask; + else + val &= ~mask; + + writel(val, pmu->base + JH71XX_AON_PMU_SWITCH); + spin_unlock_irqrestore(&pmu->lock, flags); + + return 0; +} + static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) { struct jh71xx_pmu *pmu = pmd->pmu; @@ -316,10 +339,12 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) if (!match_data) return -EINVAL; - ret = match_data->pmu_parse_irq(pdev, pmu); - if (ret) { - dev_err(dev, "failed to parse irq\n"); - return ret; + if (match_data->pmu_parse_irq) { + ret = match_data->pmu_parse_irq(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse irq\n"); + return ret; + } } pmu->genpd = devm_kcalloc(dev, match_data->num_domains, @@ -393,10 +418,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = { .pmu_set_state = jh7110_pmu_set_state, }; +static const struct jh71xx_domain_info jh7110_aon_power_domains[] = { + [JH7110_PD_DPHY_TX] = { + .name = "DPHY-TX", + .bit = 30, + }, + [JH7110_PD_DPHY_RX] = { + .name = "DPHY-RX", + .bit = 31, + }, +}; + +static const struct jh71xx_pmu_match_data jh7110_aon_pmu = { + .num_domains = ARRAY_SIZE(jh7110_aon_power_domains), + .domain_info = jh7110_aon_power_domains, + .pmu_status = JH71XX_AON_PMU_SWITCH, + .pmu_set_state = jh7110_aon_pmu_set_state, +}; + static const struct of_device_id jh71xx_pmu_of_match[] = { { .compatible = "starfive,jh7110-pmu", .data = (void *)&jh7110_pmu, + }, { + .compatible = "starfive,jh7110-aon-syscon", + .data = (void *)&jh7110_aon_pmu, }, { /* sentinel */ } @@ -413,5 +459,6 @@ static struct platform_driver jh71xx_pmu_driver = { builtin_platform_driver(jh71xx_pmu_driver); MODULE_AUTHOR("Walker Chen "); +MODULE_AUTHOR("Changhuang Liang "); MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); MODULE_LICENSE("GPL"); From d149718ea22c8e53a7a7dd6ac8034ee9be7784ce Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Mon, 11 Sep 2023 17:22:15 +0200 Subject: [PATCH 11/56] pmdomain: Prepare to move Kconfig files into the pmdomain subsystem Rather than having the various Kconfig files for the genpd providers sprinkled across subsystems, let's prepare to move them into the pmdomain subsystem along with the implementations. Reviewed-by: Geert Uytterhoeven Signed-off-by: Ulf Hansson --- drivers/Kconfig | 2 ++ drivers/pmdomain/Kconfig | 4 ++++ 2 files changed, 6 insertions(+) create mode 100644 drivers/pmdomain/Kconfig diff --git a/drivers/Kconfig b/drivers/Kconfig index efb66e25fa2dd..3aebffb2efe9b 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -175,6 +175,8 @@ source "drivers/soundwire/Kconfig" source "drivers/soc/Kconfig" +source "drivers/pmdomain/Kconfig" + source "drivers/devfreq/Kconfig" source "drivers/extcon/Kconfig" diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig new file mode 100644 index 0000000000000..ac77cf4271a70 --- /dev/null +++ b/drivers/pmdomain/Kconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "PM Domains" + +endmenu From 4db570466cddfdf3ccbbc6d180d059551ff93e68 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Mon, 11 Sep 2023 17:32:31 +0200 Subject: [PATCH 12/56] pmdomain: actions: Move Kconfig file to the pmdomain subsystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: "Andreas Färber" Cc: Manivannan Sadhasivam Cc: Signed-off-by: Ulf Hansson --- MAINTAINERS | 2 +- drivers/pmdomain/Kconfig | 2 ++ drivers/{soc => pmdomain}/actions/Kconfig | 0 drivers/soc/Kconfig | 1 - 4 files changed, 3 insertions(+), 2 deletions(-) rename drivers/{soc => pmdomain}/actions/Kconfig (100%) diff --git a/MAINTAINERS b/MAINTAINERS index f1c34484c9b23..6b491ebcf790d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1788,7 +1788,7 @@ F: drivers/irqchip/irq-owl-sirq.c F: drivers/mmc/host/owl-mmc.c F: drivers/net/ethernet/actions/ F: drivers/pinctrl/actions/* -F: drivers/soc/actions/ +F: drivers/pmdomain/actions/ F: include/dt-bindings/power/owl-* F: include/dt-bindings/reset/actions,* F: include/linux/soc/actions/ diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index ac77cf4271a70..e410c4b8071a6 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "PM Domains" +source "drivers/pmdomain/actions/Kconfig" + endmenu diff --git a/drivers/soc/actions/Kconfig b/drivers/pmdomain/actions/Kconfig similarity index 100% rename from drivers/soc/actions/Kconfig rename to drivers/pmdomain/actions/Kconfig diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d21e75d692943..8b46da40f1074 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "SOC (System On Chip) specific Drivers" -source "drivers/soc/actions/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" From 2dfb28355dd352dcee0053095f3faa7cebe3151e Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Mon, 11 Sep 2023 23:38:08 +0200 Subject: [PATCH 13/56] pmdomain: amlogic: Move Kconfig options to the pmdomain subsystem The Kconfig options belongs closer to the corresponding implementations, hence let's move them from the soc subsystem to the pmdomain subsystem. Cc: Neil Armstrong Cc: Kevin Hilman Cc: Jerome Brunet Cc: Martin Blumenstingl Cc: Acked-by: Neil Armstrong Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/amlogic/Kconfig | 39 ++++++++++++++++++++++++++++++++ drivers/soc/amlogic/Kconfig | 35 ---------------------------- 3 files changed, 40 insertions(+), 35 deletions(-) create mode 100644 drivers/pmdomain/amlogic/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index e410c4b8071a6..03c8991ad0fd6 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -2,5 +2,6 @@ menu "PM Domains" source "drivers/pmdomain/actions/Kconfig" +source "drivers/pmdomain/amlogic/Kconfig" endmenu diff --git a/drivers/pmdomain/amlogic/Kconfig b/drivers/pmdomain/amlogic/Kconfig new file mode 100644 index 0000000000000..2108729909b5f --- /dev/null +++ b/drivers/pmdomain/amlogic/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "Amlogic PM Domains" + +config MESON_GX_PM_DOMAINS + tristate "Amlogic Meson GX Power Domains driver" + depends on ARCH_MESON || COMPILE_TEST + depends on PM && OF + default ARCH_MESON + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + Say yes to expose Amlogic Meson GX Power Domains as + Generic Power Domains. + +config MESON_EE_PM_DOMAINS + tristate "Amlogic Meson Everything-Else Power Domains driver" + depends on ARCH_MESON || COMPILE_TEST + depends on PM && OF + default ARCH_MESON + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + Say yes to expose Amlogic Meson Everything-Else Power Domains as + Generic Power Domains. + +config MESON_SECURE_PM_DOMAINS + tristate "Amlogic Meson Secure Power Domains driver" + depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM + depends on PM && OF + depends on HAVE_ARM_SMCCC + default ARCH_MESON + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + Support for the power controller on Amlogic A1/C1 series. + Say yes to expose Amlogic Meson Secure Power Domains as Generic + Power Domains. + +endmenu diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index 174a9b0114612..d08e398bdad48 100644 --- a/drivers/soc/amlogic/Kconfig +++ b/drivers/soc/amlogic/Kconfig @@ -26,41 +26,6 @@ config MESON_GX_SOCINFO Say yes to support decoding of Amlogic Meson GX SoC family information about the type, package and version. -config MESON_GX_PM_DOMAINS - tristate "Amlogic Meson GX Power Domains driver" - depends on ARCH_MESON || COMPILE_TEST - depends on PM && OF - default ARCH_MESON - select PM_GENERIC_DOMAINS - select PM_GENERIC_DOMAINS_OF - help - Say yes to expose Amlogic Meson GX Power Domains as - Generic Power Domains. - -config MESON_EE_PM_DOMAINS - tristate "Amlogic Meson Everything-Else Power Domains driver" - depends on ARCH_MESON || COMPILE_TEST - depends on PM && OF - default ARCH_MESON - select PM_GENERIC_DOMAINS - select PM_GENERIC_DOMAINS_OF - help - Say yes to expose Amlogic Meson Everything-Else Power Domains as - Generic Power Domains. - -config MESON_SECURE_PM_DOMAINS - tristate "Amlogic Meson Secure Power Domains driver" - depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM - depends on PM && OF - depends on HAVE_ARM_SMCCC - default ARCH_MESON - select PM_GENERIC_DOMAINS - select PM_GENERIC_DOMAINS_OF - help - Support for the power controller on Amlogic A1/C1 series. - Say yes to expose Amlogic Meson Secure Power Domains as Generic - Power Domains. - config MESON_MX_SOCINFO bool "Amlogic Meson MX SoC Information driver" depends on (ARM && ARCH_MESON) || COMPILE_TEST From 1bfadf2edd653af321af17e1cfac4fb28c3f790d Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 00:13:37 +0200 Subject: [PATCH 14/56] pmdomain: apple: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Hector Martin Cc: Sven Peter Cc: Alyssa Rosenzweig Cc: Reviewed-by: Eric Curtin Reviewed-by: Neal Gompa Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/apple/Kconfig | 18 ++++++++++++++++++ drivers/soc/apple/Kconfig | 13 ------------- 3 files changed, 19 insertions(+), 13 deletions(-) create mode 100644 drivers/pmdomain/apple/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 03c8991ad0fd6..482d9e970e147 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -3,5 +3,6 @@ menu "PM Domains" source "drivers/pmdomain/actions/Kconfig" source "drivers/pmdomain/amlogic/Kconfig" +source "drivers/pmdomain/apple/Kconfig" endmenu diff --git a/drivers/pmdomain/apple/Kconfig b/drivers/pmdomain/apple/Kconfig new file mode 100644 index 0000000000000..12237cbcfaa98 --- /dev/null +++ b/drivers/pmdomain/apple/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_APPLE || COMPILE_TEST + +config APPLE_PMGR_PWRSTATE + bool "Apple SoC PMGR power state control" + depends on PM + select REGMAP + select MFD_SYSCON + select PM_GENERIC_DOMAINS + select RESET_CONTROLLER + default ARCH_APPLE + help + The PMGR block in Apple SoCs provides high-level power state + controls for SoC devices. This driver manages them through the + generic power domain framework, and also provides reset support. + +endif diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig index a1596fefacffe..eff486a773377 100644 --- a/drivers/soc/apple/Kconfig +++ b/drivers/soc/apple/Kconfig @@ -4,19 +4,6 @@ if ARCH_APPLE || COMPILE_TEST menu "Apple SoC drivers" -config APPLE_PMGR_PWRSTATE - bool "Apple SoC PMGR power state control" - depends on PM - select REGMAP - select MFD_SYSCON - select PM_GENERIC_DOMAINS - select RESET_CONTROLLER - default ARCH_APPLE - help - The PMGR block in Apple SoCs provides high-level power state - controls for SoC devices. This driver manages them through the - generic power domain framework, and also provides reset support. - config APPLE_RTKIT tristate "Apple RTKit co-processor IPC protocol" depends on MAILBOX From c067e7ffb31f270163b9f11da83a86ab660ee783 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 00:25:50 +0200 Subject: [PATCH 15/56] pmdomain: bcm: Move Kconfig options to the pmdomain subsystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kconfig options belongs closer to the corresponding implementations, hence let's move them from the soc subsystem to the pmdomain subsystem. Cc: Florian Fainelli Cc: Ray Jui Cc: Scott Branden Cc: Cc: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/bcm/Kconfig | 42 +++++++++++++++++++++++++++++ drivers/soc/bcm/Kconfig | 51 ------------------------------------ 3 files changed, 43 insertions(+), 51 deletions(-) create mode 100644 drivers/pmdomain/bcm/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 482d9e970e147..ddc05d6af1003 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -4,5 +4,6 @@ menu "PM Domains" source "drivers/pmdomain/actions/Kconfig" source "drivers/pmdomain/amlogic/Kconfig" source "drivers/pmdomain/apple/Kconfig" +source "drivers/pmdomain/bcm/Kconfig" endmenu diff --git a/drivers/pmdomain/bcm/Kconfig b/drivers/pmdomain/bcm/Kconfig new file mode 100644 index 0000000000000..b28c9f6d256b3 --- /dev/null +++ b/drivers/pmdomain/bcm/Kconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "Broadcom PM Domains" + +config BCM2835_POWER + bool "BCM2835 power domain driver" + depends on ARCH_BCM2835 || (COMPILE_TEST && OF) + default y if ARCH_BCM2835 + select PM_GENERIC_DOMAINS if PM + select RESET_CONTROLLER + help + This enables support for the BCM2835 power domains and reset + controller. Any usage of power domains by the Raspberry Pi + firmware means that Linux usage of the same power domain + must be accessed using the RASPBERRYPI_POWER driver + +config RASPBERRYPI_POWER + bool "Raspberry Pi power domain driver" + depends on ARCH_BCM2835 || (COMPILE_TEST && OF) + depends on RASPBERRYPI_FIRMWARE=y + select PM_GENERIC_DOMAINS if PM + help + This enables support for the RPi power domains which can be enabled + or disabled via the RPi firmware. + +config BCM_PMB + bool "Broadcom PMB (Power Management Bus) driver" + depends on ARCH_BCMBCA || (COMPILE_TEST && OF) + default ARCH_BCMBCA + select PM_GENERIC_DOMAINS if PM + help + This enables support for the Broadcom's PMB (Power Management Bus) that + is used for disabling and enabling SoC devices. + +config BCM63XX_POWER + bool "BCM63xx power domain driver" + depends on BMIPS_GENERIC || (COMPILE_TEST && OF) + select PM_GENERIC_DOMAINS if PM + help + This enables support for the BCM63xx power domains controller on + BCM6318, BCM6328, BCM6362 and BCM63268 SoCs. + +endmenu diff --git a/drivers/soc/bcm/Kconfig b/drivers/soc/bcm/Kconfig index f96906795fa6d..1f5577cfd68c6 100644 --- a/drivers/soc/bcm/Kconfig +++ b/drivers/soc/bcm/Kconfig @@ -1,36 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "Broadcom SoC drivers" -config BCM2835_POWER - bool "BCM2835 power domain driver" - depends on ARCH_BCM2835 || (COMPILE_TEST && OF) - default y if ARCH_BCM2835 - select PM_GENERIC_DOMAINS if PM - select RESET_CONTROLLER - help - This enables support for the BCM2835 power domains and reset - controller. Any usage of power domains by the Raspberry Pi - firmware means that Linux usage of the same power domain - must be accessed using the RASPBERRYPI_POWER driver - -config RASPBERRYPI_POWER - bool "Raspberry Pi power domain driver" - depends on ARCH_BCM2835 || (COMPILE_TEST && OF) - depends on RASPBERRYPI_FIRMWARE=y - select PM_GENERIC_DOMAINS if PM - help - This enables support for the RPi power domains which can be enabled - or disabled via the RPi firmware. - -config SOC_BCM63XX - bool "Broadcom 63xx SoC drivers" - depends on BMIPS_GENERIC || COMPILE_TEST - help - Enables drivers for the Broadcom 63xx series of chips. - Drivers can be enabled individually within this menu. - - If unsure, say N. - config SOC_BRCMSTB bool "Broadcom STB SoC drivers" depends on ARM || ARM64 || BMIPS_GENERIC || COMPILE_TEST @@ -42,27 +12,6 @@ config SOC_BRCMSTB If unsure, say N. -config BCM_PMB - bool "Broadcom PMB (Power Management Bus) driver" - depends on ARCH_BCMBCA || (COMPILE_TEST && OF) - default ARCH_BCMBCA - select PM_GENERIC_DOMAINS if PM - help - This enables support for the Broadcom's PMB (Power Management Bus) that - is used for disabling and enabling SoC devices. - -if SOC_BCM63XX - -config BCM63XX_POWER - bool "BCM63xx power domain driver" - depends on BMIPS_GENERIC || (COMPILE_TEST && OF) - select PM_GENERIC_DOMAINS if PM - help - This enables support for the BCM63xx power domains controller on - BCM6318, BCM6328, BCM6362 and BCM63268 SoCs. - -endif # SOC_BCM63XX - source "drivers/soc/bcm/brcmstb/Kconfig" endmenu From 0cd3f86ad558d3f585634e211c6fccbe786cbc28 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sat, 16 Sep 2023 20:59:51 +0300 Subject: [PATCH 16/56] dt-bindings: power: qcom,rpmpd: Add SM7150 Add a compatible for SM7150 platforms. Signed-off-by: Danila Tikhonov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230916175952.178611-2-danila@jiaxyga.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 9b03c41d3604e..53886f02d98a9 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -46,6 +46,7 @@ properties: - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd - qcom,sm6375-rpmpd + - qcom,sm7150-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd From 24a11a1e82456d865c4ab18f01456ef5e0f9dda0 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 00:45:34 +0200 Subject: [PATCH 17/56] pmdomain: imx: Move Kconfig options to the pmdomain subsystem The Kconfig options belongs closer to the corresponding implementations, hence let's move them from the soc- and firmware subsystem to the pmdomain subsystem. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Peng Fan Cc: Cc: Acked-by: Peng Fan Acked-by: Shawn Guo Signed-off-by: Ulf Hansson --- drivers/firmware/imx/Kconfig | 6 ------ drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/imx/Kconfig | 29 +++++++++++++++++++++++++++++ drivers/soc/imx/Kconfig | 19 ------------------- 4 files changed, 30 insertions(+), 25 deletions(-) create mode 100644 drivers/pmdomain/imx/Kconfig diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig index c027d99f2a599..183613f82a110 100644 --- a/drivers/firmware/imx/Kconfig +++ b/drivers/firmware/imx/Kconfig @@ -22,9 +22,3 @@ config IMX_SCU This driver manages the IPC interface between host CPU and the SCU firmware running on M4. - -config IMX_SCU_PD - bool "IMX SCU Power Domain driver" - depends on IMX_SCU - help - The System Controller Firmware (SCFW) based power domain driver. diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index ddc05d6af1003..e2c85f20a0c3a 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -5,5 +5,6 @@ source "drivers/pmdomain/actions/Kconfig" source "drivers/pmdomain/amlogic/Kconfig" source "drivers/pmdomain/apple/Kconfig" source "drivers/pmdomain/bcm/Kconfig" +source "drivers/pmdomain/imx/Kconfig" endmenu diff --git a/drivers/pmdomain/imx/Kconfig b/drivers/pmdomain/imx/Kconfig new file mode 100644 index 0000000000000..00203615c65e9 --- /dev/null +++ b/drivers/pmdomain/imx/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "i.MX PM Domains" + +config IMX_GPCV2_PM_DOMAINS + bool "i.MX GPCv2 PM domains" + depends on ARCH_MXC || (COMPILE_TEST && OF) + depends on PM + select PM_GENERIC_DOMAINS + select REGMAP_MMIO + default y if SOC_IMX7D + +config IMX8M_BLK_CTRL + bool + default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS + depends on PM_GENERIC_DOMAINS + depends on COMMON_CLK + +config IMX9_BLK_CTRL + bool + default SOC_IMX9 && IMX_GPCV2_PM_DOMAINS + depends on PM_GENERIC_DOMAINS + +config IMX_SCU_PD + bool "IMX SCU Power Domain driver" + depends on IMX_SCU + help + The System Controller Firmware (SCFW) based power domain driver. + +endmenu diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index 76a4593baf0a2..2a90ddd201040 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -1,14 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "i.MX SoC drivers" -config IMX_GPCV2_PM_DOMAINS - bool "i.MX GPCv2 PM domains" - depends on ARCH_MXC || (COMPILE_TEST && OF) - depends on PM - select PM_GENERIC_DOMAINS - select REGMAP_MMIO - default y if SOC_IMX7D - config SOC_IMX8M tristate "i.MX8M SoC family support" depends on ARCH_MXC || COMPILE_TEST @@ -28,15 +20,4 @@ config SOC_IMX9 help If you say yes here, you get support for the NXP i.MX9 family -config IMX8M_BLK_CTRL - bool - default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS - depends on PM_GENERIC_DOMAINS - depends on COMMON_CLK - -config IMX9_BLK_CTRL - bool - default SOC_IMX9 && IMX_GPCV2_PM_DOMAINS - depends on PM_GENERIC_DOMAINS - endmenu From 8b1d7a2785ab2d4153abd7bf77e53b8e5fa49869 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 00:52:25 +0200 Subject: [PATCH 18/56] pmdomain: mediatek: Move Kconfig options to the pmdomain subsystem The Kconfig options belongs closer to the corresponding implementations, hence let's move them from the soc subsystem to the pmdomain subsystem. Cc: Matthias Brugger Cc: AngeloGioacchino Del Regno Cc: Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/mediatek/Kconfig | 29 +++++++++++++++++++++++++++++ drivers/soc/mediatek/Kconfig | 23 ----------------------- 3 files changed, 30 insertions(+), 23 deletions(-) create mode 100644 drivers/pmdomain/mediatek/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index e2c85f20a0c3a..b1d9dc7d71e30 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -6,5 +6,6 @@ source "drivers/pmdomain/amlogic/Kconfig" source "drivers/pmdomain/apple/Kconfig" source "drivers/pmdomain/bcm/Kconfig" source "drivers/pmdomain/imx/Kconfig" +source "drivers/pmdomain/mediatek/Kconfig" endmenu diff --git a/drivers/pmdomain/mediatek/Kconfig b/drivers/pmdomain/mediatek/Kconfig new file mode 100644 index 0000000000000..21305c4f17fea --- /dev/null +++ b/drivers/pmdomain/mediatek/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menu "MediaTek PM Domains" + depends on ARCH_MEDIATEK || COMPILE_TEST + +config MTK_SCPSYS + bool "MediaTek SCPSYS Support" + default ARCH_MEDIATEK + depends on OF + select REGMAP + select MTK_INFRACFG + select PM_GENERIC_DOMAINS if PM + help + Say yes here to add support for the MediaTek SCPSYS power domain + driver. + +config MTK_SCPSYS_PM_DOMAINS + bool "MediaTek SCPSYS generic power domain" + default ARCH_MEDIATEK + depends on PM + select PM_GENERIC_DOMAINS + select REGMAP + help + Say y here to enable power domain support. + In order to meet high performance and low power requirements, the System + Control Processor System (SCPSYS) has several power management related + tasks in the system. + +endmenu diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index a88cf04fc803d..0810b5b0c6883 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -49,29 +49,6 @@ config MTK_REGULATOR_COUPLER default ARCH_MEDIATEK depends on REGULATOR -config MTK_SCPSYS - bool "MediaTek SCPSYS Support" - default ARCH_MEDIATEK - depends on OF - select REGMAP - select MTK_INFRACFG - select PM_GENERIC_DOMAINS if PM - help - Say yes here to add support for the MediaTek SCPSYS power domain - driver. - -config MTK_SCPSYS_PM_DOMAINS - bool "MediaTek SCPSYS generic power domain" - default ARCH_MEDIATEK - depends on PM - select PM_GENERIC_DOMAINS - select REGMAP - help - Say y here to enable power domain support. - In order to meet high performance and low power requirements, the System - Control Processor System (SCPSYS) has several power management related - tasks in the system. - config MTK_MMSYS tristate "MediaTek MMSYS Support" default ARCH_MEDIATEK From 4eb42e5bd86da528be604845f52732742ef74e6b Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 11:39:24 +0200 Subject: [PATCH 19/56] pmdomain: qcom: Move Kconfig options to the pmdomain subsystem The Kconfig options belongs closer to the corresponding implementations, hence let's move them from the soc subsystem to the pmdomain subsystem. Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: Andy Gross Cc: Acked-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/qcom/Kconfig | 41 +++++++++++++++++++++++++++++++++++ drivers/soc/qcom/Kconfig | 37 ------------------------------- 3 files changed, 42 insertions(+), 37 deletions(-) create mode 100644 drivers/pmdomain/qcom/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index b1d9dc7d71e30..c91fdd40163a6 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -7,5 +7,6 @@ source "drivers/pmdomain/apple/Kconfig" source "drivers/pmdomain/bcm/Kconfig" source "drivers/pmdomain/imx/Kconfig" source "drivers/pmdomain/mediatek/Kconfig" +source "drivers/pmdomain/qcom/Kconfig" endmenu diff --git a/drivers/pmdomain/qcom/Kconfig b/drivers/pmdomain/qcom/Kconfig new file mode 100644 index 0000000000000..3d3948eabef0f --- /dev/null +++ b/drivers/pmdomain/qcom/Kconfig @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "Qualcomm PM Domains" + +config QCOM_CPR + tristate "QCOM Core Power Reduction (CPR) support" + depends on ARCH_QCOM && HAS_IOMEM + select PM_OPP + select REGMAP + help + Say Y here to enable support for the CPR hardware found on Qualcomm + SoCs like QCS404. + + This driver populates CPU OPPs tables and makes adjustments to the + tables based on feedback from the CPR hardware. If you want to do + CPUfrequency scaling say Y here. + + To compile this driver as a module, choose M here: the module will + be called qcom-cpr + +config QCOM_RPMHPD + tristate "Qualcomm RPMh Power domain driver" + depends on QCOM_RPMH && QCOM_COMMAND_DB + help + QCOM RPMh Power domain driver to support power-domains with + performance states. The driver communicates a performance state + value to RPMh which then translates it into corresponding voltage + for the voltage rail. + +config QCOM_RPMPD + tristate "Qualcomm RPM Power domain driver" + depends on PM && OF + depends on QCOM_SMD_RPM + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + QCOM RPM Power domain driver to support power-domains with + performance states. The driver communicates a performance state + value to RPM which then translates it into corresponding voltage + for the voltage rail. + +endmenu diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 715348869d048..b3634e10f6f5e 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -26,22 +26,6 @@ config QCOM_COMMAND_DB resource on a RPM-hardened platform must use this database to get SoC specific identifier and information for the shared resources. -config QCOM_CPR - tristate "QCOM Core Power Reduction (CPR) support" - depends on ARCH_QCOM && HAS_IOMEM - select PM_OPP - select REGMAP - help - Say Y here to enable support for the CPR hardware found on Qualcomm - SoCs like QCS404. - - This driver populates CPU OPPs tables and makes adjustments to the - tables based on feedback from the CPR hardware. If you want to do - CPUfrequency scaling say Y here. - - To compile this driver as a module, choose M here: the module will - be called qcom-cpr - config QCOM_GENI_SE tristate "QCOM GENI Serial Engine Driver" depends on ARCH_QCOM || COMPILE_TEST @@ -157,27 +141,6 @@ config QCOM_RPMH of hardware components aggregate requests for these resources and help apply the aggregated state on the resource. -config QCOM_RPMHPD - tristate "Qualcomm RPMh Power domain driver" - depends on QCOM_RPMH && QCOM_COMMAND_DB - help - QCOM RPMh Power domain driver to support power-domains with - performance states. The driver communicates a performance state - value to RPMh which then translates it into corresponding voltage - for the voltage rail. - -config QCOM_RPMPD - tristate "Qualcomm RPM Power domain driver" - depends on PM && OF - depends on QCOM_SMD_RPM - select PM_GENERIC_DOMAINS - select PM_GENERIC_DOMAINS_OF - help - QCOM RPM Power domain driver to support power-domains with - performance states. The driver communicates a performance state - value to RPM which then translates it into corresponding voltage - for the voltage rail. - config QCOM_SMEM tristate "Qualcomm Shared Memory Manager (SMEM)" depends on ARCH_QCOM || COMPILE_TEST From a3aa70f9727431a1fef70f9f9cbc4765599c0cc2 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 12:27:58 +0200 Subject: [PATCH 20/56] pmdomain: renesas: Move Kconfig options to the pmdomain subsystem The Kconfig options belongs closer to the corresponding implementations, hence let's move them from the soc subsystem to the pmdomain subsystem. Cc: Geert Uytterhoeven Cc: Magnus Damm Cc: Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/renesas/Kconfig | 109 +++++++++++++++++++++++++++++++ drivers/soc/renesas/Kconfig | 105 ----------------------------- 3 files changed, 110 insertions(+), 105 deletions(-) create mode 100644 drivers/pmdomain/renesas/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index c91fdd40163a6..0a75a17f2f3a9 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -8,5 +8,6 @@ source "drivers/pmdomain/bcm/Kconfig" source "drivers/pmdomain/imx/Kconfig" source "drivers/pmdomain/mediatek/Kconfig" source "drivers/pmdomain/qcom/Kconfig" +source "drivers/pmdomain/renesas/Kconfig" endmenu diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kconfig new file mode 100644 index 0000000000000..80bf2cf8b60e6 --- /dev/null +++ b/drivers/pmdomain/renesas/Kconfig @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0 +if SOC_RENESAS + +config SYSC_RCAR + bool "System Controller support for R-Car" if COMPILE_TEST + +config SYSC_RCAR_GEN4 + bool "System Controller support for R-Car Gen4" if COMPILE_TEST + +config SYSC_R8A77995 + bool "System Controller support for R-Car D3" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7794 + bool "System Controller support for R-Car E2" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A77990 + bool "System Controller support for R-Car E3" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7779 + bool "System Controller support for R-Car H1" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7790 + bool "System Controller support for R-Car H2" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7795 + bool "System Controller support for R-Car H3" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7791 + bool "System Controller support for R-Car M2-W/N" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A77965 + bool "System Controller support for R-Car M3-N" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A77960 + bool "System Controller support for R-Car M3-W" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A77961 + bool "System Controller support for R-Car M3-W+" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A779F0 + bool "System Controller support for R-Car S4-8" if COMPILE_TEST + select SYSC_RCAR_GEN4 + +config SYSC_R8A7792 + bool "System Controller support for R-Car V2H" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A77980 + bool "System Controller support for R-Car V3H" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A77970 + bool "System Controller support for R-Car V3M" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A779A0 + bool "System Controller support for R-Car V3U" if COMPILE_TEST + select SYSC_RCAR_GEN4 + +config SYSC_R8A779G0 + bool "System Controller support for R-Car V4H" if COMPILE_TEST + select SYSC_RCAR_GEN4 + +config SYSC_RMOBILE + bool "System Controller support for R-Mobile" if COMPILE_TEST + +config SYSC_R8A77470 + bool "System Controller support for RZ/G1C" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7745 + bool "System Controller support for RZ/G1E" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7742 + bool "System Controller support for RZ/G1H" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A7743 + bool "System Controller support for RZ/G1M" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A774C0 + bool "System Controller support for RZ/G2E" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A774E1 + bool "System Controller support for RZ/G2H" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A774A1 + bool "System Controller support for RZ/G2M" if COMPILE_TEST + select SYSC_RCAR + +config SYSC_R8A774B1 + bool "System Controller support for RZ/G2N" if COMPILE_TEST + select SYSC_RCAR + +endif diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 5a75ab64d1ed3..650f4dd96decc 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -350,109 +350,4 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST -config SYSC_RCAR - bool "System Controller support for R-Car" if COMPILE_TEST - -config SYSC_RCAR_GEN4 - bool "System Controller support for R-Car Gen4" if COMPILE_TEST - -config SYSC_R8A77995 - bool "System Controller support for R-Car D3" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7794 - bool "System Controller support for R-Car E2" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A77990 - bool "System Controller support for R-Car E3" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7779 - bool "System Controller support for R-Car H1" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7790 - bool "System Controller support for R-Car H2" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7795 - bool "System Controller support for R-Car H3" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7791 - bool "System Controller support for R-Car M2-W/N" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A77965 - bool "System Controller support for R-Car M3-N" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A77960 - bool "System Controller support for R-Car M3-W" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A77961 - bool "System Controller support for R-Car M3-W+" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A779F0 - bool "System Controller support for R-Car S4-8" if COMPILE_TEST - select SYSC_RCAR_GEN4 - -config SYSC_R8A7792 - bool "System Controller support for R-Car V2H" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A77980 - bool "System Controller support for R-Car V3H" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A77970 - bool "System Controller support for R-Car V3M" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A779A0 - bool "System Controller support for R-Car V3U" if COMPILE_TEST - select SYSC_RCAR_GEN4 - -config SYSC_R8A779G0 - bool "System Controller support for R-Car V4H" if COMPILE_TEST - select SYSC_RCAR_GEN4 - -config SYSC_RMOBILE - bool "System Controller support for R-Mobile" if COMPILE_TEST - -config SYSC_R8A77470 - bool "System Controller support for RZ/G1C" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7745 - bool "System Controller support for RZ/G1E" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7742 - bool "System Controller support for RZ/G1H" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A7743 - bool "System Controller support for RZ/G1M" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A774C0 - bool "System Controller support for RZ/G2E" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A774E1 - bool "System Controller support for RZ/G2H" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A774A1 - bool "System Controller support for RZ/G2M" if COMPILE_TEST - select SYSC_RCAR - -config SYSC_R8A774B1 - bool "System Controller support for RZ/G2N" if COMPILE_TEST - select SYSC_RCAR - endif # SOC_RENESAS From 70a69266b3925f7d0e9c3906d15d4ca3431aa519 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 12:39:02 +0200 Subject: [PATCH 21/56] pmdomain: rockchip: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Heiko Stuebner Cc: Acked-by: Heiko Stuebner Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/rockchip/Kconfig | 16 ++++++++++++++++ drivers/soc/rockchip/Kconfig | 12 ------------ 3 files changed, 17 insertions(+), 12 deletions(-) create mode 100644 drivers/pmdomain/rockchip/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 0a75a17f2f3a9..8afe69251dd22 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -9,5 +9,6 @@ source "drivers/pmdomain/imx/Kconfig" source "drivers/pmdomain/mediatek/Kconfig" source "drivers/pmdomain/qcom/Kconfig" source "drivers/pmdomain/renesas/Kconfig" +source "drivers/pmdomain/rockchip/Kconfig" endmenu diff --git a/drivers/pmdomain/rockchip/Kconfig b/drivers/pmdomain/rockchip/Kconfig new file mode 100644 index 0000000000000..b0d70f1a8439e --- /dev/null +++ b/drivers/pmdomain/rockchip/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +if ARCH_ROCKCHIP || COMPILE_TEST + +config ROCKCHIP_PM_DOMAINS + bool "Rockchip generic power domain" + depends on PM + select PM_GENERIC_DOMAINS + help + Say y here to enable power domain support. + In order to meet high performance and low power requirements, a power + management unit is designed or saving power when RK3288 in low power + mode. The RK3288 PMU is dedicated for managing the power of the whole chip. + + If unsure, say N. + +endif diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig index aff2f7e952374..785f60c6f3ad1 100644 --- a/drivers/soc/rockchip/Kconfig +++ b/drivers/soc/rockchip/Kconfig @@ -22,18 +22,6 @@ config ROCKCHIP_IODOMAIN necessary for the io domain setting of the SoC to match the voltage supplied by the regulators. -config ROCKCHIP_PM_DOMAINS - bool "Rockchip generic power domain" - depends on PM - select PM_GENERIC_DOMAINS - help - Say y here to enable power domain support. - In order to meet high performance and low power requirements, a power - management unit is designed or saving power when RK3288 in low power - mode. The RK3288 PMU is dedicated for managing the power of the whole chip. - - If unsure, say N. - config ROCKCHIP_DTPM tristate "Rockchip DTPM hierarchy" depends on DTPM && m From 70556c57eab404cc0241e991065b4cd532883e57 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 12:48:37 +0200 Subject: [PATCH 22/56] pmdomain: samsung: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Krzysztof Kozlowski Cc: Alim Akhtar Cc: Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/samsung/Kconfig | 8 ++++++++ drivers/soc/samsung/Kconfig | 4 ---- 3 files changed, 9 insertions(+), 4 deletions(-) create mode 100644 drivers/pmdomain/samsung/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 8afe69251dd22..4a411e0985c37 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -10,5 +10,6 @@ source "drivers/pmdomain/mediatek/Kconfig" source "drivers/pmdomain/qcom/Kconfig" source "drivers/pmdomain/renesas/Kconfig" source "drivers/pmdomain/rockchip/Kconfig" +source "drivers/pmdomain/samsung/Kconfig" endmenu diff --git a/drivers/pmdomain/samsung/Kconfig b/drivers/pmdomain/samsung/Kconfig new file mode 100644 index 0000000000000..0debfe36b00aa --- /dev/null +++ b/drivers/pmdomain/samsung/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +if SOC_SAMSUNG + +config EXYNOS_PM_DOMAINS + bool "Exynos PM domains" if COMPILE_TEST + depends on (ARCH_EXYNOS && PM_GENERIC_DOMAINS) || COMPILE_TEST + +endif diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index 7a8f291e7704c..27ec99af77e33 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -48,10 +48,6 @@ config EXYNOS_PMU_ARM_DRIVERS bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST depends on EXYNOS_PMU -config EXYNOS_PM_DOMAINS - bool "Exynos PM domains" if COMPILE_TEST - depends on (ARCH_EXYNOS && PM_GENERIC_DOMAINS) || COMPILE_TEST - config SAMSUNG_PM_CHECK bool "S3C2410 PM Suspend Memory CRC" depends on PM && (ARCH_S3C64XX || ARCH_S5PV210) From c6d6afb840108ae3920812dd66b25a65acfe447b Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 12:59:11 +0200 Subject: [PATCH 23/56] pmdomain: st: Add a Kconfig option for the ux500 power domain We shouldn't really use the CONFIG_ARCH_U8500 option directly, but rather have our own dedicated Kconfig option, so let's add that. Cc: Linus Walleij Reviewed-by: Linus Walleij Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/st/Kconfig | 5 +++++ drivers/pmdomain/st/Makefile | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) create mode 100644 drivers/pmdomain/st/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 4a411e0985c37..08f8a3aa98051 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -11,5 +11,6 @@ source "drivers/pmdomain/qcom/Kconfig" source "drivers/pmdomain/renesas/Kconfig" source "drivers/pmdomain/rockchip/Kconfig" source "drivers/pmdomain/samsung/Kconfig" +source "drivers/pmdomain/st/Kconfig" endmenu diff --git a/drivers/pmdomain/st/Kconfig b/drivers/pmdomain/st/Kconfig new file mode 100644 index 0000000000000..a77a70211f61b --- /dev/null +++ b/drivers/pmdomain/st/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +config UX500_PM_DOMAIN + bool "ST-Ericsson ux500 Power Domain" + depends on ARCH_U8500 || COMPILE_TEST + default ARCH_U8500 diff --git a/drivers/pmdomain/st/Makefile b/drivers/pmdomain/st/Makefile index 8fa5f98554608..6d8b617eb834c 100644 --- a/drivers/pmdomain/st/Makefile +++ b/drivers/pmdomain/st/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_ARCH_U8500) += ste-ux500-pm-domain.o +obj-$(CONFIG_UX500_PM_DOMAIN) += ste-ux500-pm-domain.o From ac68b50d15f12f3168f6cde8e59928ec86ba0f36 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 13:31:44 +0200 Subject: [PATCH 24/56] pmdomain: starfive: Move Kconfig file to the pmdomain subsystem The Kconfig belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Walker Chen Cc: Conor Dooley Acked-by: Conor Dooley Signed-off-by: Ulf Hansson --- MAINTAINERS | 3 +-- drivers/pmdomain/Kconfig | 1 + drivers/{soc => pmdomain}/starfive/Kconfig | 0 drivers/soc/Kconfig | 1 - 4 files changed, 2 insertions(+), 3 deletions(-) rename drivers/{soc => pmdomain}/starfive/Kconfig (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 6b491ebcf790d..40744fefed3d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20515,7 +20515,7 @@ M: Walker Chen M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/power/starfive* -F: drivers/pmdomain/starfive/jh71xx-pmu.c +F: drivers/pmdomain/starfive/ F: include/dt-bindings/power/starfive,jh7110-pmu.h STARFIVE SOC DRIVERS @@ -20523,7 +20523,6 @@ M: Conor Dooley S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/soc/starfive/ -F: drivers/soc/starfive/ STARFIVE TRNG DRIVER M: Jia Jie Ho diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 08f8a3aa98051..2286c36076db5 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -12,5 +12,6 @@ source "drivers/pmdomain/renesas/Kconfig" source "drivers/pmdomain/rockchip/Kconfig" source "drivers/pmdomain/samsung/Kconfig" source "drivers/pmdomain/st/Kconfig" +source "drivers/pmdomain/starfive/Kconfig" endmenu diff --git a/drivers/soc/starfive/Kconfig b/drivers/pmdomain/starfive/Kconfig similarity index 100% rename from drivers/soc/starfive/Kconfig rename to drivers/pmdomain/starfive/Kconfig diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 8b46da40f1074..10a9ff84ff41d 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -23,7 +23,6 @@ source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" source "drivers/soc/sifive/Kconfig" -source "drivers/soc/starfive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" From fe78050a002524f332d19bca8127de6fdbdad32b Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 14:09:39 +0200 Subject: [PATCH 25/56] pmdomain: sunxi: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Chen-Yu Tsai Cc: Jernej Skrabec Cc: Samuel Holland Cc: Acked-by: Jernej Skrabec Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/sunxi/Kconfig | 10 ++++++++++ drivers/soc/sunxi/Kconfig | 9 --------- 3 files changed, 11 insertions(+), 9 deletions(-) create mode 100644 drivers/pmdomain/sunxi/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 2286c36076db5..10c3bc2e24447 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -13,5 +13,6 @@ source "drivers/pmdomain/rockchip/Kconfig" source "drivers/pmdomain/samsung/Kconfig" source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" +source "drivers/pmdomain/sunxi/Kconfig" endmenu diff --git a/drivers/pmdomain/sunxi/Kconfig b/drivers/pmdomain/sunxi/Kconfig new file mode 100644 index 0000000000000..17781bf8d86d7 --- /dev/null +++ b/drivers/pmdomain/sunxi/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUN20I_PPU + bool "Allwinner D1 PPU power domain driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on PM + select PM_GENERIC_DOMAINS + help + Say y to enable the PPU power domain driver. This saves power + when certain peripherals, such as the video engine, are idle. diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig index c5070914fc6aa..8aecbc9b19763 100644 --- a/drivers/soc/sunxi/Kconfig +++ b/drivers/soc/sunxi/Kconfig @@ -19,12 +19,3 @@ config SUNXI_SRAM Say y here to enable the SRAM controller support. This device is responsible on mapping the SRAM in the sunXi SoCs whether to the CPU/DMA, or to the devices. - -config SUN20I_PPU - bool "Allwinner D1 PPU power domain driver" - depends on ARCH_SUNXI || COMPILE_TEST - depends on PM - select PM_GENERIC_DOMAINS - help - Say y to enable the PPU power domain driver. This saves power - when certain peripherals, such as the video engine, are idle. From f28cd697505d4d4d83fcb0d132d042551056ee13 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 14:16:49 +0200 Subject: [PATCH 26/56] pmdomain: tegra: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Thierry Reding Cc: Jonathan Hunter Cc: Mikko Perttunen Cc: Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/tegra/Kconfig | 6 ++++++ drivers/soc/tegra/Kconfig | 5 ----- 3 files changed, 7 insertions(+), 5 deletions(-) create mode 100644 drivers/pmdomain/tegra/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 10c3bc2e24447..98e04589bef4e 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -14,5 +14,6 @@ source "drivers/pmdomain/samsung/Kconfig" source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" +source "drivers/pmdomain/tegra/Kconfig" endmenu diff --git a/drivers/pmdomain/tegra/Kconfig b/drivers/pmdomain/tegra/Kconfig new file mode 100644 index 0000000000000..13ade6d84696d --- /dev/null +++ b/drivers/pmdomain/tegra/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOC_TEGRA_POWERGATE_BPMP + def_bool y + depends on PM_GENERIC_DOMAINS + depends on TEGRA_BPMP diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 6f30988229692..f16beeabaa92b 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -152,11 +152,6 @@ config SOC_TEGRA_PMC select PM_GENERIC_DOMAINS select REGMAP -config SOC_TEGRA_POWERGATE_BPMP - def_bool y - depends on PM_GENERIC_DOMAINS - depends on TEGRA_BPMP - config SOC_TEGRA20_VOLTAGE_COUPLER bool "Voltage scaling support for Tegra20 SoCs" depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST From 02c24a120374b8beb3078a40ce1e7fd326518fcf Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 15:35:25 +0200 Subject: [PATCH 27/56] pmdomain: ti: Move and add Kconfig options to the pmdomain subsystem The TI_SCI_PM_DOMAINS Kconfig option belongs closer to its corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. While at it, let's also add a Kconfig option the omap_prm driver, rather than using ARCH_OMAP2PLUS directly. Cc: Nishanth Menon Cc: Santosh Shilimkar Cc: Tero Kristo Cc: Tony Lindgren Reviewed-by: Dhruva Gole Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/ti/Kconfig | 22 ++++++++++++++++++++++ drivers/pmdomain/ti/Makefile | 2 +- drivers/soc/ti/Kconfig | 12 ------------ 4 files changed, 24 insertions(+), 13 deletions(-) create mode 100644 drivers/pmdomain/ti/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 98e04589bef4e..33bfec9c4f7a6 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -15,5 +15,6 @@ source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" source "drivers/pmdomain/tegra/Kconfig" +source "drivers/pmdomain/ti/Kconfig" endmenu diff --git a/drivers/pmdomain/ti/Kconfig b/drivers/pmdomain/ti/Kconfig new file mode 100644 index 0000000000000..67c608bf7ed02 --- /dev/null +++ b/drivers/pmdomain/ti/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config OMAP2PLUS_PRM + bool + depends on ARCH_OMAP2PLUS + default ARCH_OMAP2PLUS + +if SOC_TI + +config TI_SCI_PM_DOMAINS + tristate "TI SCI PM Domains Driver" + depends on TI_SCI_PROTOCOL + depends on PM_GENERIC_DOMAINS + help + Generic power domain implementation for TI device implementing + the TI SCI protocol. + + To compile this as a module, choose M here. The module will be + called ti_sci_pm_domains. Note this is needed early in boot before + rootfs may be available. + +endif diff --git a/drivers/pmdomain/ti/Makefile b/drivers/pmdomain/ti/Makefile index 69580afbb4366..af6cd056c1586 100644 --- a/drivers/pmdomain/ti/Makefile +++ b/drivers/pmdomain/ti/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o +obj-$(CONFIG_OMAP2PLUS_PRM) += omap_prm.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 2cae17b65fd93..1a93001c9e367 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -50,18 +50,6 @@ config WKUP_M3_IPC to communicate and use the Wakeup M3 for PM features like suspend resume and boots it using wkup_m3_rproc driver. -config TI_SCI_PM_DOMAINS - tristate "TI SCI PM Domains Driver" - depends on TI_SCI_PROTOCOL - depends on PM_GENERIC_DOMAINS - help - Generic power domain implementation for TI device implementing - the TI SCI protocol. - - To compile this as a module, choose M here. The module will be - called ti_sci_pm_domains. Note this is needed early in boot before - rootfs may be available. - config TI_K3_RINGACC tristate "K3 Ring accelerator Sub System" depends on ARCH_K3 || COMPILE_TEST From d8237f8733efeb2f687907e73c658e4662dbfa00 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 12 Sep 2023 15:41:22 +0200 Subject: [PATCH 28/56] pmdomain: xilinx: Move Kconfig option to the pmdomain subsystem The Kconfig option belongs closer to the corresponding implementation, hence let's move it from the soc subsystem to the pmdomain subsystem. Cc: Michal Simek Signed-off-by: Ulf Hansson --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/xilinx/Kconfig | 10 ++++++++++ drivers/soc/xilinx/Kconfig | 9 --------- 3 files changed, 11 insertions(+), 9 deletions(-) create mode 100644 drivers/pmdomain/xilinx/Kconfig diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 33bfec9c4f7a6..c98c5bf75a14b 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -16,5 +16,6 @@ source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" source "drivers/pmdomain/tegra/Kconfig" source "drivers/pmdomain/ti/Kconfig" +source "drivers/pmdomain/xilinx/Kconfig" endmenu diff --git a/drivers/pmdomain/xilinx/Kconfig b/drivers/pmdomain/xilinx/Kconfig new file mode 100644 index 0000000000000..5242753d848a8 --- /dev/null +++ b/drivers/pmdomain/xilinx/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +config ZYNQMP_PM_DOMAINS + bool "Enable Zynq MPSoC generic PM domains" + default y + depends on PM && ZYNQMP_FIRMWARE + select PM_GENERIC_DOMAINS + help + Say yes to enable device power management through PM domains + If in doubt, say N. diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig index 8a755a5c88360..49d69d6e18fea 100644 --- a/drivers/soc/xilinx/Kconfig +++ b/drivers/soc/xilinx/Kconfig @@ -16,15 +16,6 @@ config ZYNQMP_POWER If in doubt, say N. -config ZYNQMP_PM_DOMAINS - bool "Enable Zynq MPSoC generic PM domains" - default y - depends on PM && ZYNQMP_FIRMWARE - select PM_GENERIC_DOMAINS - help - Say yes to enable device power management through PM domains - If in doubt, say N. - config XLNX_EVENT_MANAGER bool "Enable Xilinx Event Management Driver" depends on ZYNQMP_FIRMWARE From 38c2efa260e6d0eab861c21c6ad1e4d79e1377ac Mon Sep 17 00:00:00 2001 From: Justin Stitt Date: Mon, 14 Aug 2023 22:11:28 +0000 Subject: [PATCH 29/56] pmdomain: renesas: rmobile-sysc: fix -Wvoid-pointer-to-enum-cast warning When building with clang 18 I see the following warning: | drivers/soc/renesas/rmobile-sysc.c:193:22: warning: cast to smaller integer | type 'enum pd_types' from 'const void *' [-Wvoid-pointer-to-enum-cast] | 193 | add_special_pd(np, (enum pd_types)id->data); This is due to the fact that `id->data` is a void* and `enum pd_types` has the size of an integer. This cast from pointer-width to int-width causes truncation and possible data loss. Instead, cast to `uintptr_t` which has the same width as void*. Reported-by: Nathan Chancellor Closes: https://github.com/ClangBuiltLinux/linux/issues/1910 Signed-off-by: Justin Stitt Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230814-void-drivers-soc-renesas-rmobile-sysc-v1-1-6648dfd854de@google.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/renesas/rmobile-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pmdomain/renesas/rmobile-sysc.c b/drivers/pmdomain/renesas/rmobile-sysc.c index 912daadaa10d1..0b77f37787d58 100644 --- a/drivers/pmdomain/renesas/rmobile-sysc.c +++ b/drivers/pmdomain/renesas/rmobile-sysc.c @@ -190,7 +190,7 @@ static void __init get_special_pds(void) /* PM domains containing other special devices */ for_each_matching_node_and_match(np, special_ids, &id) - add_special_pd(np, (enum pd_types)id->data); + add_special_pd(np, (uintptr_t)id->data); } static void __init put_special_pds(void) From 0958eccbeb818f56b314c34881315bd6e81d90e2 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sat, 16 Sep 2023 20:59:52 +0300 Subject: [PATCH 30/56] pmdomain: qcom: rpmhpd: Add support for SM7150 rpmh clocks This adds the RPMH clocks present in SM7150 SoC. Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230916175952.178611-3-danila@jiaxyga.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/qcom/rpmhpd.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index a87e336d5e33b..ec2582f7225c8 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -337,6 +337,23 @@ static const struct rpmhpd_desc sm6350_desc = { .num_pds = ARRAY_SIZE(sm6350_rpmhpds), }; +/* SM7150 RPMH powerdomains */ +static struct rpmhpd *sm7150_rpmhpds[] = { + [RPMHPD_CX] = &cx_w_mx_parent, + [RPMHPD_CX_AO] = &cx_ao_w_mx_parent, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_MSS] = &mss, +}; + +static const struct rpmhpd_desc sm7150_desc = { + .rpmhpds = sm7150_rpmhpds, + .num_pds = ARRAY_SIZE(sm7150_rpmhpds), +}; + /* SM8150 RPMH powerdomains */ static struct rpmhpd *sm8150_rpmhpds[] = { [SM8150_CX] = &cx_w_mx_parent, @@ -562,6 +579,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc}, { .compatible = "qcom,sdx75-rpmhpd", .data = &sdx75_desc}, { .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc }, + { .compatible = "qcom,sm7150-rpmhpd", .data = &sm7150_desc }, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, { .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc }, From 793f4def8c0a4e0ba8e711421768fd2bcca04cd1 Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Wed, 27 Sep 2023 06:07:33 -0700 Subject: [PATCH 31/56] dt-bindings: power: Update prefixes for AON power domain Use "JH7110_AON_PD_" prefix for AON power domain for JH7110 SoC. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230927130734.9921-2-changhuang.liang@starfivetech.com Signed-off-by: Ulf Hansson --- include/dt-bindings/power/starfive,jh7110-pmu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h index 341e2a0676ba0..7b4f24927dee8 100644 --- a/include/dt-bindings/power/starfive,jh7110-pmu.h +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -14,7 +14,8 @@ #define JH7110_PD_ISP 5 #define JH7110_PD_VENC 6 -#define JH7110_PD_DPHY_TX 0 -#define JH7110_PD_DPHY_RX 1 +/* AON Power Domain */ +#define JH7110_AON_PD_DPHY_TX 0 +#define JH7110_AON_PD_DPHY_RX 1 #endif From a7de2727e5f35110fe68ea08c899647a41bcc86c Mon Sep 17 00:00:00 2001 From: Changhuang Liang Date: Wed, 27 Sep 2023 06:07:34 -0700 Subject: [PATCH 32/56] pmdomain: starfive: Update prefixes for AON power domain Use "JH7110_AON_PD_" prefix for AON power doamin for JH7110 SoC. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang Link: https://lore.kernel.org/r/20230927130734.9921-3-changhuang.liang@starfivetech.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/starfive/jh71xx-pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/starfive/jh71xx-pmu.c b/drivers/pmdomain/starfive/jh71xx-pmu.c index 2724bee7e85f2..74720c09a6e3a 100644 --- a/drivers/pmdomain/starfive/jh71xx-pmu.c +++ b/drivers/pmdomain/starfive/jh71xx-pmu.c @@ -419,11 +419,11 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = { }; static const struct jh71xx_domain_info jh7110_aon_power_domains[] = { - [JH7110_PD_DPHY_TX] = { + [JH7110_AON_PD_DPHY_TX] = { .name = "DPHY-TX", .bit = 30, }, - [JH7110_PD_DPHY_RX] = { + [JH7110_AON_PD_DPHY_RX] = { .name = "DPHY-RX", .bit = 31, }, From a1571f1f333c2fced076f0d54ed771d1838d827f Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 18 Sep 2023 11:37:45 +0200 Subject: [PATCH 33/56] dt-bindings: power: Add MT8365 power domains Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-2-msp@baylibre.com Signed-off-by: Ulf Hansson --- .../power/mediatek,power-controller.yaml | 6 ++++++ .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index c9acef80f4528..8985e2df8a566 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8188-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller '#power-domain-cells': const: 1 @@ -88,6 +89,7 @@ $defs: "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. + "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain. maxItems: 1 clocks: @@ -115,6 +117,10 @@ $defs: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG register range. + mediatek,infracfg-nao: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the INFRACFG-NAO register range. + mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register range. diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h new file mode 100644 index 0000000000000..e6cfd0ec7871d --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ From c6bee73207684bf6dac2855de8faa508c3c5026d Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 18 Sep 2023 11:37:46 +0200 Subject: [PATCH 34/56] pmdomain: mediatek: Move bools to a flags field To simplify the macros, use a flags field for simple bools. This is in preparation for more flags. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-3-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 6 +++--- drivers/pmdomain/mediatek/mtk-pm-domains.h | 19 +++++++++++-------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index ee962804b8303..da675a33bdf5f 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st if (!mask) break; - if (bpd[i].bus_prot_reg_update) + if (bpd[i].flags & BUS_PROT_REG_UPDATE) regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); else regmap_write(regmap, bpd[i].bus_prot_set, mask); @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, if (!mask) continue; - if (bpd[i].bus_prot_reg_update) + if (bpd[i].flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); else regmap_write(regmap, bpd[i].bus_prot_clr, mask); - if (bpd[i].ignore_clr_ack) + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) continue; ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index 5ec53ee073c42..d8c0c299dd45c 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -42,23 +42,27 @@ #define SPM_MAX_BUS_PROT_DATA 6 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ +enum scpsys_bus_prot_flags { + BUS_PROT_REG_UPDATE = BIT(1), + BUS_PROT_IGNORE_CLR_ACK = BIT(2), +}; + +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \ .bus_prot_mask = (_mask), \ .bus_prot_set = _set, \ .bus_prot_clr = _clr, \ .bus_prot_sta = _sta, \ - .bus_prot_reg_update = _update, \ - .ignore_clr_ack = _ignore, \ + .flags = _flags \ } #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _sta, 0) #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK) #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE) #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data { u32 bus_prot_set; u32 bus_prot_clr; u32 bus_prot_sta; - bool bus_prot_reg_update; - bool ignore_clr_ack; + u8 flags; }; /** From ae442ba85a6657f284cdc166ba107af3a762e668 Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 18 Sep 2023 11:37:47 +0200 Subject: [PATCH 35/56] pmdomain: mediatek: Split bus_prot_mask bus_prot_mask is used for all operations, set clear and acknowledge. In preparation of m8365 power domain support split this one mask into two, one mask for set and clear, another one for acknowledge. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-4-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 24 +++++++++++++--------- drivers/pmdomain/mediatek/mtk-pm-domains.h | 14 +++++++------ 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index da675a33bdf5f..dbb268e963106 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -123,18 +123,20 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st int i, ret; for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask = bpd[i].bus_prot_mask; + u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; + u32 sta_mask = bpd[i].bus_prot_sta_mask; + u32 val; - if (!mask) + if (!set_clr_mask) break; if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_set, mask); + regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) == mask, + val, (val & sta_mask) == sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -160,21 +162,23 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, int i, ret; for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { - u32 val, mask = bpd[i].bus_prot_mask; + u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; + u32 sta_mask = bpd[i].bus_prot_sta_mask; + u32 val; - if (!mask) + if (!set_clr_mask) continue; if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_clr, mask); + regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) continue; ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), + val, !(val & sta_mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index d8c0c299dd45c..4c3ab72a907b3 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -47,22 +47,23 @@ enum scpsys_bus_prot_flags { BUS_PROT_IGNORE_CLR_ACK = BIT(2), }; -#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \ - .bus_prot_mask = (_mask), \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ + .bus_prot_set_clr_mask = (_set_clr_mask), \ .bus_prot_set = _set, \ .bus_prot_clr = _clr, \ + .bus_prot_sta_mask = (_sta_mask), \ .bus_prot_sta = _sta, \ .flags = _flags \ } #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, 0) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -71,9 +72,10 @@ enum scpsys_bus_prot_flags { INFRA_TOPAXI_PROTECTSTA1) struct scpsys_bus_prot_data { - u32 bus_prot_mask; + u32 bus_prot_set_clr_mask; u32 bus_prot_set; u32 bus_prot_clr; + u32 bus_prot_sta_mask; u32 bus_prot_sta; u8 flags; }; From 2ec81379eaf0feb2fe6d48c2789e66ca4191c5ba Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 18 Sep 2023 11:37:48 +0200 Subject: [PATCH 36/56] pmdomain: mediatek: Create bus protection operation functions Separate the register access used for bus protection enable/disable into their own functions. These will be used later for WAY_EN support. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-5-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 68 +++++++++++++--------- 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index dbb268e963106..5b694fde7b56e 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -118,26 +118,50 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) MTK_POLL_TIMEOUT); } +static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 sta_mask = bpd->bus_prot_sta_mask; + u32 val; + + if (bpd->flags & BUS_PROT_REG_UPDATE) + regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + + if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) + return 0; + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, !(val & sta_mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 sta_mask = bpd->bus_prot_sta_mask; + u32 val; + + if (bpd->flags & BUS_PROT_REG_UPDATE) + regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, (val & sta_mask) == sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap) { int i, ret; for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; - u32 sta_mask = bpd[i].bus_prot_sta_mask; - u32 val; - - if (!set_clr_mask) + if (!bpd[i].bus_prot_set_clr_mask) break; - if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); - - ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & sta_mask) == sta_mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = scpsys_bus_protect_set(&bpd[i], regmap); if (ret) return ret; } @@ -162,24 +186,10 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, int i, ret; for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { - u32 set_clr_mask = bpd[i].bus_prot_set_clr_mask; - u32 sta_mask = bpd[i].bus_prot_sta_mask; - u32 val; - - if (!set_clr_mask) - continue; - - if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); - - if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) + if (!bpd[i].bus_prot_set_clr_mask) continue; - ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & sta_mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = scpsys_bus_protect_clear(&bpd[i], regmap); if (ret) return ret; } From 151bd6c55f73df589d88e84a948edf0f0b4e9bc0 Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 18 Sep 2023 11:37:49 +0200 Subject: [PATCH 37/56] pmdomain: mediatek: Unify configuration for infracfg and smi Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-6-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mt6795-pm-domains.h | 16 +- drivers/pmdomain/mediatek/mt8167-pm-domains.h | 20 +- drivers/pmdomain/mediatek/mt8173-pm-domains.h | 16 +- drivers/pmdomain/mediatek/mt8183-pm-domains.h | 125 ++++++---- drivers/pmdomain/mediatek/mt8186-pm-domains.h | 236 ++++++++++-------- drivers/pmdomain/mediatek/mt8188-pm-domains.h | 223 +++++++++++------ drivers/pmdomain/mediatek/mt8192-pm-domains.h | 112 ++++++--- drivers/pmdomain/mediatek/mt8195-pm-domains.h | 199 +++++++++------ drivers/pmdomain/mediatek/mtk-pm-domains.c | 64 ++--- drivers/pmdomain/mediatek/mtk-pm-domains.h | 26 +- 10 files changed, 612 insertions(+), 425 deletions(-) diff --git a/drivers/pmdomain/mediatek/mt6795-pm-domains.h b/drivers/pmdomain/mediatek/mt6795-pm-domains.h index ef07c9dfdd9b9..a3f7785b04bd3 100644 --- a/drivers/pmdomain/mediatek/mt6795-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt6795-pm-domains.h @@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT6795_POWER_DOMAIN_MJC] = { @@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = { .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/pmdomain/mediatek/mt8167-pm-domains.h b/drivers/pmdomain/mediatek/mt8167-pm-domains.h index 4d6c327596060..8a0e898b79ab8 100644 --- a/drivers/pmdomain/mediatek/mt8167-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8167-pm-domains.h @@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | - MT8167_TOP_AXI_PROT_EN_MCU_MM), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | + MT8167_TOP_AXI_PROT_EN_MCU_MM), }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | - MT8167_TOP_AXI_PROT_EN_MFG_EMI), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | + MT8167_TOP_AXI_PROT_EN_MFG_EMI), }, }, [MT8167_POWER_DOMAIN_MFG_2D] = { @@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = 0, .caps = MTK_SCPD_ACTIVE_WAKEUP, - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | - MT8167_TOP_AXI_PROT_EN_CONN_MCU | - MT8167_TOP_AXI_PROT_EN_MCU_CONN), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | + MT8167_TOP_AXI_PROT_EN_CONN_MCU | + MT8167_TOP_AXI_PROT_EN_MCU_CONN), }, }, }; diff --git a/drivers/pmdomain/mediatek/mt8173-pm-domains.h b/drivers/pmdomain/mediatek/mt8173-pm-domains.h index 1a5dc63b73571..7be0f47f52140 100644 --- a/drivers/pmdomain/mediatek/mt8173-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8173-pm-domains.h @@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT8173_POWER_DOMAIN_VENC_LT] = { @@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .bp_infracfg = { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/pmdomain/mediatek/mt8183-pm-domains.h b/drivers/pmdomain/mediatek/mt8183-pm-domains.h index 99de67fe5de89..c4c1b63d85b19 100644 --- a/drivers/pmdomain/mediatek/mt8183-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8183-pm-domains.h @@ -28,9 +28,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_CONN, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_MFG_ASYNC] = { @@ -79,11 +82,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_1_MFG, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MFG, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_DISP] = { @@ -94,14 +103,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_1_DISP, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_DISP, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_DISP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -115,18 +129,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, - MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_CAM, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_CAM, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR_IGN(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_CAM, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -140,18 +160,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_ISP, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, + BUS_PROT_WR_IGN(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_ISP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -165,8 +186,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, + .bp_cfg = { + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VDEC, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -180,8 +202,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, + .bp_cfg = { + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VENC, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -195,22 +218,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_VPU_TOP, MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi = { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -224,12 +249,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), @@ -244,12 +271,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), diff --git a/drivers/pmdomain/mediatek/mt8186-pm-domains.h b/drivers/pmdomain/mediatek/mt8186-pm-domains.h index fce86f79c5055..cbac715c38fac 100644 --- a/drivers/pmdomain/mediatek/mt8186-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8186-pm-domains.h @@ -33,23 +33,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -101,15 +105,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_DIS_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), }, }, [MT8186_POWER_DOMAIN_IMG] = { @@ -120,15 +126,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -150,15 +158,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -170,15 +180,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -210,15 +222,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -230,15 +244,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -250,15 +266,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, - MT8186_TOP_AXI_PROT_EN_2_SET, - MT8186_TOP_AXI_PROT_EN_2_CLR, - MT8186_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, - MT8186_TOP_AXI_PROT_EN_2_SET, - MT8186_TOP_AXI_PROT_EN_2_CLR, - MT8186_TOP_AXI_PROT_EN_2_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -268,23 +286,27 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .ctl_offs = 0x304, .pwr_sta_offs = 0x16C, .pwr_sta2nd_offs = 0x170, - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), }, .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -320,15 +342,17 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, - MT8186_TOP_AXI_PROT_EN_3_SET, - MT8186_TOP_AXI_PROT_EN_3_CLR, - MT8186_TOP_AXI_PROT_EN_3_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, - MT8186_TOP_AXI_PROT_EN_3_SET, - MT8186_TOP_AXI_PROT_EN_3_CLR, - MT8186_TOP_AXI_PROT_EN_3_STA), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), }, .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, }, diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdomain/mediatek/mt8188-pm-domains.h index 0692cb444ed02..06834ab6597c1 100644 --- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h @@ -33,28 +33,34 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, MT8188_TOP_AXI_PROT_EN_1_SET, MT8188_TOP_AXI_PROT_EN_1_CLR, MT8188_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), @@ -99,12 +105,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -135,8 +143,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -151,8 +160,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -165,12 +175,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .ctl_offs = 0x35C, .pwr_sta_offs = 0x16C, .pwr_sta2nd_offs = 0x170, - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -185,12 +197,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -205,12 +219,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -225,12 +241,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -245,12 +263,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -265,24 +285,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), @@ -296,16 +321,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), @@ -319,16 +347,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -342,8 +373,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -358,8 +390,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -374,16 +407,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -397,12 +433,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -417,12 +455,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -437,12 +477,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), @@ -457,16 +499,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -479,16 +524,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .ctl_offs = 0x3A4, .pwr_sta_offs = 0x16C, .pwr_sta2nd_offs = 0x170, - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -503,12 +551,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -541,24 +591,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .ctl_offs = 0x3A0, .pwr_sta_offs = 0x16C, .pwr_sta2nd_offs = 0x170, - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, MT8188_TOP_AXI_PROT_EN_1_SET, MT8188_TOP_AXI_PROT_EN_1_CLR, MT8188_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -573,20 +628,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = BIT(8), .sram_pdn_ack_bits = BIT(12), - .bp_infracfg = { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), diff --git a/drivers/pmdomain/mediatek/mt8192-pm-domains.h b/drivers/pmdomain/mediatek/mt8192-pm-domains.h index b97b2051920fe..6f139eed37693 100644 --- a/drivers/pmdomain/mediatek/mt8192-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8192-pm-domains.h @@ -19,8 +19,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_AUDIO, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), @@ -34,16 +35,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_CONN, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_CONN_2ND, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_CONN, MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_STA1), @@ -68,20 +72,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_MFG1, MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_MFG1, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MFG1, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), @@ -141,24 +149,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_DISP, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, + BUS_PROT_WR_IGN(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_DISP, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_DISP, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), @@ -172,12 +185,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_IPE, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -191,12 +206,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), @@ -210,12 +227,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_ISP2, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -229,12 +248,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_MDP, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), @@ -248,12 +269,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VENC, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -267,12 +290,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VDEC, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -295,24 +320,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_CAM, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_CAM, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_CAM, MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_VDNR_CAM, MT8192_TOP_AXI_PROT_EN_VDNR_SET, MT8192_TOP_AXI_PROT_EN_VDNR_CLR, MT8192_TOP_AXI_PROT_EN_VDNR_STA1), diff --git a/drivers/pmdomain/mediatek/mt8195-pm-domains.h b/drivers/pmdomain/mediatek/mt8195-pm-domains.h index d7387ea1b9c91..59aa031ae6323 100644 --- a/drivers/pmdomain/mediatek/mt8195-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt8195-pm-domains.h @@ -23,12 +23,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, MT8195_TOP_AXI_PROT_EN_VDNR_SET, MT8195_TOP_AXI_PROT_EN_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -42,12 +44,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, MT8195_TOP_AXI_PROT_EN_VDNR_SET, MT8195_TOP_AXI_PROT_EN_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -95,8 +99,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_ADSP, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), @@ -111,8 +116,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_AUDIO, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), @@ -136,28 +142,34 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x178, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MFG1, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_MFG1, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_1_MFG1, MT8195_TOP_AXI_PROT_EN_1_SET, MT8195_TOP_AXI_PROT_EN_1_CLR, MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MFG1_2ND, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -222,24 +234,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VPPSYS0, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -253,16 +270,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDOSYS0, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -276,16 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -299,16 +322,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -322,8 +348,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -338,8 +365,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -364,16 +392,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_WPESYS, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -387,20 +418,24 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC0, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -415,12 +450,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), @@ -435,12 +472,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -455,16 +494,19 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VENC, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -479,12 +521,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -499,12 +543,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IMG, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), @@ -529,12 +575,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IPE, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_IPE, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -549,24 +597,29 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { .pwr_sta2nd_offs = 0x170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, + .bp_cfg = { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_CAM, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_CAM, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_1_CAM, MT8195_TOP_AXI_PROT_EN_1_SET, MT8195_TOP_AXI_PROT_EN_1_CLR, MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_CAM, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index 5b694fde7b56e..c1154de98830a 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) MTK_POLL_TIMEOUT); } -static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) { + if (bpd->flags & BUS_PROT_COMPONENT_SMI) + return pd->smi; + else + return pd->infracfg; +} + +static int scpsys_bus_protect_clear(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) +{ + struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask = bpd->bus_prot_sta_mask; u32 val; @@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } -static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static int scpsys_bus_protect_set(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) { + struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask = bpd->bus_prot_sta_mask; u32 val; @@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap) +static int scpsys_bus_protect_enable(struct scpsys_domain *pd) { - int i, ret; + for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { + const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; + int ret; - for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - if (!bpd[i].bus_prot_set_clr_mask) + if (!bpd->bus_prot_set_clr_mask) break; - ret = scpsys_bus_protect_set(&bpd[i], regmap); + ret = scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st return 0; } -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) -{ - int ret; - - ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); - if (ret) - return ret; - - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); -} - -static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static int scpsys_bus_protect_disable(struct scpsys_domain *pd) { - int i, ret; + for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { + const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; + int ret; - for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { - if (!bpd[i].bus_prot_set_clr_mask) + if (!bpd->bus_prot_set_clr_mask) continue; - ret = scpsys_bus_protect_clear(&bpd[i], regmap); + ret = scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, return 0; } -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) -{ - int ret; - - ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); - if (ret) - return ret; - - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); -} - static int scpsys_regulator_enable(struct regulator *supply) { return supply ? regulator_enable(supply) : 0; diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index 4c3ab72a907b3..209f68dcaeac6 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -45,6 +45,8 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE = BIT(1), BUS_PROT_IGNORE_CLR_ACK = BIT(2), + BUS_PROT_COMPONENT_INFRA = BIT(4), + BUS_PROT_COMPONENT_SMI = BIT(5), }; #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ @@ -56,17 +58,19 @@ enum scpsys_bus_prot_flags { .flags = _flags \ } -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) +#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip) -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) +#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK) -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) +#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE) -#define BUS_PROT_UPDATE_TOPAXI(_mask) \ - BUS_PROT_UPDATE(_mask, \ +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ + BUS_PROT_UPDATE(INFRA, _mask, \ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) @@ -90,8 +94,7 @@ struct scpsys_bus_prot_data { * @ext_buck_iso_offs: The offset for external buck isolation * @ext_buck_iso_mask: The mask for external buck isolation * @caps: The flag for active wake-up action. - * @bp_infracfg: bus protection for infracfg subsystem - * @bp_smi: bus protection for smi subsystem + * @bp_cfg: bus protection configuration for any subsystem */ struct scpsys_domain_data { const char *name; @@ -102,8 +105,7 @@ struct scpsys_domain_data { int ext_buck_iso_offs; u32 ext_buck_iso_mask; u8 caps; - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; }; From ecaf11aaee98d3f79f195b73c5efc7065ef00072 Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Mon, 18 Sep 2023 11:37:50 +0200 Subject: [PATCH 38/56] pmdomain: mediatek: Add support for WAY_EN operations This updates the power domain to support WAY_EN operations. WAY_EN operations on mt8365 are using a different component to check for the acknowledgment, namely the infracfg-nao component. Also to enable a way it the bit needs to be cleared while disabling a way needs a bit to be set. To support these two operations two flags are added, BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally another regmap is created if the INFRA_NAO capability is set. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-7-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++--- drivers/pmdomain/mediatek/mtk-pm-domains.h | 3 ++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index c1154de98830a..4bf3a375b7490 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -44,6 +44,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd, return pd->infracfg; } +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) +{ + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO) + return pd->infracfg_nao; + else + return scpsys_bus_protect_get_regmap(pd, bpd); +} + static int scpsys_bus_protect_clear(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask = bpd->bus_prot_sta_mask; + u32 expected_ack; u32 val; + expected_ack = (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mask : 0); + if (bpd->flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); else @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd, if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) return 0; - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) == expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } static int scpsys_bus_protect_set(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask = bpd->bus_prot_sta_mask; u32 val; @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) == sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) if (!bpd->bus_prot_set_clr_mask) break; - ret = scpsys_bus_protect_set(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret = scpsys_bus_protect_clear(pd, bpd); + else + ret = scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) if (!bpd->bus_prot_set_clr_mask) continue; - ret = scpsys_bus_protect_clear(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret = scpsys_bus_protect_set(pd, bpd); + else + ret = scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no return ERR_CAST(pd->smi); } + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) { + pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao"); + if (IS_ERR(pd->infracfg_nao)) + return ERR_CAST(pd->infracfg_nao); + } else { + pd->infracfg_nao = NULL; + } + num_clks = of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index 209f68dcaeac6..17c0332177045 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) +#define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -45,8 +46,10 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE = BIT(1), BUS_PROT_IGNORE_CLR_ACK = BIT(2), + BUS_PROT_INVERTED = BIT(3), BUS_PROT_COMPONENT_INFRA = BIT(4), BUS_PROT_COMPONENT_SMI = BIT(5), + BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6), }; #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ From d2567a84520d10b8418cc3b53454e4b6aadaf728 Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Mon, 18 Sep 2023 11:37:51 +0200 Subject: [PATCH 39/56] pmdomain: mediatek: Add support for MTK_SCPD_STRICT_BUS_PROTECTION cap This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-8-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 27 ++++++++++++++++++---- drivers/pmdomain/mediatek/mtk-pm-domains.h | 3 ++- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index 4bf3a375b7490..69cdf6ff00b88 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -262,9 +262,17 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } ret = scpsys_sram_enable(pd); if (ret < 0) @@ -274,12 +282,23 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret < 0) goto err_disable_sram; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index 17c0332177045..aaba5e6b0536f 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -12,6 +12,7 @@ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_HAS_INFRA_NAO BIT(7) +#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -107,7 +108,7 @@ struct scpsys_domain_data { u32 sram_pdn_ack_bits; int ext_buck_iso_offs; u32 ext_buck_iso_mask; - u8 caps; + u16 caps; const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; From c5b5831f3c168a1bf1172159c4956e721a0064cf Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 18 Sep 2023 11:37:52 +0200 Subject: [PATCH 40/56] pmdomain: mediatek: Add support for MT8365 Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230918093751.1188668-9-msp@baylibre.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/mediatek/mt8365-pm-domains.h | 197 ++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + include/linux/soc/mediatek/infracfg.h | 41 ++++ 3 files changed, 243 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt8365-pm-domains.h diff --git a/drivers/pmdomain/mediatek/mt8365-pm-domains.h b/drivers/pmdomain/mediatek/mt8365-pm-domains.h new file mode 100644 index 0000000000000..3d83d49eaa7c8 --- /dev/null +++ b/drivers/pmdomain/mediatek/mt8365-pm-domains.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \ + BUS_PROT_WR(INFRA, _mask, \ + MT8365_INFRA_TOPAXI_PROTECTEN_SET, \ + MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \ + MT8365_INFRA_TOPAXI_PROTECTEN_STA1) + +#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \ + BUS_PROT_WR(INFRA, _mask, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1) + +#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \ + BUS_PROT_WR(SMI, BIT(port), \ + MT8365_SMI_COMMON_CLAMP_EN_SET, \ + MT8365_SMI_COMMON_CLAMP_EN_CLR, \ + MT8365_SMI_COMMON_CLAMP_EN) + +#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ + _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \ + BUS_PROT_COMPONENT_INFRA | \ + BUS_PROT_STA_COMPONENT_INFRA_NAO | \ + BUS_PROT_INVERTED | \ + BUS_PROT_REG_UPDATE) + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = { + [MT8365_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x30c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 | + MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 | + MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 | + MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 | + MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1), + MT8365_BUS_PROT_WAY_EN( + MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S, + MT8365_INFRA_TOPAXI_SI0_CTL, + MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED, + MT8365_INFRA_NAO_TOPAXI_SI0_STA), + MT8365_BUS_PROT_WAY_EN( + MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1, + MT8365_INFRA_TOPAXI_SI2_CTL, + MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED, + MT8365_INFRA_NAO_TOPAXI_SI2_STA), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S), + }, + .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO, + }, + [MT8365_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_cfg = { + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(12, 8), + .sram_pdn_ack_bits = GENMASK(17, 13), + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB), + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB), + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 | + MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG), + }, + }, + [MT8365_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST), + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0370, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_cfg = { + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3), + }, + }, + [MT8365_POWER_DOMAIN_APU] = { + .name = "apu", + .sta_mask = BIT(16), + .ctl_offs = 0x0378, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(14, 8), + .sram_pdn_ack_bits = GENMASK(21, 15), + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP | + MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST), + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4), + }, + }, + [MT8365_POWER_DOMAIN_DSP] = { + .name = "dsp", + .sta_mask = BIT(17), + .ctl_offs = 0x037C, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_cfg = { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data = { + .domains_data = scpsys_domain_data_mt8365, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index 69cdf6ff00b88..e26dc17d07ad7 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -24,6 +24,7 @@ #include "mt8188-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8195-power-controller", .data = &mt8195_scpsys_data, }, + { + .compatible = "mediatek,mt8365-power-controller", + .data = &mt8365_scpsys_data, + }, { } }; diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 07f67b3d8e970..6c6cccc848f48 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,47 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H +#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228 +#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0 +#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4 +#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11) +#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13) +#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21) +#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258 +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8 +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31) + +#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0 +#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24) +#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28 +#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14) +#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200 +#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6) +#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234 +#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5) + +#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0 +#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8 + #define MT8195_TOP_AXI_PROT_EN_STA1 0x228 #define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 #define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 From bc0d59d757ed528a5219de74fa4adbf75236f4cc Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Thu, 7 Sep 2023 11:55:14 +0200 Subject: [PATCH 41/56] pmdomain: ti: add missing of_node_put for_each_node_with_property performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. This was done using the Coccinelle semantic patch iterators/for_each_child.cocci Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/20230907095521.14053-5-Julia.Lawall@inria.fr Signed-off-by: Ulf Hansson --- drivers/pmdomain/ti/ti_sci_pm_domains.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/ti/ti_sci_pm_domains.c b/drivers/pmdomain/ti/ti_sci_pm_domains.c index 34645104fe45d..c091d569ecd5f 100644 --- a/drivers/pmdomain/ti/ti_sci_pm_domains.c +++ b/drivers/pmdomain/ti/ti_sci_pm_domains.c @@ -153,14 +153,18 @@ static int ti_sci_pm_domain_probe(struct platform_device *pdev) max_id = args.args[0]; pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); - if (!pd) + if (!pd) { + of_node_put(np); return -ENOMEM; + } pd->pd.name = devm_kasprintf(dev, GFP_KERNEL, "pd:%d", args.args[0]); - if (!pd->pd.name) + if (!pd->pd.name) { + of_node_put(np); return -ENOMEM; + } pd->pd.power_off = ti_sci_pd_power_off; pd->pd.power_on = ti_sci_pd_power_on; From 3ba9fdfaa550936837b50b73d6c27ac401fde875 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 6 Oct 2023 17:46:13 -0500 Subject: [PATCH 42/56] pmdomain: Use device_get_match_data() Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20231006224614.444488-1-robh@kernel.org Signed-off-by: Ulf Hansson --- drivers/pmdomain/actions/owl-sps.c | 16 +++++----------- drivers/pmdomain/imx/gpc.c | 7 +++---- drivers/pmdomain/rockchip/pm-domains.c | 13 ++++--------- 3 files changed, 12 insertions(+), 24 deletions(-) diff --git a/drivers/pmdomain/actions/owl-sps.c b/drivers/pmdomain/actions/owl-sps.c index 73a9e0bb7e8ed..3a586d1f32567 100644 --- a/drivers/pmdomain/actions/owl-sps.c +++ b/drivers/pmdomain/actions/owl-sps.c @@ -8,8 +8,10 @@ * Copyright (c) 2017 Andreas Färber */ +#include #include -#include +#include +#include #include #include #include @@ -96,24 +98,16 @@ static int owl_sps_init_domain(struct owl_sps *sps, int index) static int owl_sps_probe(struct platform_device *pdev) { - const struct of_device_id *match; const struct owl_sps_info *sps_info; struct owl_sps *sps; int i, ret; - if (!pdev->dev.of_node) { - dev_err(&pdev->dev, "no device node\n"); - return -ENODEV; - } - - match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev); - if (!match || !match->data) { + sps_info = device_get_match_data(&pdev->dev); + if (!sps_info) { dev_err(&pdev->dev, "unknown compatible or missing data\n"); return -EINVAL; } - sps_info = match->data; - sps = devm_kzalloc(&pdev->dev, struct_size(sps, domains, sps_info->num_domains), GFP_KERNEL); diff --git a/drivers/pmdomain/imx/gpc.c b/drivers/pmdomain/imx/gpc.c index 90a8b2c0676ff..114f44ca07dd5 100644 --- a/drivers/pmdomain/imx/gpc.c +++ b/drivers/pmdomain/imx/gpc.c @@ -7,9 +7,10 @@ #include #include #include -#include +#include #include #include +#include #include #include @@ -403,9 +404,7 @@ static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap, static int imx_gpc_probe(struct platform_device *pdev) { - const struct of_device_id *of_id = - of_match_device(imx_gpc_dt_ids, &pdev->dev); - const struct imx_gpc_dt_data *of_id_data = of_id->data; + const struct imx_gpc_dt_data *of_id_data = device_get_match_data(&pdev->dev); struct device_node *pgc_node; struct regmap *regmap; void __iomem *base; diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index d5d3ecb38283c..9b76b62869d0d 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -9,11 +9,13 @@ #include #include #include +#include #include #include +#include +#include #include #include -#include #include #include #include @@ -857,7 +859,6 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) struct device_node *node; struct device *parent; struct rockchip_pmu *pmu; - const struct of_device_id *match; const struct rockchip_pmu_info *pmu_info; int error; @@ -866,13 +867,7 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) return -ENODEV; } - match = of_match_device(dev->driver->of_match_table, dev); - if (!match || !match->data) { - dev_err(dev, "missing pmu data\n"); - return -EINVAL; - } - - pmu_info = match->data; + pmu_info = device_get_match_data(dev); pmu = devm_kzalloc(dev, struct_size(pmu, domains, pmu_info->num_domains), From 016b4e5e286282a98902bfc8ac9273da89d07a6f Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 12 Oct 2023 17:35:50 +0200 Subject: [PATCH 43/56] pmdomain: qcom: cpr: Drop the ->opp_to_performance_state() callback Since commit 7c41cdcd3bbe ("OPP: Simplify the over-designed pstate <-> level dance"), there is no longer any need for genpd providers to assign the ->opp_to_performance_state(), hence let's drop it. Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Ulf Hansson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231012153550.101425-1-ulf.hansson@linaro.org --- drivers/pmdomain/qcom/cpr.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pmdomain/qcom/cpr.c b/drivers/pmdomain/qcom/cpr.c index 94a3f09772125..e9dd42bded6f9 100644 --- a/drivers/pmdomain/qcom/cpr.c +++ b/drivers/pmdomain/qcom/cpr.c @@ -1424,12 +1424,6 @@ static const struct cpr_acc_desc qcs404_cpr_acc_desc = { .acc_desc = &qcs404_acc_desc, }; -static unsigned int cpr_get_performance_state(struct generic_pm_domain *genpd, - struct dev_pm_opp *opp) -{ - return dev_pm_opp_get_level(opp); -} - static int cpr_power_off(struct generic_pm_domain *domain) { struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); @@ -1698,7 +1692,6 @@ static int cpr_probe(struct platform_device *pdev) drv->pd.power_off = cpr_power_off; drv->pd.power_on = cpr_power_on; drv->pd.set_performance_state = cpr_set_performance_state; - drv->pd.opp_to_performance_state = cpr_get_performance_state; drv->pd.attach_dev = cpr_pd_attach_dev; ret = pm_genpd_init(&drv->pd, NULL, true); From 40d7f4d2e6de7b2bb6a2fe4cedf824ee670fec6b Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 12 Oct 2023 17:35:58 +0200 Subject: [PATCH 44/56] pmdomain: qcom: rpmpd: Drop the ->opp_to_performance_state() callback Since commit 7c41cdcd3bbe ("OPP: Simplify the over-designed pstate <-> level dance"), there is no longer any need for genpd providers to assign the ->opp_to_performance_state(), hence let's drop it. Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Ulf Hansson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231012153558.101445-1-ulf.hansson@linaro.org --- drivers/pmdomain/qcom/rpmpd.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 3135dd1dafe06..524631dcab4b2 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -908,12 +908,6 @@ static int rpmpd_set_performance(struct generic_pm_domain *domain, return ret; } -static unsigned int rpmpd_get_performance(struct generic_pm_domain *genpd, - struct dev_pm_opp *opp) -{ - return dev_pm_opp_get_level(opp); -} - static int rpmpd_probe(struct platform_device *pdev) { int i; @@ -959,7 +953,6 @@ static int rpmpd_probe(struct platform_device *pdev) rpmpds[i]->pd.power_off = rpmpd_power_off; rpmpds[i]->pd.power_on = rpmpd_power_on; rpmpds[i]->pd.set_performance_state = rpmpd_set_performance; - rpmpds[i]->pd.opp_to_performance_state = rpmpd_get_performance; pm_genpd_init(&rpmpds[i]->pd, NULL, true); data->domains[i] = &rpmpds[i]->pd; From 55089e1fb2d8b637bd9471539c4a7759261d6433 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 12 Oct 2023 17:36:07 +0200 Subject: [PATCH 45/56] pmdomain: qcom: rpmhpd: Drop the ->opp_to_performance_state() callback Since commit 7c41cdcd3bbe ("OPP: Simplify the over-designed pstate <-> level dance"), there is no longer any need for genpd providers to assign the ->opp_to_performance_state(), hence let's drop it. Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Ulf Hansson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231012153607.101465-1-ulf.hansson@linaro.org --- drivers/pmdomain/qcom/rpmhpd.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index ec2582f7225c8..a631fe1f9a068 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -743,12 +743,6 @@ static int rpmhpd_set_performance_state(struct generic_pm_domain *domain, return ret; } -static unsigned int rpmhpd_get_performance_state(struct generic_pm_domain *genpd, - struct dev_pm_opp *opp) -{ - return dev_pm_opp_get_level(opp); -} - static int rpmhpd_update_level_mapping(struct rpmhpd *rpmhpd) { int i; @@ -838,7 +832,6 @@ static int rpmhpd_probe(struct platform_device *pdev) rpmhpds[i]->pd.power_off = rpmhpd_power_off; rpmhpds[i]->pd.power_on = rpmhpd_power_on; rpmhpds[i]->pd.set_performance_state = rpmhpd_set_performance_state; - rpmhpds[i]->pd.opp_to_performance_state = rpmhpd_get_performance_state; pm_genpd_init(&rpmhpds[i]->pd, NULL, true); data->domains[i] = &rpmhpds[i]->pd; From 2e75396f1df61e1f1d26d0d703fc7292c4ae4371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ma=C3=ADra=20Canal?= Date: Tue, 24 Oct 2023 07:10:40 -0300 Subject: [PATCH 46/56] pmdomain: bcm: bcm2835-power: check if the ASB register is equal to enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The commit c494a447c14e ("soc: bcm: bcm2835-power: Refactor ASB control") refactored the ASB control by using a general function to handle both the enable and disable. But this patch introduced a subtle regression: we need to check if !!(readl(base + reg) & ASB_ACK) == enable, not just check if (readl(base + reg) & ASB_ACK) == true. Currently, this is causing an invalid register state in V3D when unloading and loading the driver, because `bcm2835_asb_disable()` will return -ETIMEDOUT and `bcm2835_asb_power_off()` will fail to disable the ASB slave for V3D. Fixes: c494a447c14e ("soc: bcm: bcm2835-power: Refactor ASB control") Signed-off-by: Maíra Canal Reviewed-by: Florian Fainelli Reviewed-by: Stefan Wahren Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231024101251.6357-2-mcanal@igalia.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/bcm/bcm2835-power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pmdomain/bcm/bcm2835-power.c b/drivers/pmdomain/bcm/bcm2835-power.c index 1a179d4e011cf..d2f0233cb6206 100644 --- a/drivers/pmdomain/bcm/bcm2835-power.c +++ b/drivers/pmdomain/bcm/bcm2835-power.c @@ -175,7 +175,7 @@ static int bcm2835_asb_control(struct bcm2835_power *power, u32 reg, bool enable } writel(PM_PASSWORD | val, base + reg); - while (readl(base + reg) & ASB_ACK) { + while (!!(readl(base + reg) & ASB_ACK) == enable) { cpu_relax(); if (ktime_get_ns() - start >= 1000) return -ETIMEDOUT; From 61848698288d93a230cab9c0585e726df66f2402 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Sat, 14 Oct 2023 15:38:21 +0200 Subject: [PATCH 47/56] dt-bindings: power: rpmpd: Add MSM8917, MSM8937 and QM215 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MSM8917, MSM8937 and QM215 SoCs have VDDCX and VDDMX power domains controlled in voltage level mode. Define the MSM8937 and QM215 power domains as aliases because these SoCs are similar to MSM8917 and may share some parts of the device tree. Also add the compatibles for these SoCs to the documentation, with qcom,msm8937-rpmpd using qcom,msm8917-rpmpd as a fallback compatible because there are no known differences. QM215 is not compatible with these because it uses different regulators. Signed-off-by: Otto Pflüger Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231014133823.14088-2-otto.pflueger@abscue.de Signed-off-by: Ulf Hansson --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 81 ++++++++++--------- include/dt-bindings/power/qcom-rpmpd.h | 21 +++++ 2 files changed, 65 insertions(+), 37 deletions(-) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 53886f02d98a9..d38c762e12804 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -15,43 +15,50 @@ description: properties: compatible: - enum: - - qcom,mdm9607-rpmpd - - qcom,msm8226-rpmpd - - qcom,msm8909-rpmpd - - qcom,msm8916-rpmpd - - qcom,msm8939-rpmpd - - qcom,msm8953-rpmpd - - qcom,msm8976-rpmpd - - qcom,msm8994-rpmpd - - qcom,msm8996-rpmpd - - qcom,msm8998-rpmpd - - qcom,qcm2290-rpmpd - - qcom,qcs404-rpmpd - - qcom,qdu1000-rpmhpd - - qcom,sa8155p-rpmhpd - - qcom,sa8540p-rpmhpd - - qcom,sa8775p-rpmhpd - - qcom,sdm660-rpmpd - - qcom,sc7180-rpmhpd - - qcom,sc7280-rpmhpd - - qcom,sc8180x-rpmhpd - - qcom,sc8280xp-rpmhpd - - qcom,sdm670-rpmhpd - - qcom,sdm845-rpmhpd - - qcom,sdx55-rpmhpd - - qcom,sdx65-rpmhpd - - qcom,sdx75-rpmhpd - - qcom,sm6115-rpmpd - - qcom,sm6125-rpmpd - - qcom,sm6350-rpmhpd - - qcom,sm6375-rpmpd - - qcom,sm7150-rpmhpd - - qcom,sm8150-rpmhpd - - qcom,sm8250-rpmhpd - - qcom,sm8350-rpmhpd - - qcom,sm8450-rpmhpd - - qcom,sm8550-rpmhpd + oneOf: + - enum: + - qcom,mdm9607-rpmpd + - qcom,msm8226-rpmpd + - qcom,msm8909-rpmpd + - qcom,msm8916-rpmpd + - qcom,msm8917-rpmpd + - qcom,msm8939-rpmpd + - qcom,msm8953-rpmpd + - qcom,msm8976-rpmpd + - qcom,msm8994-rpmpd + - qcom,msm8996-rpmpd + - qcom,msm8998-rpmpd + - qcom,qcm2290-rpmpd + - qcom,qcs404-rpmpd + - qcom,qdu1000-rpmhpd + - qcom,qm215-rpmpd + - qcom,sa8155p-rpmhpd + - qcom,sa8540p-rpmhpd + - qcom,sa8775p-rpmhpd + - qcom,sc7180-rpmhpd + - qcom,sc7280-rpmhpd + - qcom,sc8180x-rpmhpd + - qcom,sc8280xp-rpmhpd + - qcom,sdm660-rpmpd + - qcom,sdm670-rpmhpd + - qcom,sdm845-rpmhpd + - qcom,sdx55-rpmhpd + - qcom,sdx65-rpmhpd + - qcom,sdx75-rpmhpd + - qcom,sm6115-rpmpd + - qcom,sm6125-rpmpd + - qcom,sm6350-rpmhpd + - qcom,sm6375-rpmpd + - qcom,sm7150-rpmhpd + - qcom,sm8150-rpmhpd + - qcom,sm8250-rpmhpd + - qcom,sm8350-rpmhpd + - qcom,sm8450-rpmhpd + - qcom,sm8550-rpmhpd + - items: + - enum: + - qcom,msm8937-rpmpd + - const: qcom,msm8917-rpmpd '#power-domain-cells': const: 1 diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 83be996cb5eb9..7f4e2983a4c57 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -278,6 +278,27 @@ #define MSM8909_VDDMX MSM8916_VDDMX #define MSM8909_VDDMX_AO MSM8916_VDDMX_AO +/* MSM8917 Power Domain Indexes */ +#define MSM8917_VDDCX 0 +#define MSM8917_VDDCX_AO 1 +#define MSM8917_VDDCX_VFL 2 +#define MSM8917_VDDMX 3 +#define MSM8917_VDDMX_AO 4 + +/* MSM8937 Power Domain Indexes */ +#define MSM8937_VDDCX MSM8917_VDDCX +#define MSM8937_VDDCX_AO MSM8917_VDDCX_AO +#define MSM8937_VDDCX_VFL MSM8917_VDDCX_VFL +#define MSM8937_VDDMX MSM8917_VDDMX +#define MSM8937_VDDMX_AO MSM8917_VDDMX_AO + +/* QM215 Power Domain Indexes */ +#define QM215_VDDCX MSM8917_VDDCX +#define QM215_VDDCX_AO MSM8917_VDDCX_AO +#define QM215_VDDCX_VFL MSM8917_VDDCX_VFL +#define QM215_VDDMX MSM8917_VDDMX +#define QM215_VDDMX_AO MSM8917_VDDMX_AO + /* MSM8953 Power Domain Indexes */ #define MSM8953_VDDMD 0 #define MSM8953_VDDMD_AO 1 From d975a9a9d631da97d22af06a9c806a0530b0f90b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Sat, 14 Oct 2023 15:38:22 +0200 Subject: [PATCH 48/56] pmdomain: qcom: rpmpd: Add MSM8917 power domains MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MSM8917 uses the SMPA2 and LDOA3 regulators provided by the PM8937 PMIC for the VDDCX and VDDMX power domains in voltage level mode, respectively. These definitions should also work on MSM8937. Signed-off-by: Otto Pflüger Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231014133823.14088-3-otto.pflueger@abscue.de Signed-off-by: Ulf Hansson --- drivers/pmdomain/qcom/rpmpd.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 524631dcab4b2..ae71f78243e1e 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -257,6 +257,24 @@ static struct rpmpd mx_l3a_corner_ao = { .key = KEY_CORNER, }; +static struct rpmpd mx_l3a_lvl_ao; +static struct rpmpd mx_l3a_lvl = { + .pd = { .name = "mx", }, + .peer = &mx_l3a_lvl_ao, + .res_type = RPMPD_LDOA, + .res_id = 3, + .key = KEY_LEVEL, +}; + +static struct rpmpd mx_l3a_lvl_ao = { + .pd = { .name = "mx_ao", }, + .peer = &mx_l3a_lvl, + .active_only = true, + .res_type = RPMPD_LDOA, + .res_id = 3, + .key = KEY_LEVEL, +}; + static struct rpmpd mx_l12a_lvl_ao; static struct rpmpd mx_l12a_lvl = { .pd = { .name = "mx", }, @@ -572,6 +590,20 @@ static const struct rpmpd_desc msm8916_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; +static struct rpmpd *msm8917_rpmpds[] = { + [MSM8917_VDDCX] = &cx_s2a_lvl, + [MSM8917_VDDCX_AO] = &cx_s2a_lvl_ao, + [MSM8917_VDDCX_VFL] = &cx_s2a_vfl, + [MSM8917_VDDMX] = &mx_l3a_lvl, + [MSM8917_VDDMX_AO] = &mx_l3a_lvl_ao, +}; + +static const struct rpmpd_desc msm8917_desc = { + .rpmpds = msm8917_rpmpds, + .num_pds = ARRAY_SIZE(msm8917_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO, +}; + static struct rpmpd *msm8953_rpmpds[] = { [MSM8953_VDDMD] = &md_s1a_lvl, [MSM8953_VDDMD_AO] = &md_s1a_lvl_ao, @@ -764,6 +796,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc }, { .compatible = "qcom,msm8909-rpmpd", .data = &msm8916_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, + { .compatible = "qcom,msm8917-rpmpd", .data = &msm8917_desc }, { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, { .compatible = "qcom,msm8953-rpmpd", .data = &msm8953_desc }, { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, From fad5bf2e2c900232277288460b7a91b147954aab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Sat, 14 Oct 2023 15:38:23 +0200 Subject: [PATCH 49/56] pmdomain: qcom: rpmpd: Add QM215 power domains MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QM215 is typically paired with a PM8916 PMIC and uses its SMPA1 and LDOA2 regulators in voltage level mode for VDDCX and VDDMX, respectively. Signed-off-by: Otto Pflüger Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231014133823.14088-4-otto.pflueger@abscue.de Signed-off-by: Ulf Hansson --- drivers/pmdomain/qcom/rpmpd.c | 58 +++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index ae71f78243e1e..07590a3ef19c2 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -105,6 +105,24 @@ static struct rpmpd cx_s1a_corner_ao = { .key = KEY_CORNER, }; +static struct rpmpd cx_s1a_lvl_ao; +static struct rpmpd cx_s1a_lvl = { + .pd = { .name = "cx", }, + .peer = &cx_s1a_lvl_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_LEVEL, +}; + +static struct rpmpd cx_s1a_lvl_ao = { + .pd = { .name = "cx_ao", }, + .peer = &cx_s1a_lvl, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_LEVEL, +}; + static struct rpmpd cx_s2a_corner_ao; static struct rpmpd cx_s2a_corner = { .pd = { .name = "cx", }, @@ -180,6 +198,13 @@ static struct rpmpd cx_s1a_vfc = { .key = KEY_FLOOR_CORNER, }; +static struct rpmpd cx_s1a_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_FLOOR_LEVEL, +}; + static struct rpmpd cx_s2a_vfc = { .pd = { .name = "cx_vfc", }, .res_type = RPMPD_SMPA, @@ -239,6 +264,24 @@ static struct rpmpd gx_rwgx0_lvl_ao = { }; /* MX */ +static struct rpmpd mx_l2a_lvl_ao; +static struct rpmpd mx_l2a_lvl = { + .pd = { .name = "mx", }, + .peer = &mx_l2a_lvl_ao, + .res_type = RPMPD_LDOA, + .res_id = 2, + .key = KEY_LEVEL, +}; + +static struct rpmpd mx_l2a_lvl_ao = { + .pd = { .name = "mx_ao", }, + .peer = &mx_l2a_lvl, + .active_only = true, + .res_type = RPMPD_LDOA, + .res_id = 2, + .key = KEY_LEVEL, +}; + static struct rpmpd mx_l3a_corner_ao; static struct rpmpd mx_l3a_corner = { .pd = { .name = "mx", }, @@ -704,6 +747,20 @@ static const struct rpmpd_desc qcs404_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; +static struct rpmpd *qm215_rpmpds[] = { + [QM215_VDDCX] = &cx_s1a_lvl, + [QM215_VDDCX_AO] = &cx_s1a_lvl_ao, + [QM215_VDDCX_VFL] = &cx_s1a_vfl, + [QM215_VDDMX] = &mx_l2a_lvl, + [QM215_VDDMX_AO] = &mx_l2a_lvl_ao, +}; + +static const struct rpmpd_desc qm215_desc = { + .rpmpds = qm215_rpmpds, + .num_pds = ARRAY_SIZE(qm215_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO, +}; + static struct rpmpd *sdm660_rpmpds[] = { [SDM660_VDDCX] = &cx_rwcx0_lvl, [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -805,6 +862,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc }, { .compatible = "qcom,qcm2290-rpmpd", .data = &qcm2290_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, + { .compatible = "qcom,qm215-rpmpd", .data = &qm215_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, { .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc }, From 374de39d38f97b0e58cfee88da590b2d056ccf7f Mon Sep 17 00:00:00 2001 From: Pengfei Li Date: Sat, 21 Oct 2023 02:59:49 +0800 Subject: [PATCH 50/56] pmdomain: imx: Make imx pgc power domain also set the fwnode Currently, The imx pgc power domain doesn't set the fwnode pointer, which results in supply regulator device can't get consumer imx pgc power domain device from fwnode when creating a link. This causes the driver core to instead try to create a link between the parent gpc device of imx pgc power domain device and supply regulator device. However, at this point, the gpc device has already been bound, and the link creation will fail. So adding the fwnode pointer to the imx pgc power domain device will fix this issue. Signed-off-by: Pengfei Li Tested-by: Emil Kronborg Fixes: 3fb16866b51d ("driver core: fw_devlink: Make cycle detection more robust") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231020185949.537083-1-pengfei.li_1@nxp.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/imx/gpc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pmdomain/imx/gpc.c b/drivers/pmdomain/imx/gpc.c index 90a8b2c0676ff..419ed15cc10c4 100644 --- a/drivers/pmdomain/imx/gpc.c +++ b/drivers/pmdomain/imx/gpc.c @@ -498,6 +498,7 @@ static int imx_gpc_probe(struct platform_device *pdev) pd_pdev->dev.parent = &pdev->dev; pd_pdev->dev.of_node = np; + pd_pdev->dev.fwnode = of_fwnode_handle(np); ret = platform_device_add(pd_pdev); if (ret) { From d4d56c079ddd19293b11de1f2309add0b8972af2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 25 Oct 2023 09:32:02 +0200 Subject: [PATCH 51/56] dt-bindings: power: qcom,rpmpd: document the SM8650 RPMh Power Domains Document the RPMh Power Domains on the SM8650 Platform. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-rpmpd-v1-1-f25d313104c6@linaro.org Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom,rpmhpd.h | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index d38c762e12804..2803f7d568217 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -55,6 +55,7 @@ properties: - qcom,sm8350-rpmhpd - qcom,sm8450-rpmhpd - qcom,sm8550-rpmhpd + - qcom,sm8650-rpmhpd - items: - enum: - qcom,msm8937-rpmpd diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h index 7c201a66bc691..0f6a74e099701 100644 --- a/include/dt-bindings/power/qcom,rpmhpd.h +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -26,5 +26,6 @@ #define RPMHPD_QPHY 16 #define RPMHPD_DDR 17 #define RPMHPD_XO 18 +#define RPMHPD_NSP2 19 #endif From 7eb31ec5e1cdb4705450e4d728407767cae2b919 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 25 Oct 2023 19:29:41 +0530 Subject: [PATCH 52/56] dt-bindings: power: qcom,rpmhpd: Add GMXC PD index Document GMXC (Graphics MXC) power domain index which will be used on SC8380XP SoCs. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20231025135943.13854-2-quic_sibis@quicinc.com [Ulf: Re-based to step up the index number] Signed-off-by: Ulf Hansson --- include/dt-bindings/power/qcom,rpmhpd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h index 0f6a74e099701..e54ffa3614515 100644 --- a/include/dt-bindings/power/qcom,rpmhpd.h +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -27,5 +27,6 @@ #define RPMHPD_DDR 17 #define RPMHPD_XO 18 #define RPMHPD_NSP2 19 +#define RPMHPD_GMXC 20 #endif From c638b9516abd60aebccdbded5041a3e9d1c519f3 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 25 Oct 2023 19:29:42 +0530 Subject: [PATCH 53/56] dt-bindings: power: rpmpd: Add SC8380XP support Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SC8380XP platform. Signed-off-by: Abel Vesa Signed-off-by: Rajendra Nayak Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20231025135943.13854-3-quic_sibis@quicinc.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 2803f7d568217..da9c5846f4e11 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -39,6 +39,7 @@ properties: - qcom,sc7280-rpmhpd - qcom,sc8180x-rpmhpd - qcom,sc8280xp-rpmhpd + - qcom,sc8380xp-rpmhpd - qcom,sdm660-rpmpd - qcom,sdm670-rpmhpd - qcom,sdm845-rpmhpd From 9c82c9005cb0ca14ed8885bab27d81894ba184d9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 25 Oct 2023 09:32:03 +0200 Subject: [PATCH 54/56] pmdomain: qcom: rpmhpd: Add SM8650 RPMh Power Domains Add RPMh Power Domains support for the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-rpmpd-v1-2-f25d313104c6@linaro.org Signed-off-by: Ulf Hansson --- drivers/pmdomain/qcom/rpmhpd.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index a631fe1f9a068..cf25ba1cac669 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -197,6 +197,11 @@ static struct rpmhpd nsp1 = { .res_name = "nsp1.lvl", }; +static struct rpmhpd nsp2 = { + .pd = { .name = "nsp2", }, + .res_name = "nsp2.lvl", +}; + static struct rpmhpd qphy = { .pd = { .name = "qphy", }, .res_name = "qphy.lvl", @@ -475,6 +480,30 @@ static const struct rpmhpd_desc sm8550_desc = { .num_pds = ARRAY_SIZE(sm8550_rpmhpds), }; +/* SM8650 RPMH powerdomains */ +static struct rpmhpd *sm8650_rpmhpds[] = { + [RPMHPD_CX] = &cx, + [RPMHPD_CX_AO] = &cx_ao, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MMCX] = &mmcx_w_cx_parent, + [RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent, + [RPMHPD_MSS] = &mss, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_MXC] = &mxc, + [RPMHPD_MXC_AO] = &mxc_ao, + [RPMHPD_NSP] = &nsp, + [RPMHPD_NSP2] = &nsp2, +}; + +static const struct rpmhpd_desc sm8650_desc = { + .rpmhpds = sm8650_rpmhpds, + .num_pds = ARRAY_SIZE(sm8650_rpmhpds), +}; + /* QDU1000/QRU1000 RPMH powerdomains */ static struct rpmhpd *qdu1000_rpmhpds[] = { [QDU1000_CX] = &cx, @@ -585,6 +614,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc }, { .compatible = "qcom,sm8450-rpmhpd", .data = &sm8450_desc }, { .compatible = "qcom,sm8550-rpmhpd", .data = &sm8550_desc }, + { .compatible = "qcom,sm8650-rpmhpd", .data = &sm8650_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmhpd_match_table); From 2050c9bc4f7bbdd7d1dc0b6bf7749ec4f7b6f407 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 25 Oct 2023 19:29:43 +0530 Subject: [PATCH 55/56] pmdomain: qcom: rpmhpd: Add SC8380XP power domains Add the power domains exposed by RPMH in the Qualcomm SC8380XP platform. Signed-off-by: Abel Vesa Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231025135943.13854-4-quic_sibis@quicinc.com Signed-off-by: Ulf Hansson --- drivers/pmdomain/qcom/rpmhpd.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index cf25ba1cac669..f2e64324deb84 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -207,6 +207,11 @@ static struct rpmhpd qphy = { .res_name = "qphy.lvl", }; +static struct rpmhpd gmxc = { + .pd = { .name = "gmxc", }, + .res_name = "gmxc.lvl", +}; + /* SA8540P RPMH powerdomains */ static struct rpmhpd *sa8540p_rpmhpds[] = { [SC8280XP_CX] = &cx, @@ -593,6 +598,28 @@ static const struct rpmhpd_desc sc8280xp_desc = { .num_pds = ARRAY_SIZE(sc8280xp_rpmhpds), }; +/* SC8380xp RPMH powerdomains */ +static struct rpmhpd *sc8380xp_rpmhpds[] = { + [RPMHPD_CX] = &cx, + [RPMHPD_CX_AO] = &cx_ao, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MMCX] = &mmcx, + [RPMHPD_MMCX_AO] = &mmcx_ao, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_NSP] = &nsp, + [RPMHPD_MXC] = &mxc, + [RPMHPD_GMXC] = &gmxc, +}; + +static const struct rpmhpd_desc sc8380xp_desc = { + .rpmhpds = sc8380xp_rpmhpds, + .num_pds = ARRAY_SIZE(sc8380xp_rpmhpds), +}; + static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc }, { .compatible = "qcom,sa8155p-rpmhpd", .data = &sa8155p_desc }, @@ -602,6 +629,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc }, { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, { .compatible = "qcom,sc8280xp-rpmhpd", .data = &sc8280xp_desc }, + { .compatible = "qcom,sc8380xp-rpmhpd", .data = &sc8380xp_desc }, { .compatible = "qcom,sdm670-rpmhpd", .data = &sdm670_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, From b131329b9bfbd1b4c0c5e088cb0c6ec03a12930f Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Mon, 16 Oct 2023 10:02:04 +0200 Subject: [PATCH 56/56] pmdomain: amlogic: Fix mask for the second NNA mem PD domain Without this change, the NPU hangs when the 8th NN core is used. It matches what the out-of-tree driver does. Signed-off-by: Tomeu Vizoso Fixes: 9a217b7e8953 ("soc: amlogic: meson-pwrc: Add NNA power domain for A311D") Acked-by: Neil Armstrong Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231016080205.41982-2-tomeu@tomeuvizoso.net Signed-off-by: Ulf Hansson --- drivers/pmdomain/amlogic/meson-ee-pwrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pmdomain/amlogic/meson-ee-pwrc.c b/drivers/pmdomain/amlogic/meson-ee-pwrc.c index cfb796d40d9d2..0dd71cd814c52 100644 --- a/drivers/pmdomain/amlogic/meson-ee-pwrc.c +++ b/drivers/pmdomain/amlogic/meson-ee-pwrc.c @@ -228,7 +228,7 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, - { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) }, + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) }, }; #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \