From e9a4c7f667ed16a95da0e9d68cc88b381dcd99f9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 23 Mar 2022 11:50:06 +0300 Subject: [PATCH 1/3] clk: qcom: regmap-mux: add pipe clk implementation On recent Qualcomm platforms the QMP PIPE clocks feed into a set of muxes which must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. However the same code sequence should be applied in the pcie-qcom endpoint, USB3 and UFS drivers. Rather than copying this sequence over and over again, follow the example of clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations. As we are changing the parent behind the back of the clock framework, also implement custom set_parent() and get_parent() operations behaving accroding to the clock framework expectations (cache the new parent if the clock is in disabled state, return cached parent). Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323085010.1753493-2-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/clk-regmap-mux.c | 78 +++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-regmap-mux.h | 3 ++ 2 files changed, 81 insertions(+) diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c index 45d9cca28064f..c39ee783ee832 100644 --- a/drivers/clk/qcom/clk-regmap-mux.c +++ b/drivers/clk/qcom/clk-regmap-mux.c @@ -49,9 +49,87 @@ static int mux_set_parent(struct clk_hw *hw, u8 index) return regmap_update_bits(clkr->regmap, mux->reg, mask, val); } +static u8 mux_safe_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + unsigned int val; + + if (clk_hw_is_enabled(hw)) + return mux_get_parent(hw); + + val = mux->stored_parent_cfg; + + if (mux->parent_map) + return qcom_find_cfg_index(hw, mux->parent_map, val); + + return val; +} + +static int mux_safe_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + + if (clk_hw_is_enabled(hw)) + return mux_set_parent(hw, index); + + if (mux->parent_map) + index = mux->parent_map[index].cfg; + + mux->stored_parent_cfg = index; + + return 0; +} + +static void mux_safe_disable(struct clk_hw *hw) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + struct clk_regmap *clkr = to_clk_regmap(hw); + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + unsigned int val; + + regmap_read(clkr->regmap, mux->reg, &val); + + mux->stored_parent_cfg = (val & mask) >> mux->shift; + + val = mux->safe_src_parent; + if (mux->parent_map) { + int index = qcom_find_src_index(hw, mux->parent_map, val); + + if (WARN_ON(index < 0)) + return; + + val = mux->parent_map[index].cfg; + } + val <<= mux->shift; + + regmap_update_bits(clkr->regmap, mux->reg, mask, val); +} + +static int mux_safe_enable(struct clk_hw *hw) +{ + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); + struct clk_regmap *clkr = to_clk_regmap(hw); + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + unsigned int val; + + val = mux->stored_parent_cfg; + val <<= mux->shift; + + return regmap_update_bits(clkr->regmap, mux->reg, mask, val); +} + const struct clk_ops clk_regmap_mux_closest_ops = { .get_parent = mux_get_parent, .set_parent = mux_set_parent, .determine_rate = __clk_mux_determine_rate_closest, }; EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops); + +const struct clk_ops clk_regmap_mux_safe_ops = { + .enable = mux_safe_enable, + .disable = mux_safe_disable, + .get_parent = mux_safe_get_parent, + .set_parent = mux_safe_set_parent, + .determine_rate = __clk_mux_determine_rate_closest, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops); diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h index db6f4cdd9586d..f86c674ce1393 100644 --- a/drivers/clk/qcom/clk-regmap-mux.h +++ b/drivers/clk/qcom/clk-regmap-mux.h @@ -14,10 +14,13 @@ struct clk_regmap_mux { u32 reg; u32 shift; u32 width; + u8 safe_src_parent; + u8 stored_parent_cfg; const struct parent_map *parent_map; struct clk_regmap clkr; }; extern const struct clk_ops clk_regmap_mux_closest_ops; +extern const struct clk_ops clk_regmap_mux_safe_ops; #endif From fa5ad5c51706e5407a3bb56c9542a63c81e35a2f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 23 Mar 2022 11:50:07 +0300 Subject: [PATCH 2/3] clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323085010.1753493-3-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-sm8450.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff0..fb6decd3df498 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -243,13 +243,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, .shift = 0, .width = 2, + .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; @@ -273,13 +274,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, .shift = 0, .width = 2, + .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; From a9ed9e2bf7940353d2ffa4faa2ad2b75a24f3ac0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 23 Mar 2022 11:50:08 +0300 Subject: [PATCH 3/3] clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let the clock framework automatically park the clock when the clock is switched off and restore the parent when the clock is switched on. Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323085010.1753493-4-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-sc7280.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 423627d49719c..dafbbc8f3bf42 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -373,13 +373,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x6b054, .shift = 0, .width = 2, + .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; @@ -388,13 +389,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x8d054, .shift = 0, .width = 2, + .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, };