From d24cd78399a3625a69887c8124638260c1c37a2b Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Tue, 12 Aug 2014 16:37:57 +0200 Subject: [PATCH 1/9] ARM: at91: sama5d3: add usart dma configurations Add the DMA configuration for USARTs mainly because it is not obvious to add the FIFO flag which is needed for rx. Signed-off-by: Ludovic Desroches Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 7702a0d120cb9..70a941fb1c90e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -177,6 +177,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; clocks = <&usart0_clk>; @@ -188,6 +191,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; clocks = <&usart1_clk>; @@ -333,6 +339,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; clocks = <&usart2_clk>; @@ -344,6 +353,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; clocks = <&usart3_clk>; @@ -412,6 +424,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; clocks = <&dbgu_clk>; From fe855dbfd3fde8fd3093e51992904e3c875a4a02 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 18 Sep 2014 14:56:43 +0200 Subject: [PATCH 2/9] ARM: at91: sama5d3xek: reserve dma channel for audio We set the DMA configuration on USARTs in the SoC DT in (ARM: at91: sama5d3: add usart dma configurations). As the audio must work with DMA channels, we reserve some dma channels for audio, or else audio won't work. Signed-off-by: Bo Shen [nicolas.ferre@atmel.com: move to the sama5d3xmb.dtsi to cover all board variants] Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xmb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index b8c6f20e780c9..49c10d33df302 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -25,6 +25,8 @@ }; spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + m25p80@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; @@ -51,6 +53,7 @@ }; usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; status = "okay"; @@ -132,6 +135,7 @@ }; dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ status = "okay"; }; From 496d3c2898cedf66530e057e68b54ffe5055154c Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 11 Jun 2014 18:14:41 +0800 Subject: [PATCH 3/9] ARM: at91/dt: at91sam9rl: switch ssc compatible string As the SSC integrate in at91sam9rl support frame sync length extension, so switch compatible string to support this feature. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index ab56c8b81dfa2..f0b4352650ed1 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -204,7 +204,7 @@ }; ssc0: ssc@fffc0000 { - compatible = "atmel,at91rm9200-ssc"; + compatible = "atmel,at91sam9rl-ssc"; reg = <0xfffc0000 0x4000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; @@ -213,7 +213,7 @@ }; ssc1: ssc@fffc4000 { - compatible = "atmel,at91rm9200-ssc"; + compatible = "atmel,at91sam9rl-ssc"; reg = <0xfffc4000 0x4000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; From 9bd277300fd81d69c335fc6a48d1b802dac4c7c3 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 11 Jun 2014 18:14:42 +0800 Subject: [PATCH 4/9] ARM: at91/dt: at91sam9g20: switch ssc compatible string As the SSC integrate in at91sam9g20 support frame sync length extension, so switch compatible string to support this feature. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g20.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 31f7652612fc8..5734dc18d7e19 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -22,6 +22,10 @@ compatible = "atmel,at91sam9g20-i2c"; }; + ssc0: ssc@fffbc000 { + compatible = "atmel,at91sam9rl-ssc"; + }; + adc0: adc@fffe0000 { atmel,adc-startup-time = <40>; }; From 0a51d644c20f5c88fd3a659119d1903f74927082 Mon Sep 17 00:00:00 2001 From: David Dueck Date: Wed, 17 Sep 2014 10:33:32 +0200 Subject: [PATCH 5/9] ARM: at91/dt: Fix typo regarding can0_clk Otherwise the clock for can0 will never get enabled. Signed-off-by: David Dueck Signed-off-by: Anthony Harivel Acked-by: Boris Brezillon Cc: stable@vger.kernel.org # v3.14 Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3_can.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index a0775851cce56..eaf41451ad0cf 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -40,7 +40,7 @@ atmel,clk-output-range = <0 66000000>; }; - can1_clk: can0_clk { + can1_clk: can1_clk { #clock-cells = <0>; reg = <41>; atmel,clk-output-range = <0 66000000>; From 97735da4e3fc2cad464994f615b0d2211f132497 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 9 Sep 2014 12:14:20 +0200 Subject: [PATCH 6/9] ARM: at91/dt: declare sckc node on at91sam9g45 Declare the SCKC (Slow Clock Configuration) block and its clks. Make use of the clk32k clk instead of slow_osc where appropriate. Signed-off-by: Boris BREZILLON Acked-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 857fd3e0b8a0d..6d3d68e0d72d1 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -165,7 +165,7 @@ compatible = "atmel,at91rm9200-clk-master"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; atmel,clk-output-range = <0 133333333>; atmel,clk-divisors = <1 2 4 3>; }; @@ -181,7 +181,7 @@ #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; prog0: prog0 { #clock-cells = <0>; @@ -1165,6 +1165,32 @@ atmel,can-isoc; }; }; + + sckc@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <1200000>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <75>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; }; fb0: fb@0x00500000 { From 8a85ba2075a5fde3bc4c69c3f972f5144522453c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 16 Sep 2014 10:43:57 +0200 Subject: [PATCH 7/9] ARM: at91/dt: sama5d3: add the nfc clock The atmel_nand driver is now able to handle the nfc clock, add it to sama5d3. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 70a941fb1c90e..277541b99eb2e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1020,6 +1020,11 @@ reg = <2>; }; + hsmc_clk: hsmc_clk { + #clock-cells = <0>; + reg = <5>; + }; + pioA_clk: pioA_clk { #clock-cells = <0>; reg = <6>; @@ -1420,6 +1425,7 @@ 0xffffc000 0x00000070 /* NFC HSMC regs */ 0x00200000 0x00100000 /* NFC SRAM banks */ >; + clocks = <&hsmc_clk>; }; }; }; From e0065cf719a9d84a05c9722d149c9ce8f0508a36 Mon Sep 17 00:00:00 2001 From: Marek Roszko Date: Sat, 23 Aug 2014 23:12:05 -0400 Subject: [PATCH 8/9] ARM: at91/dt: sama5d3: use new pinctrl compatible string This switches the SAMA5D3 to use the new atmel,sama5d3-pinctrl id that was added with the drive strength options patch. Signed-off-by: Marek Roszko Acked-by: Linus Walleij [nicolas.ferre@atmel.com: second compatible string kept as at91sam9x5] Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 277541b99eb2e..5f4144d1e3a1e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -445,7 +445,7 @@ pinctrl@fffff200 { #address-cells = <1>; #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; atmel,mux-mask = < /* A B C */ From 4dd7933ad606af457bc85b1afdaaac68aa993abf Mon Sep 17 00:00:00 2001 From: Erik van Luijk Date: Tue, 2 Sep 2014 12:52:12 +0200 Subject: [PATCH 9/9] ARM: at91/dt: at91sam9m10g45ek add rtc node Add rtc node to both the at91sam9g45 SoC family and the at91sam9m10g45ek board. Signed-off-by: Erik van Luijk Acked-by: Boris Brezillon Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 7 +++++++ arch/arm/boot/dts/at91sam9m10g45ek.dts | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 6d3d68e0d72d1..d3f65130a1f8b 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1191,6 +1191,13 @@ clocks = <&slow_rc_osc &slow_osc>; }; }; + + rtc@fffffdb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffdb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; }; fb0: fb@0x00500000 { diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 96ccc7de4f0a1..d8dd226510907 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -160,6 +160,10 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_leds>; }; + + rtc@fffffdb0 { + status = "okay"; + }; }; fb0: fb@0x00500000 {