From a8fdb80f4d477a71a98cb069f4d5a42f41bbbe9c Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Thu, 21 Nov 2019 14:21:14 +0530 Subject: [PATCH 01/21] arm64: zynqmp: Add ZynqMP SDHCI compatible string Add the new compatible string for ZynqMP SD Host Controller for its use in the Arasan SDHCI driver for some of the ZynqMP specific operations. Add required properties for the same. Signed-off-by: Manish Narani Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 3c731e73903ab..a49b669395383 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -522,21 +522,25 @@ }; sdhci0: mmc@ff160000 { - compatible = "arasan,sdhci-8.9a"; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@ff170000 { - compatible = "arasan,sdhci-8.9a"; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; smmu: smmu@fd800000 { From a6764cbda6c64b76a3f7511c099fc1a0accca5b0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 8 Nov 2019 19:30:32 +0200 Subject: [PATCH 02/21] arm64: dts: zynqmp: Use decimal values for drm-clock properties The #clock-cells and clock-accuracy properties are all expressed in decimal, except for the drm-clock. Fix it, as decimal is easier to read for those properties. Signed-off-by: Laurent Pinchart Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi index 306ad2157c988..d900fedf0bfcf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi @@ -66,9 +66,9 @@ drm_clock: drm-clock { compatible = "fixed-clock"; - #clock-cells = <0x0>; + #clock-cells = <0>; clock-frequency = <262750000>; - clock-accuracy = <0x64>; + clock-accuracy = <100>; }; }; From df906cf54bd54dbc87efb5129ce38e3ca9e7d329 Mon Sep 17 00:00:00 2001 From: Anurag Kumar Vulisha Date: Tue, 10 Sep 2019 15:17:22 +0000 Subject: [PATCH 03/21] arm64: zynqmp: Add dr_mode property to usb node This patch adds dr_mode property to the usb node for zynqmp boards. Signed-off-by: Anurag Kumar Vulisha Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 + 7 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 9a3e39d1294f1..386f7019d649b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -128,4 +128,5 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 2421ec71a201c..c6c8e2caff436 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -158,6 +158,7 @@ /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; + dr_mode = "host"; }; &uart0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index e5699d0d91e45..c64c7b84d8c7d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -274,11 +274,13 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "peripheral"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; + dr_mode = "host"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 2a3b66547c6d9..011f138644887 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -540,6 +540,7 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "host"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 8f456146409fc..7e372b1a5dac3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -189,6 +189,7 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "host"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 93ce7eb81498d..c4aac7ab2c52d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -514,6 +514,7 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "host"; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 8bb0001a026fc..4909533237ef1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -440,4 +440,5 @@ /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; + dr_mode = "host"; }; From 9c8a47b484ed8d7b06b4ca0032e93c458c7b931e Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Thu, 7 Nov 2019 01:44:14 -0800 Subject: [PATCH 04/21] arm64: dts: xilinx: Add the clock nodes for zynqmp Add clock nodes for zynqmp based on CCF. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +- .../boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +- .../boot/dts/xilinx/zynqmp-zc1275-revA.dts | 4 +- .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +- .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +- .../dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +- .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +- .../dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +- .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 18 +- 15 files changed, 265 insertions(+), 27 deletions(-) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi new file mode 100644 index 0000000000000..9868ca15dfc5d --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2017 - 2019, Xilinx, Inc. + * + * Michal Simek + */ + +#include +/ { + pss_ref_clk: pss_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + video_clk: video_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + pss_alt_ref_clk: pss_alt_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + gt_crx_ref_clk: gt_crx_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <108000000>; + }; + + aux_ref_clk: aux_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; +}; + +&can0 { + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&can1 { + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&cpu0 { + clocks = <&zynqmp_clk ACPU>; +}; + +&fpd_dma_chan1 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan2 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan3 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan4 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan5 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan6 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan7 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&fpd_dma_chan8 { + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan1 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan2 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan3 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan4 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan5 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan6 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan7 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&lpd_dma_chan8 { + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&gem0 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, + <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem1 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, + <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem2 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, + <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem3 { + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, + <&zynqmp_clk GEM_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gpio { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&i2c0 { + clocks = <&zynqmp_clk I2C0_REF>; +}; + +&i2c1 { + clocks = <&zynqmp_clk I2C1_REF>; +}; + +&pcie { + clocks = <&zynqmp_clk PCIE_REF>; +}; + +&sata { + clocks = <&zynqmp_clk SATA_REF>; +}; + +&sdhci0 { + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&sdhci1 { + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&spi0 { + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&spi1 { + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc0 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc1 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc2 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&ttc3 { + clocks = <&zynqmp_clk LPD_LSBUS>; +}; + +&uart0 { + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&uart1 { + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + +&usb0 { + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&watchdog0 { + clocks = <&zynqmp_clk WDT>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 0f7b4cf6078ed..2e05fa4169559 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1232 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP ZC1232 RevA"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 9092828f92ecd..3d0aaa02f184f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP ZC1254 RevA"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts index 4f404c580eec5..66a90483b0043 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZC1275 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2019, Xilinx, Inc. * * Michal Simek * Siva Durga Prasad Paladugu @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP ZC1275 RevA"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 386f7019d649b..3542d92735cb7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include / { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index c6c8e2caff436..e5d83a4aca071 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include / { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index 7a49deeae647b..3750690925adc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP zc1751-xm017-dc3 RevA"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 54c7b4f1d1e46..2366cd9f091af 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP zc1751-xm018-dc4"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index b8b5ff13818d3..9a894e6db6ba9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include / { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index c64c7b84d8c7d..dd60f7d85cc82 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2018, Xilinx, Inc. + * (C) Copyright 2016 - 2019, Xilinx, Inc. * * Michal Simek * Nathalie Chan King Choy @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include #include #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 011f138644887..d92f617f0b9dd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2018, Xilinx, Inc. + * (C) Copyright 2015 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 7e372b1a5dac3..cfb054e46723f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include / { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index c4aac7ab2c52d..ea2dcbe9effd0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 4909533237ef1..d656eb8b30401 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2018, Xilinx, Inc. + * (C) Copyright 2017 - 2019, Xilinx, Inc. * * Michal Simek */ @@ -10,7 +10,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a49b669395383..aa5ee6d470f1c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014 - 2019, Xilinx, Inc. * * Michal Simek * @@ -120,6 +120,22 @@ compatible = "xlnx,zynqmp-firmware"; method = "smc"; + zynqmp_clk: clock-controller { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, + <&video_clk>, + <&pss_alt_ref_clk>, + <&aux_ref_clk>, + <>_crx_ref_clk>; + clock-names = "pss_ref_clk", + "video_clk", + "pss_alt_ref_clk", + "aux_ref_clk", + "gt_crx_ref_clk"; + }; + nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; From 4406486805bffbf245473e6111e2d7984550846e Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Thu, 7 Nov 2019 01:44:15 -0800 Subject: [PATCH 05/21] arm64: dts: xilinx: Remove dtsi for fixed clock Currently CCF clocks sre used in zynqmp dts. So there is no use of dtsi for fixed clock. Remove dtsi for fixed clock. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 --------------------- 1 file changed, 213 deletions(-) delete mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi deleted file mode 100644 index d900fedf0bfcf..0000000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock specification for Xilinx ZynqMP - * - * (C) Copyright 2015 - 2018, Xilinx, Inc. - * - * Michal Simek - */ - -/ { - clk100: clk100 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - clk125: clk125 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk200: clk200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - clk250: clk250 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - clk300: clk300 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; - - clk600: clk600 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - }; - - dp_aclk: clock0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-accuracy = <100>; - }; - - dp_aud_clk: clock1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - clock-accuracy = <100>; - }; - - dpdma_clk: dpdma-clk { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <533000000>; - }; - - drm_clock: drm-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <262750000>; - clock-accuracy = <100>; - }; -}; - -&can0 { - clocks = <&clk100 &clk100>; -}; - -&can1 { - clocks = <&clk100 &clk100>; -}; - -&fpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&lpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&gem0 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem1 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem2 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gem3 { - clocks = <&clk125>, <&clk125>, <&clk125>; -}; - -&gpio { - clocks = <&clk100>; -}; - -&i2c0 { - clocks = <&clk100>; -}; - -&i2c1 { - clocks = <&clk100>; -}; - -&sata { - clocks = <&clk250>; -}; - -&sdhci0 { - clocks = <&clk200 &clk200>; -}; - -&sdhci1 { - clocks = <&clk200 &clk200>; -}; - -&spi0 { - clocks = <&clk200 &clk200>; -}; - -&spi1 { - clocks = <&clk200 &clk200>; -}; - -&uart0 { - clocks = <&clk100 &clk100>; -}; - -&uart1 { - clocks = <&clk100 &clk100>; -}; - -&usb0 { - clocks = <&clk250>, <&clk250>; -}; - -&usb1 { - clocks = <&clk250>, <&clk250>; -}; - -&watchdog0 { - clocks = <&clk250>; -}; From 959b86ae37c672f6f6551f2ce1517668c791ba44 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Thu, 7 Nov 2019 01:44:16 -0800 Subject: [PATCH 06/21] arm64: dts: xilinx: Add the power nodes for zynqmp Add power domain nodes for zynqmp. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index aa5ee6d470f1c..26d926eb14313 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -12,6 +12,8 @@ * the License, or (at your option) any later version. */ +#include + / { compatible = "xlnx,zynqmp"; #address-cells = <2>; @@ -118,8 +120,15 @@ firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; + #power-domain-cells = <1>; method = "smc"; + zynqmp_power: zynqmp-power { + compatible = "xlnx,zynqmp-power"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + }; + zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; @@ -203,6 +212,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { @@ -214,6 +224,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { @@ -244,6 +255,7 @@ interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { @@ -254,6 +266,7 @@ interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { @@ -264,6 +277,7 @@ interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { @@ -274,6 +288,7 @@ interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { @@ -284,6 +299,7 @@ interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { @@ -294,6 +310,7 @@ interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { @@ -304,6 +321,7 @@ interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { @@ -314,6 +332,7 @@ interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; /* LPDDMA default allows only secured access. inorder to enable @@ -328,6 +347,7 @@ interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { @@ -338,6 +358,7 @@ interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { @@ -348,6 +369,7 @@ interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { @@ -358,6 +380,7 @@ interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { @@ -368,6 +391,7 @@ interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { @@ -378,6 +402,7 @@ interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { @@ -388,6 +413,7 @@ interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { @@ -398,6 +424,7 @@ interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { @@ -416,6 +443,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { @@ -427,6 +455,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { @@ -438,6 +467,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { @@ -449,6 +479,7 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { @@ -461,6 +492,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; + power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { @@ -471,6 +503,7 @@ reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { @@ -481,6 +514,7 @@ reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_I2C_1>; }; pcie: pcie@fd0e0000 { @@ -512,6 +546,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -535,6 +570,7 @@ reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; + power-domains = <&zynqmp_firmware PD_SATA>; }; sdhci0: mmc@ff160000 { @@ -546,6 +582,7 @@ clock-names = "clk_xin", "clk_ahb"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; + power-domains = <&zynqmp_firmware PD_SD_0>; }; sdhci1: mmc@ff170000 { @@ -557,6 +594,7 @@ clock-names = "clk_xin", "clk_ahb"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; + power-domains = <&zynqmp_firmware PD_SD_1>; }; smmu: smmu@fd800000 { @@ -581,6 +619,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { @@ -592,6 +631,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { @@ -601,6 +641,7 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { @@ -610,6 +651,7 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { @@ -619,6 +661,7 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { @@ -628,6 +671,7 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; + power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { @@ -637,6 +681,7 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { @@ -646,6 +691,7 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; + power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb@fe200000 { @@ -655,6 +701,7 @@ interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; + power-domains = <&zynqmp_firmware PD_USB_0>; }; usb1: usb@fe300000 { @@ -664,6 +711,7 @@ interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; + power-domains = <&zynqmp_firmware PD_USB_1>; }; watchdog0: watchdog@fd4d0000 { From 13d21eba781ea2a4de6aab02abd2beb84e753f8a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 Aug 2019 12:44:22 +0200 Subject: [PATCH 07/21] arm64: zynqmp: Use ethernet-phy as node name for ethernet phys Ethernet phys based on devicetree specification should be using ethernet-phy@ node name instead of pure phy@. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 3542d92735cb7..69f6e46107393 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -73,7 +73,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index e5d83a4aca071..b75235ae7d302 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -84,7 +84,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@5 { + phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index 3750690925adc..4ea6ef5a7f2b7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -73,7 +73,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0 { /* VSC8211 */ + phy0: ethernet-phy@0 { /* VSC8211 */ reg = <0>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index 9a894e6db6ba9..41934e3525c6d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -74,7 +74,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index d92f617f0b9dd..7c6b538490f80 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -105,7 +105,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@21 { + phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index 1780ed237daf2..d9ad8a4b20d35 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -16,7 +16,7 @@ &gem3 { phy-handle = <&phyc>; - phyc: phy@c { + phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; @@ -24,7 +24,7 @@ ti,dp83867-rxctrl-strap-quirk; }; /* Cleanup from RevA */ - /delete-node/ phy@21; + /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index cfb054e46723f..2d71b4431cceb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -50,7 +50,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index ea2dcbe9effd0..ae62fe4287c25 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -106,7 +106,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d656eb8b30401..b3c29947d6b33 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -101,7 +101,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@c { + phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; From 4b0ec30be98cf583f3d3616a14973537a7a28b93 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 30 May 2018 08:34:29 +0200 Subject: [PATCH 08/21] arm64: zynqmp: Remove addition number in node name This change is coming from mainline review that's why this patch is sync. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index b75235ae7d302..4a86efa32d687 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -123,7 +123,7 @@ status = "okay"; num-cs = <1>; - spi0_flash0: flash0@0 { + spi0_flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; @@ -141,7 +141,7 @@ status = "okay"; num-cs = <1>; - spi1_flash0: flash0@0 { + spi1_flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; From 8cfb5a11e1799921adf3f17ba1831ac7208ec5e9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 9 Jan 2020 12:27:08 +0100 Subject: [PATCH 09/21] arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104 I2c address is not 0x21 but 0x20. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 2d71b4431cceb..7a4614e3f5fae 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -118,9 +118,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - tca6416_u97: gpio@21 { + tca6416_u97: gpio@20 { compatible = "ti,tca6416"; - reg = <0x21>; + reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* From 4426df7c8dc2eb9a1438418a3cbeeff41ef5c097 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Mar 2019 10:15:27 +0100 Subject: [PATCH 10/21] arm64: zynqmp: Turn comment to gpio-line-names Label gpio lines properly. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 43 ++++--------------- 1 file changed, 9 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7c6b538490f80..c96e8416fa7ef 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -125,21 +125,11 @@ tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; - gpio-controller; + gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - PS_GTR_LAN_SEL0 - * 1 - PS_GTR_LAN_SEL1 - * 2 - PS_GTR_LAN_SEL2 - * 3 - PS_GTR_LAN_SEL3 - * 4 - PCI_CLK_DIR_SEL - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 7, 10 - 17 - not connected - */ - + gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", + "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", + "", "", "", "", "", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; @@ -169,27 +159,12 @@ tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; - gpio-controller; + gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - VCCPSPLL_EN - * 1 - MGTRAVCC_EN - * 2 - MGTRAVTT_EN - * 3 - VCCPSDDRPLL_EN - * 4 - MIO26_PMU_INPUT_LS - * 5 - PL_PMBUS_ALERT - * 6 - PS_PMBUS_ALERT - * 7 - MAXIM_PMBUS_ALERT - * 10 - PL_DDR4_VTERM_EN - * 11 - PL_DDR4_VPP_2V5_EN - * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON - * 13 - PS_DIMM_SUSPEND_EN - * 14 - PS_DDR4_VTERM_EN - * 15 - PS_DDR4_VPP_2V5_EN - * 16 - 17 - not connected - */ + gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", + "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", + "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", + "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ From 48b44b909073e6ac745849c1220f683f5ce91347 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jul 2018 12:10:02 +0200 Subject: [PATCH 11/21] arm64: zynqmp: Setup clock-output-names for si570 chips If there are more instances of si570 clock-output-names property should be used for differentiation of clock output. The patch is adding this optional properties for all zynqmp boards with si570 chip. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index c96e8416fa7ef..845671447f602 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -389,6 +389,7 @@ temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; + clock-output-names = "si570_user"; }; }; i2c@3 { @@ -402,6 +403,7 @@ temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; + clock-output-names = "si570_mgt"; }; }; i2c@4 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index ae62fe4287c25..822de6f04725f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -388,6 +388,7 @@ temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; + clock-output-names = "si570_user"; }; }; i2c@3 { @@ -401,6 +402,7 @@ temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; + clock-output-names = "si570_mgt"; }; }; i2c@4 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index b3c29947d6b33..022c732005ee4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -304,6 +304,7 @@ temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; + clock-output-names = "si570_user"; }; }; i2c@3 { @@ -317,6 +318,7 @@ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; + clock-output-names = "si570_mgt"; }; }; i2c@4 { From 25ef9bb6c221f80b56e97456847ed525d9e2a3a5 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 5 Sep 2019 08:30:38 +0530 Subject: [PATCH 12/21] arm64: zynqmp: Fix the si570 clock frequency on zcu111 The si570 clock frequency should be 156.25MHz as per datasheet. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 022c732005ee4..cb2e46833a7b5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -317,7 +317,7 @@ reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; From b4582390d5841c3f6817953553fa3ebf523edb91 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 28 May 2018 15:19:02 +0200 Subject: [PATCH 13/21] arm64: zynqmp: Remove broken-cd from zcu100-revC Card detect bit was broken on revA and it is working fine with revC board that's why this property can be removed. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index dd60f7d85cc82..2b3757dd74cca 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -226,7 +226,6 @@ &sdhci0 { status = "okay"; no-1-8-v; - broken-cd; /* CD has to be enabled by default */ disable-wp; }; From c8e75cd490771ebfcfda29b1be27730b114cb0e7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 31 May 2018 09:50:10 +0200 Subject: [PATCH 14/21] arm64: zynqmp: Setup default number of chipselects for zcu100 There is only one chipselect on each connector. Define it directly in board dts file. There should be an option to use more chipselects via gpios. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 2b3757dd74cca..a109e82982aee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -250,11 +250,13 @@ &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; + num-cs = <1>; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; + num-cs = <1>; }; &uart0 { From 526a63f00f109796832062c69eeed14fa03d0fcd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 26 Aug 2019 09:30:34 +0200 Subject: [PATCH 15/21] arm64: zynqmp: Enable iio-hwmon for ina226 on zcu100 ina226 hwmon driver is deprecated and it is recommended to use new iio based driver. The patch is enabling iio-hwmon driver to export functionality from IIO to hwmon interface to be able to use lm-sensors package. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index a109e82982aee..d60110ad83675 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -103,6 +103,11 @@ reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; + + ina226 { + compatible = "iio-hwmon"; + io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; + }; }; &dcc { @@ -191,8 +196,9 @@ #size-cells = <0>; reg = <5>; /* PS_PMBUS */ - ina226@40 { /* u35 */ + u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ From 2fe83978336c165122a350bac212a290ffb156e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 26 Aug 2019 09:45:03 +0200 Subject: [PATCH 16/21] arm64: zynqmp: Enable iio-hwmon for ina226 on zcu111 ina226 hwmon driver is deprecated and it is recommended to use new iio based driver. The patch is enabling iio-hwmon driver to export functionality from IIO to hwmon interface to be able to use lm-sensors package. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 99 ++++++++++++++++--- 1 file changed, 85 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index cb2e46833a7b5..df2bc5a41c8d5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -59,6 +59,63 @@ linux,default-trigger = "heartbeat"; }; }; + + ina226-u67 { + compatible = "iio-hwmon"; + io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; + }; + ina226-u59 { + compatible = "iio-hwmon"; + io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; + }; + ina226-u61 { + compatible = "iio-hwmon"; + io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; + }; + ina226-u60 { + compatible = "iio-hwmon"; + io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; + }; + ina226-u64 { + compatible = "iio-hwmon"; + io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; + }; + ina226-u69 { + compatible = "iio-hwmon"; + io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; + }; + ina226-u66 { + compatible = "iio-hwmon"; + io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u63 { + compatible = "iio-hwmon"; + io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; + }; + ina226-u3 { + compatible = "iio-hwmon"; + io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; + }; + ina226-u71 { + compatible = "iio-hwmon"; + io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; + }; + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; + }; + ina226-u73 { + compatible = "iio-hwmon"; + io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; }; &dcc { @@ -152,73 +209,87 @@ reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ - ina226@40 { /* u67 */ + u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <2000>; }; - ina226@41 { /* u59 */ + u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u61 */ + u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u60 */ + u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@45 { /* u64 */ + u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u69 */ + u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x46>; shunt-resistor = <2000>; }; - ina226@47 { /* u66 */ + u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x47>; shunt-resistor = <5000>; }; - ina226@48 { /* u65 */ + u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x48>; shunt-resistor = <5000>; }; - ina226@49 { /* u63 */ + u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x49>; shunt-resistor = <5000>; }; - ina226@4a { /* u3 */ + u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4a>; shunt-resistor = <5000>; }; - ina226@4b { /* u71 */ + u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4b>; shunt-resistor = <5000>; }; - ina226@4c { /* u77 */ + u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4c>; shunt-resistor = <5000>; }; - ina226@4d { /* u73 */ + u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4d>; shunt-resistor = <5000>; }; - ina226@4e { /* u79 */ + u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4e>; shunt-resistor = <5000>; }; From 9529be140ffa7b77b3c90ebbe2e73712ba812a7d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 26 Aug 2019 10:00:26 +0200 Subject: [PATCH 17/21] arm64: zynqmp: Add label property to all ina226 on zcu111 Label property is adding capability to distiguish chips from each other when iio framework is used. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index df2bc5a41c8d5..2e92634c77f90 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -212,84 +212,98 @@ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; From 86444d3ecfd5aeafdb5a356fa4f74fcfacbecad8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 16 Aug 2019 10:42:42 +0200 Subject: [PATCH 18/21] arm64: zynqmp: Enable iio-hwmon for ina226 on zcu102 ina226 hwmon driver is deprecated and it is recommended to use new iio based driver. The patch is enabling iio-hwmon driver to export functionality from IIO to hwmon interface to be able to use lm-sensors package. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 127 +++++++++++++++--- 1 file changed, 109 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 845671447f602..afdd0ff37900a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -59,6 +59,79 @@ linux,default-trigger = "heartbeat"; }; }; + + ina226-u76 { + compatible = "iio-hwmon"; + io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; + }; + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; + }; + ina226-u78 { + compatible = "iio-hwmon"; + io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; + }; + ina226-u87 { + compatible = "iio-hwmon"; + io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; + }; + ina226-u85 { + compatible = "iio-hwmon"; + io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; + }; + ina226-u86 { + compatible = "iio-hwmon"; + io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; + }; + ina226-u93 { + compatible = "iio-hwmon"; + io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; + }; + ina226-u88 { + compatible = "iio-hwmon"; + io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; + }; + ina226-u15 { + compatible = "iio-hwmon"; + io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; + }; + ina226-u92 { + compatible = "iio-hwmon"; + io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; + ina226-u81 { + compatible = "iio-hwmon"; + io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; + }; + ina226-u80 { + compatible = "iio-hwmon"; + io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; + }; + ina226-u84 { + compatible = "iio-hwmon"; + io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; + }; + ina226-u16 { + compatible = "iio-hwmon"; + io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u74 { + compatible = "iio-hwmon"; + io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; + }; + ina226-u75 { + compatible = "iio-hwmon"; + io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; + }; }; &can1 { @@ -177,53 +250,63 @@ #size-cells = <0>; reg = <0>; /* PS_PMBUS */ - ina226@40 { /* u76 */ + u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; - ina226@41 { /* u77 */ + u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u78 */ + u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u87 */ + u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u85 */ + u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u86 */ + u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u93 */ + u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u88 */ + u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x47>; shunt-resistor = <5000>; }; - ina226@4a { /* u15 */ + u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4a>; shunt-resistor = <5000>; }; - ina226@4b { /* u92 */ + u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4b>; shunt-resistor = <5000>; }; @@ -233,43 +316,51 @@ #size-cells = <0>; reg = <1>; /* PL_PMBUS */ - ina226@40 { /* u79 */ + u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <2000>; }; - ina226@41 { /* u81 */ + u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u80 */ + u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u84 */ + u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u16 */ + u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u65 */ + u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u74 */ + u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u75 */ + u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x47>; shunt-resistor = <5000>; }; From 353f5ece949d1bdaa63fe05f2e64ab38b790a0ca Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 26 Aug 2019 10:20:07 +0200 Subject: [PATCH 19/21] arm64: zynqmp: Add label property to all ina226 on zcu102 Label property is adding capability to distiguish chips from each other when iio framework is used. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index afdd0ff37900a..4f801721564fb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -253,60 +253,70 @@ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; @@ -319,48 +329,56 @@ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; From d7b13a3cf20eb6d7338cebef19c01eaf047c108d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 26 Aug 2019 09:46:36 +0200 Subject: [PATCH 20/21] arm64: zynqmp: Enable iio-hwmon for ina226 on zcu106 ina226 hwmon driver is deprecated and it is recommended to use new iio based driver. The patch is enabling iio-hwmon driver to export functionality from IIO to hwmon interface to be able to use lm-sensors package. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 127 +++++++++++++++--- 1 file changed, 109 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 822de6f04725f..d136ce1fb07e1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -59,6 +59,79 @@ linux,default-trigger = "heartbeat"; }; }; + + ina226-u76 { + compatible = "iio-hwmon"; + io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; + }; + ina226-u77 { + compatible = "iio-hwmon"; + io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; + }; + ina226-u78 { + compatible = "iio-hwmon"; + io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; + }; + ina226-u87 { + compatible = "iio-hwmon"; + io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; + }; + ina226-u85 { + compatible = "iio-hwmon"; + io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; + }; + ina226-u86 { + compatible = "iio-hwmon"; + io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; + }; + ina226-u93 { + compatible = "iio-hwmon"; + io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; + }; + ina226-u88 { + compatible = "iio-hwmon"; + io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; + }; + ina226-u15 { + compatible = "iio-hwmon"; + io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; + }; + ina226-u92 { + compatible = "iio-hwmon"; + io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; + }; + ina226-u79 { + compatible = "iio-hwmon"; + io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; + }; + ina226-u81 { + compatible = "iio-hwmon"; + io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; + }; + ina226-u80 { + compatible = "iio-hwmon"; + io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; + }; + ina226-u84 { + compatible = "iio-hwmon"; + io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; + }; + ina226-u16 { + compatible = "iio-hwmon"; + io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u74 { + compatible = "iio-hwmon"; + io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; + }; + ina226-u75 { + compatible = "iio-hwmon"; + io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; + }; }; &can1 { @@ -177,53 +250,63 @@ #size-cells = <0>; reg = <0>; /* PS_PMBUS */ - ina226@40 { /* u76 */ + u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; - ina226@41 { /* u77 */ + u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u78 */ + u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u87 */ + u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u85 */ + u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u86 */ + u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u93 */ + u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u88 */ + u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x47>; shunt-resistor = <5000>; }; - ina226@4a { /* u15 */ + u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4a>; shunt-resistor = <5000>; }; - ina226@4b { /* u92 */ + u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x4b>; shunt-resistor = <5000>; }; @@ -233,43 +316,51 @@ #size-cells = <0>; reg = <1>; /* PL_PMBUS */ - ina226@40 { /* u79 */ + u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <2000>; }; - ina226@41 { /* u81 */ + u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x41>; shunt-resistor = <5000>; }; - ina226@42 { /* u80 */ + u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x42>; shunt-resistor = <5000>; }; - ina226@43 { /* u84 */ + u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x43>; shunt-resistor = <5000>; }; - ina226@44 { /* u16 */ + u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x44>; shunt-resistor = <5000>; }; - ina226@45 { /* u65 */ + u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x45>; shunt-resistor = <5000>; }; - ina226@46 { /* u74 */ + u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x46>; shunt-resistor = <5000>; }; - ina226@47 { /* u75 */ + u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; + #io-channel-cells = <1>; reg = <0x47>; shunt-resistor = <5000>; }; From 5a25e646902f8bfd97379b0b385d93c93cb5b94e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 26 Aug 2019 10:18:13 +0200 Subject: [PATCH 21/21] arm64: zynqmp: Add label property to all ina226 on zcu106 Label property is adding capability to distiguish chips from each other when iio framework is used. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index d136ce1fb07e1..6e9efe2338388 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -253,60 +253,70 @@ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; @@ -319,48 +329,56 @@ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; + label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; };