From 4bab74b4ee9d07cb7f981ab92fcc2de1eec3fbe5 Mon Sep 17 00:00:00 2001 From: Penny Chiu Date: Thu, 22 Oct 2015 17:46:22 +0800 Subject: [PATCH] CHROMIUM: clk: tegra: dfll: fix logic for building lookup table The lookup table entries are fixed, and the voltages in these entries are distributed based on minimum and maximum voltages and each voltages in opp table. Since the last entry is reserved for maximum voltage, we found the voltage in the next to last entry is not accurate enough for the next to last frequency in some SKUs. This causes the DFLL driver cannot find a proper voltage index when CPUFreq driver set expected frequency as the next to last frequency. This patch fixes the original logic to force to use find_vdd_map_entry_exact() for the next to last frequency, this will make the selected voltage are more accurate. BUG=chrome-os-partner:46846 TEST=Boots on smaug, check if the kernel log and no below errors: [ 95.945181] tegra124-dfll 70110000.clock: dfll_calculate_rate_request: Rate 18446744073709551594 is above dfll range [ 96.178318] tegra124-dfll 70110000.clock: dfll_calculate_rate_request: Rate 4294967294 is above dfll range [ 96.187973] tegra-dvfs: rate 18446744073709551594 too high for dvfs on cclk_g Change-Id: I3a14a75fb15f9142323757579985cd49da5720bc Signed-off-by: Penny Chiu Reviewed-on: https://chromium-review.googlesource.com/308281 Commit-Ready: Andrew Bresticker Reviewed-by: Bill Huang Reviewed-by: Andrew Bresticker --- drivers/clk/tegra/clk-dfll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index f4db02dfbd3c9..8127551e7caee 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -2128,7 +2128,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td) for (;;) { v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j)); - if (v >= v_opp) + if ((v >= v_opp) || (j == MAX_DFLL_VOLTAGES - 2)) break; selector = find_vdd_map_entry_min(td, v);