From 7cf261dd1efc593942db913c98851feadec9d73e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 30 Nov 2012 15:19:59 +0000 Subject: [PATCH 01/70] ARM: ux500: Change IRQ from low-to-high edge triggered to high-to-low When the STMPE IRQ is triggered to be active high level-sensitive, the Nomadik GPIO controller it uses complains, although it still works. Recently we attempted to move triggering to low-to-high in an attempt to prevent the warning; however, this ensured that the IRQ was actually missed completely. Now we have a solution which both works and keeps the GPIO controller happy. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/stuib.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 39446a247e798..615392a756766 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi @@ -15,7 +15,7 @@ stmpe1601: stmpe1601@40 { compatible = "st,stmpe1601"; reg = <0x40>; - interrupts = <26 0x1>; + interrupts = <26 0x2>; interrupt-parent = <&gpio6>; interrupt-controller; From fa17f9f3ef818308c8a7ed537bd87bd504cfb1f7 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 31 Jan 2013 11:24:19 +0000 Subject: [PATCH 02/70] ARM: ux500: Include the PRCMU's Secure Registers in DB8500's DT Currently we only include the PRCMU's primary registers when referencing the register count in the 'reg' property. This patch expands that count to include the secure registers also. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 69140ba99f465..2ec1599a89a0c 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -191,7 +191,7 @@ prcmu: prcmu@80157000 { compatible = "stericsson,db8500-prcmu"; - reg = <0x80157000 0x1000>; + reg = <0x80157000 0x2000>; reg-names = "prcmu"; interrupts = <0 47 0x4>; #address-cells = <1>; From c28f800475fc326cb418592e92cdd8f2ff07c045 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Dec 2012 16:36:54 +0000 Subject: [PATCH 03/70] ARM: ux500: Provide a means to obtain the SMSC9115 clock when DT is enabled Device Tree names devices differently to how some frameworks expect them. Until we can move a platform over to the new way of obtaining resources, we have to use the OF_DEV_AUXDATA() macros to craft a device name which can be used in searches during allocation time. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu-db8500.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 19235cf7bbe3f..1c7f794ad7d19 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -282,6 +282,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", &db8500_prcmu_pdata), + OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL), /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE, "pinctrl-db8500", NULL), From 9ea49fff04917255ad3dbc2231587a8e8ec0a389 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Dec 2012 16:42:29 +0000 Subject: [PATCH 04/70] clk: ux500: Ensure the FMSC clock is obtainable The FMSC clock is traditionally used for NAND flash devices when used on the ux500 series platforms. This patch makes it searchable during a clock-name search. Acked-by: Mike Turquette Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/clk/ux500/u8500_clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 6b889a0e90b32..a601802286287 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -324,7 +324,7 @@ void u8500_clk_init(void) clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0); - clk_register_clkdev(clk, NULL, "fsmc"); + clk_register_clkdev(clk, "fsmc", NULL); clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, BIT(1), 0); From 1e6b6801405ec578c8607e9dabcc4e946ea64f4c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Dec 2012 16:48:02 +0000 Subject: [PATCH 05/70] clk: ux500: Provide an alias for the SMSC911x Ethernet chip In the case of some of the ux500 platforms, an Ethernet chip is placed on an extended bus which is traditionally used as a NAND flash chip placeholder. The p3_pclk0 clock is used to control it, so we are required to provide and easy way to access it from the SMSC911x driver. We do this using an alias provided by this patch. Acked-by: Mike Turquette Acked-by: Ulf Hansson Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/clk/ux500/u8500_clk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index a601802286287..9d9add1e816da 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -325,6 +325,7 @@ void u8500_clk_init(void) clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0); clk_register_clkdev(clk, "fsmc", NULL); + clk_register_clkdev(clk, NULL, "smsc911x"); clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, BIT(1), 0); From b6c230196f07b9cdd23ceb899070076cdab0c467 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Dec 2012 17:03:48 +0000 Subject: [PATCH 06/70] net/smsc911x: Provide common clock functionality Some platforms provide clocks which require enabling before the SMSC911x chip will power on. This patch uses the new common clk framework to do just that. If no clock is provided, it will just be ignored and the driver will continue to assume that no clock is required for the chip to run successfully. Acked-by: David S. Miller Reviewed-by: Linus Walleij Reviewed-by: Ulf Hansson Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/net/ethernet/smsc/smsc911x.c | 29 +++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c index da5cc9a3b34cb..df77df16d991c 100644 --- a/drivers/net/ethernet/smsc/smsc911x.c +++ b/drivers/net/ethernet/smsc/smsc911x.c @@ -33,6 +33,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -144,6 +145,9 @@ struct smsc911x_data { /* regulators */ struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES]; + + /* clock */ + struct clk *clk; }; /* Easy access to information */ @@ -369,7 +373,7 @@ smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf, } /* - * enable resources, currently just regulators. + * enable regulator and clock resources. */ static int smsc911x_enable_resources(struct platform_device *pdev) { @@ -382,6 +386,13 @@ static int smsc911x_enable_resources(struct platform_device *pdev) if (ret) netdev_err(ndev, "failed to enable regulators %d\n", ret); + + if (!IS_ERR(pdata->clk)) { + ret = clk_prepare_enable(pdata->clk); + if (ret < 0) + netdev_err(ndev, "failed to enable clock %d\n", ret); + } + return ret; } @@ -396,6 +407,10 @@ static int smsc911x_disable_resources(struct platform_device *pdev) ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies), pdata->supplies); + + if (!IS_ERR(pdata->clk)) + clk_disable_unprepare(pdata->clk); + return ret; } @@ -421,6 +436,12 @@ static int smsc911x_request_resources(struct platform_device *pdev) if (ret) netdev_err(ndev, "couldn't get regulators %d\n", ret); + + /* Request clock */ + pdata->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(pdata->clk)) + netdev_warn(ndev, "couldn't get clock %li\n", PTR_ERR(pdata->clk)); + return ret; } @@ -436,6 +457,12 @@ static void smsc911x_free_resources(struct platform_device *pdev) /* Free regulators */ regulator_bulk_free(ARRAY_SIZE(pdata->supplies), pdata->supplies); + + /* Free clock */ + if (!IS_ERR(pdata->clk)) { + clk_put(pdata->clk); + pdata->clk = NULL; + } } /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read From 237fb5e675a312a84a602ad0fbdf0b4957c71073 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 31 Jan 2013 11:27:52 +0000 Subject: [PATCH 07/70] mmc: mmci: Move ios_handler functionality into the driver There are currently two instances of the ios_handler being used. Both of which mearly toy with some regulator settings. Now there is a GPIO regulator API, we can use that instead, and lessen the per platform burden. By doing this, we also become more Device Tree compatible. Acked-by: Chris Ball Signed-off-by: Lee Jones Signed-off-by: Ulf Hansson Signed-off-by: Russell King Signed-off-by: Linus Walleij --- drivers/mmc/host/mmci.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 372e921389c8e..375c109607ff2 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -1141,6 +1141,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) case MMC_POWER_OFF: if (!IS_ERR(mmc->supply.vmmc)) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + + if (!IS_ERR(mmc->supply.vqmmc) && + regulator_is_enabled(mmc->supply.vqmmc)) + regulator_disable(mmc->supply.vqmmc); + break; case MMC_POWER_UP: if (!IS_ERR(mmc->supply.vmmc)) @@ -1155,6 +1160,10 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; case MMC_POWER_ON: + if (!IS_ERR(mmc->supply.vqmmc) && + !regulator_is_enabled(mmc->supply.vqmmc)) + regulator_enable(mmc->supply.vqmmc); + pwr |= MCI_PWR_ON; break; } From 4f902b42211b977f00a63ad6635277ef14382240 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Dec 2012 14:00:01 +0000 Subject: [PATCH 08/70] ARM: ux500: Set correct MMCI regulator voltages in the ux5x0 Device Tree Correct the voltage specified by the mmci regulator node in Device Tree. Despite the MMC subsystem insisting on v3.3, we actually only offer v2.9, and not v2.6 which must have actually been a typo. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 2ec1599a89a0c..a8562e38e9b0b 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -675,7 +675,7 @@ compatible = "regulator-gpio"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2600000>; + regulator-max-microvolt = <2900000>; regulator-name = "mmci-reg"; regulator-type = "voltage"; From e7bda303a43f5507cb76f8b41a6e73fec0f83cc8 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Dec 2012 15:00:46 +0000 Subject: [PATCH 09/70] ARM: ux500: Specify the ux5x0 MMCI regulator's on/off GPIO as high-enable If not specified, the GPIO control bit is inverted by default i.e. low-enable and high-disable. This is not the case with the MMCI regulator, hence it will turn on during a disable and off when regulator_enable() is invoked. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/dbx5x0.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index a8562e38e9b0b..b5e73aa4c3c23 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -679,6 +679,8 @@ regulator-name = "mmci-reg"; regulator-type = "voltage"; + enable-active-high; + states = <1800000 0x1 2900000 0x0>; From d05b066f6720be1a4771f1b922a3926da7097beb Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Dec 2012 15:08:45 +0000 Subject: [PATCH 10/70] ARM: ux500: Specify which IOS regulator to use for MMCI In an effort to move platform specific GPIO controlled regulators out from platform code we've created a new mechanism to specify them from within the MMCI driver using the supply name 'vmmc-ios'. For that to happen when booting device tree, we need to supply it in the MMCI (SDI) node. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/href.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi index 592fb9dc35bdc..f2c0f66c4fda6 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/href.dtsi @@ -87,6 +87,7 @@ mmc-cap-sd-highspeed; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&vmmci>; cd-gpios = <&tc3589x_gpio 3 0x4>; From 757660038c187766d39dbfccc26e279862b23a5d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 6 Dec 2012 15:11:53 +0000 Subject: [PATCH 11/70] ARM: ux500: Use the correct name when supplying a GPIO enable pin Correct a typo in the Device Tree source file, where instead of specifying property 'enable-gpio', which the driver is expecting we specified 'gpio-enable' instead. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/hrefprev60.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index eec29c4a86dce..9194fb63348e0 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -40,7 +40,7 @@ vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; - gpio-enable = <&tc3589x_gpio 17 0x4>; + enable-gpio = <&tc3589x_gpio 17 0x4>; status = "okay"; }; From 874c920241640595da77622b6ee98c14e79296e4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 7 Dec 2012 13:46:01 +0000 Subject: [PATCH 12/70] ARM: ux500: Setup correct settling time for the MMCI regulator The GPIO controlled MMCI regulator used on the ux5x0 boards takes 100us to settle. There's already a binding to provide such information. Let's make use of it. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/dbx5x0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index b5e73aa4c3c23..d765c38afebf3 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -679,6 +679,7 @@ regulator-name = "mmci-reg"; regulator-type = "voltage"; + startup-delay-us = <100>; enable-active-high; states = <1800000 0x1 From cd2fa6d6035adb92b49ef04cbd1950c59f592cf6 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 31 Jan 2013 11:31:16 +0000 Subject: [PATCH 13/70] ARM: ux500: Use the GPIO regulator framework for SDI0's 'en' and 'vsel' To prevent lots of unnecessary call-backs into platform code, we're now using the GPIO regulator framework to control the 'enable' (en) and 'voltage select' (vsel) GPIO pins which in turn control the MMCI's secondary regulator settings. This already works with Device Tree, but when booting with ATAGs we need to register it as a platform device. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-regulators.c | 14 ++++++ arch/arm/mach-ux500/board-mop500-regulators.h | 1 + arch/arm/mach-ux500/board-mop500.c | 45 +++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 2a17bc506cff7..cb7540573a854 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -28,6 +28,20 @@ struct regulator_init_data gpio_en_3v3_regulator = { .consumer_supplies = gpio_en_3v3_consumers, }; +static struct regulator_consumer_supply sdi0_reg_consumers[] = { + REGULATOR_SUPPLY("vqmmc", "sdi0"), +}; + +struct regulator_init_data sdi0_reg_init_data = { + .constraints = { + .min_uV = 1800000, + .max_uV = 2900000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(sdi0_reg_consumers), + .consumer_supplies = sdi0_reg_consumers, +}; + /* * TPS61052 regulator */ diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index 78a0642a2206a..0c79d902f9046 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -19,5 +19,6 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS]; extern struct regulator_init_data tps61052_regulator; extern struct regulator_init_data gpio_en_3v3_regulator; +extern struct regulator_init_data sdi0_reg_init_data; #endif diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index b03457881c4b5..cd100d569f4d2 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include #include @@ -89,6 +91,37 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = { }, }; +/* Dynamically populated. */ +static struct gpio sdi0_reg_gpios[] = { + { 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" }, +}; + +static struct gpio_regulator_state sdi0_reg_states[] = { + { .value = 2900000, .gpios = (0 << 0) }, + { .value = 1800000, .gpios = (1 << 0) }, +}; + +static struct gpio_regulator_config sdi0_reg_info = { + .supply_name = "ext-mmc-level-shifter", + .gpios = sdi0_reg_gpios, + .nr_gpios = ARRAY_SIZE(sdi0_reg_gpios), + .states = sdi0_reg_states, + .nr_states = ARRAY_SIZE(sdi0_reg_states), + .type = REGULATOR_VOLTAGE, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &sdi0_reg_init_data, + .startup_delay = 100, +}; + +static struct platform_device sdi0_regulator = { + .name = "gpio-regulator", + .id = -1, + .dev = { + .platform_data = &sdi0_reg_info, + }, +}; + static struct abx500_gpio_platform_data ab8500_gpio_pdata = { .gpio_base = MOP500_AB8500_PIN_GPIO(1), }; @@ -481,6 +514,7 @@ static struct hash_platform_data u8500_hash1_platform_data = { /* add any platform devices here - TODO */ static struct platform_device *mop500_platform_devs[] __initdata = { &mop500_gpio_keys_device, + &sdi0_regulator, }; #ifdef CONFIG_STE_DMA40 @@ -624,6 +658,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = { &snowball_gpio_en_3v3_regulator_dev, &u8500_thsens_device, &u8500_cpufreq_cooling_device, + &sdi0_regulator, }; static void __init mop500_init_machine(void) @@ -635,6 +670,9 @@ static void __init mop500_init_machine(void) platform_device_register(&db8500_prcmu_device); mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; + sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN; + sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL; + mop500_pinmaps_init(); parent = u8500_init_devices(&ab8500_platdata); @@ -668,6 +706,10 @@ static void __init snowball_init_machine(void) int i; platform_device_register(&db8500_prcmu_device); + + sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO; + sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO; + snowball_pinmaps_init(); parent = u8500_init_devices(&ab8500_platdata); @@ -701,6 +743,9 @@ static void __init hrefv60_init_machine(void) */ mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; + sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO; + sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO; + hrefv60_pinmaps_init(); parent = u8500_init_devices(&ab8500_platdata); From fcab564e2fd3c9048e457fb699c253db9a169c67 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 7 Dec 2012 14:00:51 +0000 Subject: [PATCH 14/70] ARM: ux500: Remove traces of the ios_handler from platform code Now MMCI on/off functionality is using the regulator framework from the MMCI driver, there is no need to keep the ios_handler laying around, duplicating functionality. So we're removing it. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-sdi.c | 52 -------------------------- 1 file changed, 52 deletions(-) diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 051b62c271020..6db0740128de5 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -31,35 +31,6 @@ * SDI 0 (MicroSD slot) */ -/* GPIO pins used by the sdi0 level shifter */ -static int sdi0_en = -1; -static int sdi0_vsel = -1; - -static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios) -{ - switch (ios->power_mode) { - case MMC_POWER_UP: - case MMC_POWER_ON: - /* - * Level shifter voltage should depend on vdd to when deciding - * on either 1.8V or 2.9V. Once the decision has been made the - * level shifter must be disabled and re-enabled with a changed - * select signal in order to switch the voltage. Since there is - * no framework support yet for indicating 1.8V in vdd, use the - * default 2.9V. - */ - gpio_direction_output(sdi0_vsel, 0); - gpio_direction_output(sdi0_en, 1); - break; - case MMC_POWER_OFF: - gpio_direction_output(sdi0_vsel, 0); - gpio_direction_output(sdi0_en, 0); - break; - } - - return 0; -} - #ifdef CONFIG_STE_DMA40 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { .mode = STEDMA40_MODE_LOGICAL, @@ -81,7 +52,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { #endif struct mmci_platform_data mop500_sdi0_data = { - .ios_handler = mop500_sdi0_ios_handler, .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | @@ -101,22 +71,6 @@ struct mmci_platform_data mop500_sdi0_data = { static void sdi0_configure(struct device *parent) { - int ret; - - ret = gpio_request(sdi0_en, "level shifter enable"); - if (!ret) - ret = gpio_request(sdi0_vsel, - "level shifter 1v8-3v select"); - - if (ret) { - pr_warning("unable to config sdi0 gpios for level shifter.\n"); - return; - } - - /* Select the default 2.9V and enable level shifter */ - gpio_direction_output(sdi0_vsel, 0); - gpio_direction_output(sdi0_en, 1); - /* Add the device, force v2 to subrevision 1 */ db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID); } @@ -124,8 +78,6 @@ static void sdi0_configure(struct device *parent) void mop500_sdi_tc35892_init(struct device *parent) { mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD; - sdi0_en = GPIO_SDMMC_EN; - sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL; sdi0_configure(parent); } @@ -264,8 +216,6 @@ void __init snowball_sdi_init(struct device *parent) /* External Micro SD slot */ mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; mop500_sdi0_data.cd_invert = true; - sdi0_en = SNOWBALL_SDMMC_EN_GPIO; - sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; sdi0_configure(parent); } @@ -277,8 +227,6 @@ void __init hrefv60_sdi_init(struct device *parent) db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); /* External Micro SD slot */ mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; - sdi0_en = HREFV60_SDMMC_EN_GPIO; - sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; sdi0_configure(parent); /* WLAN SDIO channel */ db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID); From d00156e8dfc204b97653a59ae31fa9eceff1db5f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 16 Jan 2013 14:23:38 +0000 Subject: [PATCH 15/70] ARM: ux500: enable AB8500 GPIO for HREF The AB8500 GPIO driver has been un-BROKEN and rewritten as a pinctrl driver. Now that it's back in use, let's ensure that it's available when booting HREF with Device Tree enabled. Cc: arm@kernel.org Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/hrefprev60.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index 9194fb63348e0..c2d2748159238 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts @@ -25,6 +25,14 @@ }; soc-u9500 { + prcmu@80157000 { + ab8500@5 { + ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; + }; + }; + }; + i2c@80004000 { tps61052@33 { compatible = "tps61052"; From 924e82dacab9a0b2ea661c57c98112569267f0db Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 16 Jan 2013 14:28:03 +0000 Subject: [PATCH 16/70] ARM: ux500: allow Snowball access to the AB8500 GPIO pins The AB8500 GPIO driver has been un-BROKEN and rewritten as a pinctrl driver. Now that it's back in use, let's ensure that it's available when booting Snowball with Device Tree enabled. Cc: arm@kernel.org Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/snowball.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 27f31a5fa4947..b095e85d93c8e 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -299,6 +299,10 @@ }; ab8500@5 { + ab8500-gpio { + compatible = "stericsson,ab8500-gpio"; + }; + ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; From 908ab9368866e6edf0edebdd546adefd5f3128f9 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 22 Feb 2013 11:23:39 +0800 Subject: [PATCH 17/70] ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host The GPIO pin of SD slot card detection should active low. Signed-off-by: Joseph Lo Tested-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 2 +- arch/arm/boot/dts/tegra20-harmony.dts | 4 ++-- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +- arch/arm/boot/dts/tegra20-trimslice.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra20-whistler.dts | 1 + arch/arm/boot/dts/tegra30-beaver.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 10 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 444162090042c..cb73e62d61a97 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -444,7 +444,7 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 23 0>; /* gpio PC7 */ + cd-gpios = <&gpio 23 1>; /* gpio PC7 */ }; sound { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 61d027f03617d..1f79c0debb050 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -437,7 +437,7 @@ sdhci@c8000200 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <4>; @@ -445,7 +445,7 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <8>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 54d6fce00a59e..9db36da8e0233 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -436,7 +436,7 @@ sdhci@c8000000 { status = "okay"; - cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + cd-gpios = <&gpio 173 1>; /* gpio PV5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 169 0>; /* gpio PV1 */ bus-width = <4>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 37b3a57ec0f15..715a8b8dd9cdd 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -584,7 +584,7 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 4766abae7a72b..6e9d91fc61956 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -465,7 +465,7 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ bus-width = <4>; status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 5d79e4fc49a63..98f3e44f2a51c 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -325,7 +325,7 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 121 0>; /* gpio PP1 */ + cd-gpios = <&gpio 121 1>; /* gpio PP1 */ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ bus-width = <4>; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 425c89000c20e..4aef56f2d96a0 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -520,7 +520,7 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index ea57c0f6dccea..5762188c60ad3 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -510,6 +510,7 @@ sdhci@c8000400 { status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 173 0>; /* gpio PV5 */ bus-width = <8>; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 8ff2ff20e4a34..0a2cd24df853b 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -257,7 +257,7 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 17499272a4ef9..3e2d21018a5b1 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -311,7 +311,7 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; From c34f30e588d310a70f994659c06f0a31dfdcfc15 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 4 Mar 2013 17:05:56 -0700 Subject: [PATCH 18/70] ARM: tegra: add CPU errata WARs to Tegra reset handler The CPU cores in Tegra contain some errata. Workarounds must be applied for these every time a CPU boots. Implement those workarounds directly in the Tegra-specific CPU reset vector. Many of these workarounds duplicate code in the core ARM kernel. However, the core ARM kernel cannot enable those workarounds when building a multi-platform kernel, since they require writing to secure- only registers, and a multi-platform kernel often does not run in secure mode, and also cannot generically/architecturally detect whether it is running in secure mode, and hence cannot either unconditionally or conditionally apply these workarounds. Instead, the workarounds must be applied in architecture-specific reset code, which is able to have more direct knowledge of the secure/normal state. On Tegra, we will be able to detect this using a non-architected register in the future, although we currently assume the kernel runs only in secure mode. Other SoCs may never run the kernel in secure mode, and hence always rely on a secure monitor to enable the workarounds, and hence never implement them in the kernel. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/reset-handler.S | 45 +++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 54382ceade4a5..ff7b45c6c2a0a 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -99,6 +99,8 @@ ENTRY(__tegra_cpu_reset_handler_start) * * Register usage within the reset handler: * + * Others: scratch + * R6 = SoC ID << 8 * R7 = CPU present (to the OS) mask * R8 = CPU in LP1 state mask * R9 = CPU in LP2 state mask @@ -114,6 +116,40 @@ ENTRY(__tegra_cpu_reset_handler_start) ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled + + mov32 r6, TEGRA_APB_MISC_BASE + ldr r6, [r6, #APB_MISC_GP_HIDREV] + and r6, r6, #0xff00 +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +t20_check: + cmp r6, #(0x20 << 8) + bne after_t20_check +t20_errata: + # Tegra20 is a Cortex-A9 r1p1 + mrc p15, 0, r0, c1, c0, 0 @ read system control register + orr r0, r0, #1 << 14 @ erratum 716044 + mcr p15, 0, r0, c1, c0, 0 @ write system control register + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 4 @ erratum 742230 + orr r0, r0, #1 << 11 @ erratum 751472 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register + b after_errata +after_t20_check: +#endif +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +t30_check: + cmp r6, #(0x30 << 8) + bne after_t30_check +t30_errata: + # Tegra30 is a Cortex-A9 r2p9 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 6 @ erratum 743622 + orr r0, r0, #1 << 11 @ erratum 751472 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register + b after_errata +after_t30_check: +#endif +after_errata: mrc p15, 0, r10, c0, c0, 5 @ MPIDR and r10, r10, #0x3 @ R10 = CPU number mov r11, #1 @@ -129,16 +165,13 @@ ENTRY(__tegra_cpu_reset_handler) #ifdef CONFIG_ARCH_TEGRA_2x_SOC /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) + cmp r6, #(0x20 << 8) bne 1f /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov32 r6, TEGRA_PMC_BASE + mov32 r5, TEGRA_PMC_BASE mov r0, #0 cmp r10, #0 - strne r0, [r6, #PMC_SCRATCH41] + strne r0, [r5, #PMC_SCRATCH41] 1: #endif From 02e75d648899df96b79a4f98380679f48b91e3d4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 4 Mar 2013 17:05:57 -0700 Subject: [PATCH 19/70] ARM: tegra: remove save/restore of CPU diag register Prior to this change, {save,restore}_cpu_arch_register() collaborated to maintain the value of the CPU diagnostic register across power cycles. This was required to maintain any CPU errata workaround enable bits in that register. However, now that the Tegra reset vector code always enables all required workarounds, there is no need to save and restore the diagnostic register; it is always explicitly programmed in the required manner. Hence, remove the save/restore logic. This has the advantage that the kernel always directly controls the value of this register every boot, rather than relying on a bootloader or other kernel code having previously written the correct value into it. This makes CPU0 (which was previously saved/restored) and CPUn (which should have been set up by the reset vector) be controlled in exactly the same way, which is easier to debug/find/... In particular, when converting Tegra to a multi-platform kernel, the CPU0 diagnostic register value initially comes from the bootloader. Most Tegra bootloaders don't yet enable all required CPU bug workarounds. The previous commit updates the kernel to do so on any CPU power cycle. However, the save/restore code ends up over-writing the value with the old bootloader-driven value instead of the now more-likely-to-be-correct kernel value! Even irrespective of multi-platform conversion, this change limits the kernel's exposure to any WARs the bootloader didn't enable for CPU0: on the very first LP2 transition (CPU power-saving which power-cycles the CPU), the correct value will be enabled. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/cpuidle-tegra30.c | 4 ---- arch/arm/mach-tegra/pm.c | 19 ------------------- 2 files changed, 23 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 8b50cf4ddd6f0..80445ed33d952 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -102,12 +102,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, smp_wmb(); - save_cpu_arch_register(); - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); - restore_cpu_arch_register(); - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); return true; diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 523604de666f6..0494f739c95f9 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -46,26 +46,11 @@ #define PMC_CPUPWROFF_TIMER 0xcc #ifdef CONFIG_PM_SLEEP -static unsigned int g_diag_reg; static DEFINE_SPINLOCK(tegra_lp2_lock); static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); static struct clk *tegra_pclk; void (*tegra_tear_down_cpu)(void); -void save_cpu_arch_register(void) -{ - /* read diagnostic register */ - asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); - return; -} - -void restore_cpu_arch_register(void) -{ - /* write diagnostic register */ - asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); - return; -} - static void set_power_timers(unsigned long us_on, unsigned long us_off) { unsigned long long ticks; @@ -119,8 +104,6 @@ static void restore_cpu_complex(void) tegra_cpu_clock_resume(); flowctrl_cpu_suspend_exit(cpu); - - restore_cpu_arch_register(); } /* @@ -145,8 +128,6 @@ static void suspend_cpu_complex(void) tegra_cpu_clock_suspend(); flowctrl_cpu_suspend_enter(cpu); - - save_cpu_arch_register(); } void tegra_clear_cpu_in_lp2(int phy_cpu_id) From bf161d2163f7b8bf4823829dbc1a14111760187e Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Fri, 8 Feb 2013 14:44:09 +0200 Subject: [PATCH 20/70] clk: tegra: No 7.1 super clk dividers on Tegra20 Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver Signed-off-by: Stephen Warren --- drivers/clk/tegra/clk-tegra20.c | 36 ++------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 143ce1f899ad7..fa3173e3b331c 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -711,8 +711,8 @@ static void tegra20_pll_init(void) } static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", - "pll_p_cclk", "pll_p_out4_cclk", - "pll_p_out3_cclk", "clk_d", "pll_x" }; + "pll_p", "pll_p_out4", + "pll_p_out3", "clk_d", "pll_x" }; static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", "pll_p_out3", "pll_p_out2", "clk_d", "clk_32k", "pll_m_out1" }; @@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void) { struct clk *clk; - /* - * DIV_U71 dividers for CCLK, these dividers are used only - * if parent clock is fixed rate. - */ - - /* - * Clock input to cclk divided from pll_p using - * U71 divider of cclk. - */ - clk = tegra_clk_register_divider("pll_p_cclk", "pll_p", - clk_base + SUPER_CCLK_DIVIDER, 0, - TEGRA_DIVIDER_INT, 16, 8, 1, NULL); - clk_register_clkdev(clk, "pll_p_cclk", NULL); - - /* - * Clock input to cclk divided from pll_p_out3 using - * U71 divider of cclk. - */ - clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3", - clk_base + SUPER_CCLK_DIVIDER, 0, - TEGRA_DIVIDER_INT, 16, 8, 1, NULL); - clk_register_clkdev(clk, "pll_p_out3_cclk", NULL); - - /* - * Clock input to cclk divided from pll_p_out4 using - * U71 divider of cclk. - */ - clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4", - clk_base + SUPER_CCLK_DIVIDER, 0, - TEGRA_DIVIDER_INT, 16, 8, 1, NULL); - clk_register_clkdev(clk, "pll_p_out4_cclk", NULL); - /* CCLK */ clk = tegra_clk_register_super_mux("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, From b095ae2b9f35c838257786de27e550d62bd7c763 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 19 Feb 2013 18:16:13 +0800 Subject: [PATCH 21/70] ARM: tegra: don't unlock MMIO access to DBGLAR There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/headsmp.S | 3 --- arch/arm/mach-tegra/reset-handler.S | 3 --- 2 files changed, 6 deletions(-) diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index fd473f2b4c3d9..045c16f2dd51f 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -7,8 +7,5 @@ ENTRY(tegra_secondary_startup) bl v7_invalidate_l1 - /* Enable coresight */ - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 b secondary_startup ENDPROC(tegra_secondary_startup) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index ff7b45c6c2a0a..1676aba5e7b84 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -41,9 +41,6 @@ */ ENTRY(tegra_resume) bl v7_invalidate_l1 - /* Enable coresight */ - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 cpu_id r0 cmp r0, #0 @ CPU0? From b4c25cc38260950f9ede38a88f932c7958adb2ec Mon Sep 17 00:00:00 2001 From: Hiroshi Doyu Date: Fri, 22 Feb 2013 14:24:25 +0800 Subject: [PATCH 22/70] ARM: tegra: Fix unchecked return value Check a return value for tegra_powergate_remove_clamping(). Signed-off-by: Hiroshi Doyu Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/platsmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 2c6b3d55213b4..4dfc75e118ff8 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -124,6 +124,9 @@ static int tegra30_power_up_cpu(unsigned int cpu) /* Remove I/O clamps. */ ret = tegra_powergate_remove_clamping(pwrgateid); + if (ret) + return ret; + udelay(10); /* Clear flow controller CSR. */ From 2be8951e145eacf2a951288ea8e752e3b21acefd Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 22 Feb 2013 14:24:26 +0800 Subject: [PATCH 23/70] ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs The warm boot sequence of Tegra30 secondary CPUs should wait for the power ready then removing the clamps. This did not fix any known or unknown issue, but nice to have this fix. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 4dfc75e118ff8..e78d52d83acd0 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -91,7 +91,7 @@ static int tegra30_power_up_cpu(unsigned int cpu) if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { timeout = jiffies + msecs_to_jiffies(50); do { - if (!tegra_powergate_is_powered(pwrgateid)) + if (tegra_powergate_is_powered(pwrgateid)) goto remove_clamps; udelay(10); } while (time_before(jiffies, timeout)); From 84b808da2dea7020211f1d73d015ff6c3ac207c4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 6 Mar 2013 17:16:25 -0700 Subject: [PATCH 24/70] ARM: tegra: fix ignored return value of regulator_enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’: arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return value of ‘regulator_enable’, declared with attribute warn_unused_result [-Wunused-result] Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/board-harmony-pcie.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 3cdc1bb8254c6..d195db09ea326 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c @@ -62,7 +62,11 @@ int __init harmony_pcie_init(void) goto err_reg; } - regulator_enable(regulator); + err = regulator_enable(regulator); + if (err) { + pr_err("%s: regulator_enable failed: %d\n", __func__, err); + goto err_en; + } err = tegra_pcie_init(true, true); if (err) { @@ -74,6 +78,7 @@ int __init harmony_pcie_init(void) err_pcie: regulator_disable(regulator); +err_en: regulator_put(regulator); err_reg: gpio_free(en_vdd_1v05); From d4cba7fa7e2b25b463e51006bdeab7110f96ec33 Mon Sep 17 00:00:00 2001 From: Hiroshi Doyu Date: Thu, 14 Mar 2013 11:12:10 +0200 Subject: [PATCH 25/70] memory: tegra30: Fix build error w/o PM Make this depend on CONFIG_PM. Signed-off-by: Hiroshi Doyu Reviewed-by: Thierry Reding Signed-off-by: Stephen Warren --- drivers/memory/tegra30-mc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/memory/tegra30-mc.c b/drivers/memory/tegra30-mc.c index 0b975986777db..f4ae074badc37 100644 --- a/drivers/memory/tegra30-mc.c +++ b/drivers/memory/tegra30-mc.c @@ -268,6 +268,7 @@ static const u32 tegra30_mc_ctx[] = { MC_INTMASK, }; +#ifdef CONFIG_PM static int tegra30_mc_suspend(struct device *dev) { int i; @@ -291,6 +292,7 @@ static int tegra30_mc_resume(struct device *dev) mc_readl(mc, MC_TIMING_CONTROL); return 0; } +#endif static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm, tegra30_mc_suspend, From 5a898a782fee197c6d12d2d5d81868d69090df7b Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 7 Jan 2013 19:29:46 +0530 Subject: [PATCH 26/70] ARM: OMAP5: Update SOC id detection code for ES2 Update OMAP5 ES2 idcode and make ES2 as default detection. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/id.c | 12 +++++++++--- arch/arm/mach-omap2/soc.h | 2 ++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 8a68f1ec66b9a..ff0bc9e51aa77 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -529,22 +529,28 @@ void __init omap5xxx_check_revision(void) case 0xb942: switch (rev) { case 0: - default: omap_revision = OMAP5430_REV_ES1_0; + break; + case 1: + default: + omap_revision = OMAP5430_REV_ES2_0; } break; case 0xb998: switch (rev) { case 0: - default: omap_revision = OMAP5432_REV_ES1_0; + break; + case 1: + default: + omap_revision = OMAP5432_REV_ES2_0; } break; default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP5430_REV_ES1_0; + omap_revision = OMAP5430_REV_ES2_0; } pr_info("OMAP%04x ES%d.0\n", diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index c62116bbc760d..18fdeeb3a44a4 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP54XX_CLASS 0x54000054 #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) +#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) +#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); From 960cba672bcecc6357984101703e70a8c819ccaa Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 7 Jan 2013 17:23:22 +0530 Subject: [PATCH 27/70] ARM: OMAP5: timer: Update the clocksource name as per clock data OMAP5 clockdata has different sys clock node name. Fix the timer code to take care of it. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/timer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2bdd4cf17a8fd..773733fccd835 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -62,6 +62,7 @@ #define OMAP2_MPU_SOURCE "sys_ck" #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE #define OMAP4_MPU_SOURCE "sys_clkin_ck" +#define OMAP5_MPU_SOURCE "sys_clkin" #define OMAP2_32K_SOURCE "func_32k_ck" #define OMAP3_32K_SOURCE "omap_32k_fck" #define OMAP4_32K_SOURCE "sys_32k_ck" @@ -487,7 +488,7 @@ static void __init realtime_counter_init(void) pr_err("%s: ioremap failed\n", __func__); return; } - sys_clk = clk_get(NULL, "sys_clkin_ck"); + sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE); if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); @@ -616,7 +617,7 @@ void __init omap4_local_timer_init(void) #ifdef CONFIG_SOC_OMAP5 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", - 2, OMAP4_MPU_SOURCE); + 2, OMAP5_MPU_SOURCE); void __init omap5_realtime_timer_init(void) { int err; From 7515148af90aaf5cb7c400aa1436f2a5ef5c78e9 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 7 Jan 2013 17:23:22 +0530 Subject: [PATCH 28/70] ARM: OMAP5: prm: Allow prm init to succeed Allow prm init to succeed on OMAP5 SOCs. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/prm44xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index d35f98aabf7a2..960483d8a0325 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { int __init omap44xx_prm_init(void) { - if (!cpu_is_omap44xx()) + if (!cpu_is_omap44xx() && !soc_is_omap54xx()) return 0; return prm_register(&omap44xx_prm_ll_data); From 077173c0aaac62aef6f55a841f03c7d7001958ab Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 8 Feb 2013 17:51:22 +0530 Subject: [PATCH 29/70] ARM: OMAP5: Reuse prm read_inst/write_inst Make use of 'prm_base' so that prm read_inst/write_inst can work on OMAP5 devices. Signed-off-by: Tero Kristo Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/prm44xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 960483d8a0325..415c7e0c9393a 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { /* Read a register in a CM/PRM instance in the PRM module */ u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); + return __raw_readl(prm_base + inst + reg); } /* Write into a register in a CM/PRM instance in the PRM module */ void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); + __raw_writel(val, prm_base + inst + reg); } /* Read-modify-write a register in a PRM module. Caller must lock */ From da0e02a1e4a6348505cfe0cbb0d3a2717a2b5476 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 6 Feb 2013 17:54:39 +0530 Subject: [PATCH 30/70] ARM: OMAP5: Update SAR RAM base address Update SAR RAM base address for OMAP5 based devices. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap4-common.c | 10 ++++++++-- arch/arm/mach-omap2/omap54xx.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 708bb115a27ff..2aeb928efdfdb 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -240,15 +240,21 @@ void __iomem *omap4_get_sar_ram_base(void) */ static int __init omap4_sar_ram_init(void) { + unsigned long sar_base; + /* * To avoid code running on other OMAPs in * multi-omap builds */ - if (!cpu_is_omap44xx()) + if (cpu_is_omap44xx()) + sar_base = OMAP44XX_SAR_RAM_BASE; + else if (soc_is_omap54xx()) + sar_base = OMAP54XX_SAR_RAM_BASE; + else return -ENOMEM; /* Static mapping, never released */ - sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); + sar_ram_base = ioremap(sar_base, SZ_16K); if (WARN_ON(!sar_ram_base)) return -ENOMEM; diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a2582bb3cab3d..a086ba15868b2 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h @@ -28,5 +28,6 @@ #define OMAP54XX_PRCM_MPU_BASE 0x48243000 #define OMAP54XX_SCM_BASE 0x4a002000 #define OMAP54XX_CTRL_BASE 0x4a002800 +#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 #endif /* __ASM_SOC_OMAP555554XX_H */ From 13fcef9431660ebdfbd6f2a0a6ee9809bf695804 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 6 Feb 2013 18:21:53 +0530 Subject: [PATCH 31/70] ARM: OMAP5: Update SAR memory layout for WakeupGen On OMAP5 es2 WakeupGen SAR register layout offset have changed. Update the layout accordingly. Reported-by: Menon, Nishanth Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap4-sar-layout.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h index e170fe803b046..937417523b8ec 100644 --- a/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/arch/arm/mach-omap2/omap4-sar-layout.h @@ -48,13 +48,13 @@ #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ -#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) -#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) -#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) -#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) -#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) +#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) +#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) +#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) #endif From 1348bbf942ebf21db7ff235f9bbdf9cd36be3ffe Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 15 Feb 2013 18:05:49 +0530 Subject: [PATCH 32/70] ARM: OMAP5: Make errata i688 workaround available Errata i688 is also applicable for OMAP5 based devices. Update the code so that it can be enabled on OMAP5 devices. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/Kconfig | 2 +- arch/arm/mach-omap2/io.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 8111cd9ff3e52..b9c0ed3f648c8 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -408,7 +408,7 @@ config OMAP3_SDRC_AC_TIMING config OMAP4_ERRATA_I688 bool "OMAP4 errata: Async Bridge Corruption" - depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM + depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM select ARCH_HAS_BARRIERS help If a data is stalled inside asynchronous bridge because of back diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 2c3fdd65387b5..2bef5a7e6af80 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -271,6 +271,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .length = L4_PER_54XX_SIZE, .type = MT_DEVICE, }, +#ifdef CONFIG_OMAP4_ERRATA_I688 + { + .virtual = OMAP4_SRAM_VA, + .pfn = __phys_to_pfn(OMAP4_SRAM_PA), + .length = PAGE_SIZE, + .type = MT_MEMORY_SO, + }, +#endif }; #endif @@ -323,6 +331,7 @@ void __init omap4_map_io(void) void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); + omap_barriers_init(); } #endif /* From ecf51648c192377ea2830101b12fc3017bfd2b0c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 29 Jan 2013 18:33:49 +0530 Subject: [PATCH 33/70] ARM: OMAP5: clock: No Freqsel on OMAP5 devices too OMAP5 does not have freqsel either, so checks needs to be extended. Infact only OMAP343X devices has the freqsel support, so fix the check accordingly so that future patching can be avoided. Reported-by: Archit Taneja Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/dpll3xxx.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3aed4b0b95632..ae84c9d401187 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) _omap3_noncore_dpll_bypass(clk); /* - * Set jitter correction. No jitter correction for OMAP4 and 3630 - * since freqsel field is no longer present + * Set jitter correction. Jitter correction applicable for OMAP343X + * only since freqsel field is no longer present on other devices. */ - if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (cpu_is_omap343x()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -500,9 +500,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (dd->last_rounded_rate == 0) return -EINVAL; - /* No freqsel on AM335x, OMAP4 and OMAP3630 */ - if (!soc_is_am33xx() && !cpu_is_omap44xx() && - !cpu_is_omap3630()) { + /* Freqsel is available only on OMAP343X devices */ + if (cpu_is_omap343x()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); From 5b6513d277759316a69fd40ca8dbdf89dba0462f Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Fri, 8 Mar 2013 13:06:37 +0100 Subject: [PATCH 34/70] ARM: OMAP: fix typo "CONFIG_SMC91x_MODULE" There's a (rather subtle) typo in "CONFIG_SMC91x_MODULE". Fix it once and for all by using IS_ENABLED(), which is designed to avoid issues like this. Signed-off-by: Paul Bolle Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 2 +- arch/arm/mach-omap2/board-h4.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index a3e0aaa4886b9..cb0596b631cff 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void) omap_display_init(&sdp2430_dss_data); } -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 5, diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 812c829fa46f6..5b4ec51c385f0 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void) return 0; } -#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) +#if IS_ENABLED(CONFIG_SMC91X) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 1, From 99f69fea23d3c87c4f3067cb69499ff76499d93b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 28 Mar 2013 21:35:03 +0100 Subject: [PATCH 35/70] ARM: tegra: Export tegra_powergate_sequence_power_up() This function can be used by drivers to enable power to the hardware blocks that they drive. Most of the drivers can be built as a module and therefore require this function to be exported. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index c6bc8f85759c6..c472bed3245e9 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -168,6 +169,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) err_power: return ret; } +EXPORT_SYMBOL(tegra_powergate_sequence_power_up); int tegra_cpu_powergate_id(int cpuid) { From eebd1fda2342014a50ed3fd132e5dc6e8b5251e8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 28 Mar 2013 21:35:04 +0100 Subject: [PATCH 36/70] ARM: tegra: powergate: Don't error out if new state == old state Don't treat it as an error if a partition is already in the same power state when a user wants to power it on or off. This allows code to proceed if no state change is required. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index c472bed3245e9..af9067e2867cf 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -76,7 +76,7 @@ static int tegra_powergate_set(int id, bool new_state) if (status == new_state) { spin_unlock_irqrestore(&tegra_powergate_lock, flags); - return -EINVAL; + return 0; } pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); From fc46d17c4a6b7aa2af11eb9275ed9791f2594ddf Mon Sep 17 00:00:00 2001 From: Mac Lin Date: Mon, 25 Mar 2013 17:24:19 +0800 Subject: [PATCH 37/70] ARM: cns3xxx: remove unused virtual address and iotable defines Signed-off-by: Mac Lin Signed-off-by: Anton Vorontsov --- arch/arm/mach-cns3xxx/core.c | 10 -------- arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | 27 -------------------- 2 files changed, 37 deletions(-) diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 52e4bb5cf12df..126f74f6087cf 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -31,16 +31,6 @@ static struct map_desc cns3xxx_io_desc[] __initdata = { .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE), .length = SZ_4K, .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_GPIOA_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_GPIOB_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), - .length = SZ_4K, - .type = MT_DEVICE, }, { .virtual = CNS3XXX_MISC_BASE_VIRT, .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index b1021aafa4810..9b145b1e48ead 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -20,22 +20,16 @@ #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ -#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ -#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ -#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ -#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ -#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ -#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 #define SMC_MEMC_STATUS_OFFSET 0x000 #define SMC_MEMIF_CFG_OFFSET 0x004 @@ -74,13 +68,10 @@ #define SMC_PCELL_ID_3_OFFSET 0xFFC #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ -#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ -#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ -#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 #define RTC_SEC_OFFSET 0x00 #define RTC_MIN_OFFSET 0x04 @@ -112,22 +103,16 @@ #define CNS3XXX_UART0_BASE_VIRT 0xFB002000 #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ -#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 #define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ -#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 #define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ -#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 #define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ -#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 #define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ -#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 #define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ -#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 @@ -150,42 +135,31 @@ #define TIMER_FREERUN_CONTROL_OFFSET 0x44 #define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ -#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 #define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ -#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 #define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ -#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 #define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ -#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 #define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ -#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ #define CNS3XXX_SATA2_SIZE SZ_16M -#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 #define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ -#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 #define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ -#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 #define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ -#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 #define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ -#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ -#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ #define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 @@ -239,7 +213,6 @@ #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ -#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 /* * Misc block From 05cf03b6eb7f791ad70b1540df2c39b54d428258 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sun, 31 Mar 2013 20:22:21 -0600 Subject: [PATCH 38/70] ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry This patch adds sysc definitions to the wdt1 hwmod entry, which in-turn makes sure that sysc idle bit-fields are configured to valid state on enable/disable callbacks. With the recent submitted patch from Santosh Shilimkar, "ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc" (commit: 4a98c2d89), it is required to add sysconf information to each valid hwmod entry, else device will not be come out from idle state properly and leads to below kernel crash - [2.190237] Unhandled fault: external abort on non-linefetch (0x1028) at 0xf9e35034 [2.198325] Internal error: : 1028 [#1] SMP ARM [2.203101] Modules linked in: [2.206334] CPU: 0 Not tainted (3.9.0-rc3-00059-gd114294#1) [2.212679] PC is at omap_wdt_disable.clone.5+0xc/0x60 [2.218090] LR is at omap_wdt_probe+0x184/0x1fc Signed-off-by: Vaibhav Hiremath Cc: Santosh Shilimkar Cc: Benoit Cousson Cc: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 26eee4a556ad1..31bea1ce3de10 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -28,6 +28,7 @@ #include "prm-regbits-33xx.h" #include "i2c.h" #include "mmc.h" +#include "wd_timer.h" /* * IP blocks @@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = { }; /* 'wd_timer' class */ +static struct omap_hwmod_class_sysconfig wdt_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { .name = "wd_timer", + .sysc = &wdt_sysc, + .pre_shutdown = &omap2_wd_timer_disable, }; /* @@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = { .name = "wd_timer2", .class = &am33xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", + .flags = HWMOD_SWSUP_SIDLE, .main_clk = "wdt1_fck", .prcm = { .omap4 = { From da91b89eb76d4ecddcfc7fca3b8422891eb5e62e Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Sun, 31 Mar 2013 20:22:21 -0600 Subject: [PATCH 39/70] ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk WDT1 module can take one of the below clocks as input functional clock - - On-Chip 32K RC Osc [default/reset] - 32K from PRCM The On-Chip 32K RC Osc clock is not an accurate clock-source as per the design/spec, so as a result, for example, timer which supposed to get expired @60Sec, but will expire somewhere ~@40Sec, which is not expected by any use-case. The solution here is to switch the input clock-source to PRCM generated 32K clock-source during boot-time itself. Signed-off-by: Vaibhav Hiremath Cc: Santosh Shilimkar Cc: Benoit Cousson Cc: Paul Walmsley --- arch/arm/mach-omap2/cclock33xx_data.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 476b82066cb6b..7f091c85384e2 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -958,6 +958,14 @@ int __init am33xx_clk_init(void) clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; } From 4280943b6bc81357eb61c3e1111d2d83ec2ef03d Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Sun, 31 Mar 2013 20:22:22 -0600 Subject: [PATCH 40/70] ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag _HWMOD_WAKEUP_ENABLED is currently unused across the hwmod framework. Just get rid of it, so we have one less flag to worry about. Tested-by: Vaibhav Bedia Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 4 ---- arch/arm/mach-omap2/omap_hwmod.h | 6 ++---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index c2c798c08c2b9..e5cafed8ef258 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -610,8 +610,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ - oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; - return 0; } @@ -645,8 +643,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ - oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; - return 0; } diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index d43d9b608edab..28f4dea0512e8 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -477,15 +477,13 @@ struct omap_hwmod_omap4_prcm { * These are for internal use only and are managed by the omap_hwmod code. * * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module - * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - * causes the first call to _enable() to only update the pinmux */ #define _HWMOD_NO_MPU_PORT (1 << 0) -#define _HWMOD_WAKEUP_ENABLED (1 << 1) -#define _HWMOD_SYSCONFIG_LOADED (1 << 2) -#define _HWMOD_SKIP_ENABLE (1 << 3) +#define _HWMOD_SYSCONFIG_LOADED (1 << 1) +#define _HWMOD_SKIP_ENABLE (1 << 2) /* * omap_hwmod._state definitions From bd70f6eb3e78b7c9c6bec2cf5be6423dd2b37f6f Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Sun, 31 Mar 2013 20:22:22 -0600 Subject: [PATCH 41/70] ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0 _pwrdm_save_clkdm_state_and_activate() tried to test one of its unsigned arguments to determine whether it was less than zero. Fix by moving the error test to the caller. Reported-by: Chen Gang Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/powerdomain.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 8e61d80bf6b34..89cad4a605dde 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -52,7 +52,6 @@ enum { #define ALREADYACTIVE_SWITCH 0 #define FORCEWAKEUP_SWITCH 1 #define LOWPOWERSTATE_SWITCH 2 -#define ERROR_SWITCH 3 /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm, { u8 sleep_switch; - if (curr_pwrst < 0) { - WARN_ON(1); - sleep_switch = ERROR_SWITCH; - } else if (curr_pwrst < PWRDM_POWER_ON) { + if (curr_pwrst < PWRDM_POWER_ON) { if (curr_pwrst > pwrst && pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && arch_pwrdm->pwrdm_set_lowpwrstchange) { @@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) */ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) { - u8 curr_pwrst, next_pwrst, sleep_switch; + u8 next_pwrst, sleep_switch; + int curr_pwrst; int ret = 0; bool hwsup = false; @@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) pwrdm_lock(pwrdm); curr_pwrst = pwrdm_read_pwrst(pwrdm); + if (curr_pwrst < 0) { + ret = -EINVAL; + goto osps_out; + } + next_pwrst = pwrdm_read_next_pwrst(pwrdm); if (curr_pwrst == pwrst && next_pwrst == pwrst) goto osps_out; sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, pwrst, &hwsup); - if (sleep_switch == ERROR_SWITCH) { - ret = -EINVAL; - goto osps_out; - } ret = pwrdm_set_next_pwrst(pwrdm, pwrst); if (ret) From 469d633d20c774ecd34ac615c838193e1e150c62 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Sun, 31 Mar 2013 20:22:23 -0600 Subject: [PATCH 42/70] ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well as ref clk for every .set_rate attempt on a noncore DPLL, regardless of whether the .set_rate results in the DPLL being locked or put in bypass. Early at boot, while some of these DPLLs are programmed and locked (using .set_rate for the DPLL), this causes an ordering issue. For instance, on OMAP5, the USB DPLL derives its bypass clk from ABE DPLL. If a .set_rate of USB DPLL which programmes the M,N and locks it is called before the one for ABE, the enable of USB bypass clk (derived from ABE DPLL) then attempts to lock the ABE DPLL and fails as the M,N values for ABE are yet to be programmed. To get rid of this ordering needs, enable bypass clk for a DPLL as part of its .set_rate only when its being put in bypass, and only enable the ref clk when its locked. Reported-by: Roger Quadros Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/dpll3xxx.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3aed4b0b95632..6e9873ff18446 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -480,20 +480,22 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!dd) return -EINVAL; - __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); - __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); - if (__clk_get_rate(dd->clk_bypass) == rate && (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("%s: %s: set rate: entering bypass.\n", __func__, __clk_get_name(hw->clk)); + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); } else { + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + if (dd->last_rounded_rate != rate) rate = __clk_round_rate(hw->clk, rate); @@ -514,6 +516,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); } /* * FIXME - this is all wrong. common code handles reparenting and @@ -525,11 +529,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!ret) __clk_reparent(hw->clk, new_parent); - clk_disable(dd->clk_ref); - __clk_unprepare(dd->clk_ref); - clk_disable(dd->clk_bypass); - __clk_unprepare(dd->clk_bypass); - return 0; } From e7feaaa75db6f2d1cace8d26ba3fa54df020b1a5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:28 -0300 Subject: [PATCH 43/70] ARM: mach-imx: cpu: Include "common.h" Fix the following sparse warnings: arch/arm/mach-imx/cpu.c:10:6: warning: symbol 'mxc_set_cpu_type' was not declared. Should it be static? arch/arm/mach-imx/cpu.c:15:6: warning: symbol 'imx_print_silicon_rev' was not declared. Should it be static? arch/arm/mach-imx/cpu.c:24:13: warning: symbol 'imx_set_aips' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 03fcbd082593b..e70e3acbf9bd0 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -3,6 +3,7 @@ #include #include "hardware.h" +#include "common.h" unsigned int __mxc_cpu_type; EXPORT_SYMBOL(__mxc_cpu_type); From eb7099be53655063162d3b67db7fbaf15dfac893 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:29 -0300 Subject: [PATCH 44/70] ARM: mach-imx: mm-imx3: Staticize imx3_init_l2x0() Fix the following sparse warning: arch/arm/mach-imx/mm-imx3.c:85:13: warning: symbol 'imx3_init_l2x0' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mm-imx3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index cefa047c4053f..e0e69a682174b 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -82,7 +82,7 @@ static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size, return __arm_ioremap_caller(phys_addr, size, mtype, caller); } -void __init imx3_init_l2x0(void) +static void __init imx3_init_l2x0(void) { #ifdef CONFIG_CACHE_L2X0 void __iomem *l2x0_base; From 4355632c54d4fd06b9fbc5d7a83dbf6437946d03 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:30 -0300 Subject: [PATCH 45/70] ARM: mach-imx: iomux-imx31: Staticize mxc_pin_alloc_map Fix the following sparse warning: arch/arm/mach-imx/iomux-imx31.c:43:15: warning: symbol 'mxc_pin_alloc_map' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/iomux-imx31.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c index cabefbc5e7c16..7c66805d2cc0d 100644 --- a/arch/arm/mach-imx/iomux-imx31.c +++ b/arch/arm/mach-imx/iomux-imx31.c @@ -40,7 +40,7 @@ static DEFINE_SPINLOCK(gpio_mux_lock); #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) -unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; +static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; /* * set the mode for a IOMUX pin. */ From 22567796220cc275e360cdb4bf9ca56067ebc5f0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:31 -0300 Subject: [PATCH 46/70] ARM: mach-imx: cpu-imx5: Include "common.h" Fix the following sparse warnings: arch/arm/mach-imx/cpu-imx5.c:65:12: warning: symbol 'mx51_neon_fixup' was not declared. Should it be static? arch/arm/mach-imx/cpu-imx5.c:99:5: warning: symbol 'mx53_revision' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu-imx5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index d7ce72252a4e6..c1c99a72c6a16 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -18,6 +18,7 @@ #include #include "hardware.h" +#include "common.h" static int mx5_cpu_rev = -1; From e9d8ab892eecf13bd60829c548e62d3dccfae3be Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:33 -0300 Subject: [PATCH 47/70] ARM: mach-imx: clk-pllv1: Staticize clk_pllv1_ops Fix the following sparse warning: arch/arm/mach-imx/clk-pllv1.c:81:16: warning: symbol 'clk_pllv1_ops' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c index abff350ba24ca..c1eaee3469542 100644 --- a/arch/arm/mach-imx/clk-pllv1.c +++ b/arch/arm/mach-imx/clk-pllv1.c @@ -78,7 +78,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, return ll; } -struct clk_ops clk_pllv1_ops = { +static struct clk_ops clk_pllv1_ops = { .recalc_rate = clk_pllv1_recalc_rate, }; From 191f162c40b4db205c12c25941a30f722ba0a4be Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:34 -0300 Subject: [PATCH 48/70] ARM: mach-imx: clk-pllv2: Staticize clk_pllv2_ops Fix the following sparse warning: rch/arm/mach-imx/clk-pllv2.c:232:16: warning: symbol 'clk_pllv2_ops' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c index 0440379e36284..20889d59b44d9 100644 --- a/arch/arm/mach-imx/clk-pllv2.c +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -229,7 +229,7 @@ static void clk_pllv2_unprepare(struct clk_hw *hw) __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); } -struct clk_ops clk_pllv2_ops = { +static struct clk_ops clk_pllv2_ops = { .prepare = clk_pllv2_prepare, .unprepare = clk_pllv2_unprepare, .recalc_rate = clk_pllv2_recalc_rate, From d7b8c030f6734fae1ef45b531a1fa26d64213b55 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:35 -0300 Subject: [PATCH 49/70] ARM: mach-imx: clk-gate2: Include "clk.h" Fix the following sparse warning: arch/arm/mach-imx/clk-gate2.c:86:12: warning: symbol 'clk_register_gate2' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-gate2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index cc49c7ae186ed..a63e415609a88 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -15,6 +15,7 @@ #include #include #include +#include "clk.h" /** * DOC: basic gatable clock which can gate and ungate it's ouput From bce344eae643663c087a976f9496d143d4d32a1e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:36 -0300 Subject: [PATCH 50/70] ARM: mach-imx: irq-common: Remove imx_irq_set_priority() imx_irq_set_priority() is not used anywhere, so remove it. This fixes the following sparse warnings: arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'imx_irq_set_priority' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/irq-common.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c index b6e11458e5aea..4b34f52dc46bc 100644 --- a/arch/arm/mach-imx/irq-common.c +++ b/arch/arm/mach-imx/irq-common.c @@ -21,25 +21,6 @@ #include "irq-common.h" -int imx_irq_set_priority(unsigned char irq, unsigned char prio) -{ - struct irq_chip_generic *gc; - struct mxc_extra_irq *exirq; - int ret; - - ret = -ENOSYS; - - gc = irq_get_chip_data(irq); - if (gc && gc->private) { - exirq = gc->private; - if (exirq->set_priority) - ret = exirq->set_priority(irq, prio); - } - - return ret; -} -EXPORT_SYMBOL(imx_irq_set_priority); - int mxc_set_irq_fiq(unsigned int irq, unsigned int type) { struct irq_chip_generic *gc; From e6d7e6ca953405dfd80c5fb72e3359c1633c0c43 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:37 -0300 Subject: [PATCH 51/70] ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops Fix the following sparse warning: arch/arm/mach-imx/clk-busy.c:150:16: warning: symbol 'clk_busy_mux_ops' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-busy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c index 1ab91b5209e65..6809c99abb406 100644 --- a/arch/arm/mach-imx/clk-busy.c +++ b/arch/arm/mach-imx/clk-busy.c @@ -147,7 +147,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index) return ret; } -struct clk_ops clk_busy_mux_ops = { +static struct clk_ops clk_busy_mux_ops = { .get_parent = clk_busy_mux_get_parent, .set_parent = clk_busy_mux_set_parent, }; From 41921c13c3d0434a8ea3466fa65d493816358787 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:38 -0300 Subject: [PATCH 52/70] ARM: mach-imx: clk: Include "clk.h" Fix the following sparse warning: arch/arm/mach-imx/clk.c:3:1: warning: symbol 'imx_ccm_lock' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c index f5e8be8e7f117..37e884ed1cd40 100644 --- a/arch/arm/mach-imx/clk.c +++ b/arch/arm/mach-imx/clk.c @@ -1,3 +1,4 @@ #include +#include "clk.h" DEFINE_SPINLOCK(imx_ccm_lock); From 516e89d7d5e5d321a8e0543cfb7f440f9942ce53 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 11:03:45 -0300 Subject: [PATCH 53/70] ARM: mach-imx: tzic: Staticize *tzic_base Fix the following sparse warning: arch/arm/mach-imx/tzic.c:52:14: warning: symbol 'tzic_base' was not declared. Should it be static? Also, remove the comment, as it does not apply for kernels newer than 3.2. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/tzic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c index 9721161f208f1..8183178d5aa33 100644 --- a/arch/arm/mach-imx/tzic.c +++ b/arch/arm/mach-imx/tzic.c @@ -49,7 +49,7 @@ #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ -void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ +static void __iomem *tzic_base; static struct irq_domain *domain; #define TZIC_NUM_IRQS 128 From ae00ac76faf51dcb9f9a8cda341ae4e6829314e6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:40 -0300 Subject: [PATCH 54/70] ARM: mach-imx: avic: Staticize *avic_base Fix the following sparse warning: arch/arm/mach-imx/avic.c:54:14: warning: symbol 'avic_base' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/avic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index 0eff23ed92b93..9c3e014705b19 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c @@ -51,7 +51,7 @@ #define AVIC_NUM_IRQS 64 -void __iomem *avic_base; +static void __iomem *avic_base; static struct irq_domain *domain; static u32 avic_saved_mask_reg[2]; From 9a67a6fd36fea1ab360249e4b7ef2d29d3e2fac8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:42 -0300 Subject: [PATCH 55/70] ARM: mach-imx: gpc: Include "common.h" Fix the following sparse warnings: arch/arm/mach-imx/gpc.c:29:6: warning: symbol 'imx_gpc_pre_suspend' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:43:6: warning: symbol 'imx_gpc_post_resume' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:71:6: warning: symbol 'imx_gpc_mask_all' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:83:6: warning: symbol 'imx_gpc_restore_all' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:122:13: warning: symbol 'imx_gpc_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/gpc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index a96ccc7f50123..02b61cdf39b97 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -16,6 +16,7 @@ #include #include #include +#include "common.h" #define GPC_IMR1 0x008 #define GPC_PGC_CPU_PDN 0x2a0 From 0989857625ba9d446916495f619435a3b42e7be4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:43 -0300 Subject: [PATCH 56/70] ARM: mach-imx: src: Include "common.h Fix the following sparse warnings: arch/arm/mach-imx/src.c:28:6: warning: symbol 'imx_enable_cpu' was not declared. Should it be static? arch/arm/mach-imx/src.c:39:6: warning: symbol 'imx_set_cpu_jump' was not declared. Should it be static? arch/arm/mach-imx/src.c:46:6: warning: symbol 'imx_src_prepare_restart' was not declared. Should it be static? arch/arm/mach-imx/src.c:59:13: warning: symbol 'imx_src_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/src.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index e15f1555c59b1..648634d9b6c39 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -16,6 +16,7 @@ #include #include #include +#include "common.h" #define SRC_SCR 0x000 #define SRC_GPR1 0x020 From f8c11b2b36a7a0f14ac98c4ca599151e1a720132 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Mar 2013 09:20:44 -0300 Subject: [PATCH 57/70] ARM: mach-imx: mach-imx6q: Fix sparse warnings Fix the following sparse warnings: arch/arm/mach-imx/mach-imx6q.c:60:6: warning: symbol 'imx6q_restart' was not declared. Should it be static? arch/arm/mach-imx/mach-imx6q.c:223:24: warning: symbol 'imx6q_cpufreq_pdev' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6q.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 9ffd103b27e4d..fe1b7aafabdcc 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -73,7 +73,7 @@ static int imx6q_revision(void) } } -void imx6q_restart(char mode, const char *cmd) +static void imx6q_restart(char mode, const char *cmd) { struct device_node *np; void __iomem *wdog_base; @@ -256,7 +256,7 @@ static void __init imx6q_opp_init(struct device *cpu_dev) of_node_put(np); } -struct platform_device imx6q_cpufreq_pdev = { +static struct platform_device imx6q_cpufreq_pdev = { .name = "imx6q-cpufreq", }; From 842db74a2b02d4caa07ece65a834e7715c419c23 Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Thu, 21 Mar 2013 22:36:09 +0100 Subject: [PATCH 58/70] ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" The Kconfig symbol MACH_OMAP_HTCWIZARD got added in v2.6.30. It has never been used. Its entry can safely be removed. Signed-off-by: Paul Bolle Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/Kconfig | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 903da8eb886c8..cdd05f2e67ee8 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -55,12 +55,6 @@ config MACH_OMAP_H3 TI OMAP 1710 H3 board support. Say Y here if you have such a board. -config MACH_OMAP_HTCWIZARD - bool "HTC Wizard" - depends on ARCH_OMAP850 - help - HTC Wizard smartphone support (AKA QTEK 9100, ...) - config MACH_HERALD bool "HTC Herald" depends on ARCH_OMAP850 From ce9df0b00ac7f0a733d361c23bebdd79f32f8adc Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Tue, 26 Mar 2013 00:30:05 +0100 Subject: [PATCH 59/70] ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" Commit 90173882ed15a8034d6d162da5f343a2c7d87587 ("omap: add dsp platform device") used CONFIG_BRIDGE_DVFS were it obviously meant CONFIG_TIDSPBRIDGE_DVFS. Fix that. Signed-off-by: Paul Bolle Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/dsp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index b155500e84a8e..b8208b4b1bd99 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -26,7 +26,7 @@ #include "control.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_TIDSPBRIDGE_DVFS #include "omap-pm.h" #endif @@ -35,7 +35,7 @@ static struct platform_device *omap_dsp_pdev; static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { -#ifdef CONFIG_BRIDGE_DVFS +#ifdef CONFIG_TIDSPBRIDGE_DVFS .dsp_set_min_opp = omap_pm_dsp_set_min_opp, .dsp_get_opp = omap_pm_dsp_get_opp, .cpu_set_freq = omap_pm_cpu_set_freq, From 4f5ef62ced8e7e01179de734856e03bddb06389c Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Fri, 22 Mar 2013 01:15:02 +0100 Subject: [PATCH 60/70] ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro Commit 2d66c7803595da0d4bcd949825d598575f5de9e6 ("cpuimx27 and mbimx27: allow fine control of UART4 and SDHC2 usage") added the Kconfig symbol MACH_EUKREA_CPUIMX27_USEUART4. But it forgot to prepend CONFIG_ to the use of its macro. Add that prefix now. Signed-off-by: Paul Bolle Signed-off-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 4 ++-- arch/arm/mach-imx/mach-cpuimx27.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index b4c70028d3599..b2f08bfbbdd39 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -46,7 +46,7 @@ static const int eukrea_mbimx27_pins[] __initconst = { PE10_PF_UART3_CTS, PE11_PF_UART3_RTS, /* UART4 */ -#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) +#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) PB26_AF_UART4_RTS, PB28_AF_UART4_TXD, PB29_AF_UART4_CTS, @@ -306,7 +306,7 @@ void __init eukrea_mbimx27_baseboard_init(void) imx27_add_imx_uart1(&uart_pdata); imx27_add_imx_uart2(&uart_pdata); -#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) +#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) imx27_add_imx_uart3(&uart_pdata); #endif diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 146559311bd28..ea50870bda807 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -48,7 +48,7 @@ static const int eukrea_cpuimx27_pins[] __initconst = { PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, /* UART4 */ -#if defined(MACH_EUKREA_CPUIMX27_USEUART4) +#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) PB26_AF_UART4_RTS, PB28_AF_UART4_TXD, PB29_AF_UART4_CTS, @@ -272,7 +272,7 @@ static void __init eukrea_cpuimx27_init(void) /* SDHC2 can be used for Wifi */ imx27_add_mxc_mmc(1, NULL); #endif -#if defined(MACH_EUKREA_CPUIMX27_USEUART4) +#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) /* in which case UART4 is also used for Bluetooth */ imx27_add_imx_uart3(&uart_pdata); #endif From 7e16063bb8f4c4f2e2b055659b40a319092e62da Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Tue, 9 Apr 2013 14:03:51 +0100 Subject: [PATCH 61/70] ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms The ARM perf core code used to rely on the pmu node being compatible with "arm,cortex-a9-pmu", even when the PMUs of the different Cortex-A processors are not really compatible... This is no longer required and actually became harmful, so remove all the offending values from Versatile Express DTS files. Signed-off-by: Pawel Moll Signed-off-by: Olof Johansson --- arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +- arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 73187173117c5..9420053acc146 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -117,7 +117,7 @@ }; pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; + compatible = "arm,cortex-a15-pmu"; interrupts = <0 68 4>, <0 69 4>; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index dfe371ec27498..d2803be4e1a8f 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -134,7 +134,7 @@ }; pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; + compatible = "arm,cortex-a15-pmu"; interrupts = <0 68 4>, <0 69 4>; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index 6328cbc71d300..c544a55045918 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -111,7 +111,7 @@ }; pmu { - compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; + compatible = "arm,cortex-a5-pmu"; interrupts = <0 68 4>, <0 69 4>; }; From 73a8c28f167c9e7bc42eafc0bcbd298031709430 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 10 Apr 2013 18:00:11 -0700 Subject: [PATCH 62/70] ARM: msm: Fix uncompess.h tx underrun check Bit 3 of the SR register is set if there is a tx underrun. If this bit isn't set, we should loop on the tx ready bit until we can transmit again. Otherwise we should skip the loop and transmit immediately. The code is doing the opposite though, checking for an underrun and then looping on the tx ready bit causing us to never loop on the tx read bit when the tx buffer may not be ready. This doesn't seem to affect my 8960 device too often, but in some cases I see a lost character or two from the decompressor prints. This also matches what we do in the assembly in debug-macro.S. Signed-off-by: Stephen Boyd Signed-off-by: David Brown --- arch/arm/mach-msm/include/mach/uncompress.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h index fa97a10d86951..94324870fb04a 100644 --- a/arch/arm/mach-msm/include/mach/uncompress.h +++ b/arch/arm/mach-msm/include/mach/uncompress.h @@ -37,7 +37,7 @@ static void putc(int c) * Wait for TX_READY to be set; but skip it if we have a * TX underrun. */ - if (UART_DM_SR & 0x08) + if (!(UART_DM_SR & 0x08)) while (!(UART_DM_ISR & 0x80)) cpu_relax(); From 5777b4b5778b9b44ee8b1476521ffcb8e527876d Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Mon, 15 Apr 2013 16:50:53 -0600 Subject: [PATCH 63/70] ARM: tegra: fix build error when THUMB2_KERNEL enabled This patch fix the build failure when CONFIG_THUBM2_KERNEL enabled. You clould see the error message below: arch/arm/mach-tegra/sleep-tegra30.S:69: Error: shift must be constant -- `orr r12,r12,r4,lsl r3' Reported-by: Arnd Bergmann Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren Reviewed-by: Dave Martin Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/sleep-tegra30.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 63a15bd9b6530..d29dfcce948d2 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -66,7 +66,9 @@ ENTRY(tegra30_cpu_shutdown) FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ FLOW_CTRL_CSR_ENABLE mov r4, #(1 << 4) - orr r12, r12, r4, lsl r3 + ARM( orr r12, r12, r4, lsl r3 ) + THUMB( lsl r4, r4, r3 ) + THUMB( orr r12, r12, r4 ) str r12, [r1] /* Halt this CPU. */ From a65dc10ffad1e041b4ad3559a026a8bb2b40b77e Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Mon, 15 Apr 2013 16:50:54 -0600 Subject: [PATCH 64/70] ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled The conditional branch instruction in Thumb2 only available to short range. The linker will fail when the conditional branch over the range. Then resulting in link error when generating kernel image. e.g.: arch/arm/mach-tegra/reset-handler.S:47:(.text+0xf8e): relocation truncated to fit: R_ARM_THM_JUMP19 against symbol `cpu_resume' defined in .data section in arch/arm/kernel/built-in.o This patch using a Thumb2 instruction IT (if-then) to have a longer branch range. Reported-by: Arnd Bergmann Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren Reviewed-by: Dave Martin Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/reset-handler.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 1676aba5e7b84..e6de88a2ea06c 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -44,6 +44,7 @@ ENTRY(tegra_resume) cpu_id r0 cmp r0, #0 @ CPU0? + THUMB( it ne ) bne cpu_resume @ no #ifdef CONFIG_ARCH_TEGRA_3x_SOC From c312908a10677cc866b2473f4f3fabb448bdfb64 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 16 Apr 2013 11:09:09 -0600 Subject: [PATCH 65/70] ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled When building the kernel with CONFIG_THUMB2_KERNEL enabled, older assemblers may emit the following error: reset-handler.S:78: Error: invalid immediate for address calculation (value = 0x00000004) Using an explicit adr.w instruction will solve this. Newer assemblers do this automatically. Use the W() macro to do this under Thumb mode only. Inspired-by: Joseph Lo Suggested-by: Dave Martin Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/mach-tegra/sleep.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4ffae541726e1..bb308eab9079a 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -92,7 +92,7 @@ #ifdef CONFIG_CACHE_L2X0 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs - adr \tmp1, \phys_l2x0_saved_regs + W(adr) \tmp1, \phys_l2x0_saved_regs ldr \tmp1, [\tmp1] ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] ldr \tmp3, [\tmp2, #L2X0_CTRL] From 4b0ed6967ef2ba4ff18d9a905c8dbdff29e02d10 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 23 Apr 2013 15:30:51 +0200 Subject: [PATCH 66/70] ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7 CONFIG_ARCH_OMAP2PLUS depends on (ARCH_MULTI_V6 || ARCH_MULTI_V7) as of a0694861 "ARM: OMAP2+: Enable ARCH_MULTIPLATFORM support", but the individual OMAP2/3/4/5 and AM33XX platforms can all be selected independent of what we are building for, which is a bug and prevents us from easily building e.g. an ARMv7-only defconfig. This makes ARCH_OMAP2 depend on ARCH_MULTI_V6 and the others depend on ARCH_MULTI_V7, to ensure we really only build the platforms for the CPUs we have enabled in the global multiplatform configuration step. Cc: Ezequiel Garcia Acked-by: Tony Lindgren Signed-off-by: Arnd Bergmann --- arch/arm/mach-omap2/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b9c0ed3f648c8..4dc34ae6a857d 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -55,6 +55,7 @@ config SOC_HAS_REALTIME_COUNTER config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_OMAP2PLUS + depends on ARCH_MULTI_V6 default y select CPU_V6 select MULTI_IRQ_HANDLER @@ -64,6 +65,7 @@ config ARCH_OMAP2 config ARCH_OMAP3 bool "TI OMAP3" depends on ARCH_OMAP2PLUS + depends on ARCH_MULTI_V7 default y select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM @@ -80,6 +82,7 @@ config ARCH_OMAP4 bool "TI OMAP4" default y depends on ARCH_OMAP2PLUS + depends on ARCH_MULTI_V7 select ARCH_HAS_OPP select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_CPU_SUSPEND if PM @@ -99,6 +102,7 @@ config ARCH_OMAP4 config SOC_OMAP5 bool "TI OMAP5" + depends on ARCH_MULTI_V7 select ARM_CPU_SUSPEND if PM select ARM_GIC select CPU_V7 @@ -135,6 +139,7 @@ config SOC_TI81XX config SOC_AM33XX bool "AM33XX support" + depends on ARCH_MULTI_V7 default y select ARM_CPU_SUSPEND if PM select CPU_V7 From 0259d9eb30d003af305626db2d8332805696e60d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 26 Apr 2013 15:29:55 +0200 Subject: [PATCH 67/70] ARM: u300: fix ages old copy/paste bug The UART1 is on the fast AHB bridge, not on the slow bus. Cc: stable@vger.kernel.org Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/mach-u300/include/mach/u300-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h index 1e49d901f2c92..0320495efc4d6 100644 --- a/arch/arm/mach-u300/include/mach/u300-regs.h +++ b/arch/arm/mach-u300/include/mach/u300-regs.h @@ -95,7 +95,7 @@ #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) /* Fast UART1 on U335 only */ -#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) +#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000) /* * SLOW peripherals From 2058842e6d7833e41be7cc2434465e69bcd51d45 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 23 Apr 2013 15:36:26 +0200 Subject: [PATCH 68/70] ARM: tegra: call cpu_do_idle from C code When building a kernel for multiple CPU architecture levels, cpu_do_idle() is a macro for an indirect function call, which cannot be called from assembly code as Tegra does. Adding a trivial C wrapper for this function lets us build a tegra kernel with ARMv6 support enabled. Signed-off-by: Arnd Bergmann Acked-by: Joseph Lo Cc: Stephen Warren --- arch/arm/mach-tegra/pm.c | 5 +++++ arch/arm/mach-tegra/sleep-tegra20.S | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 0494f739c95f9..04a8e06f59a91 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -162,6 +162,11 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id) return last_cpu; } +int tegra_cpu_do_idle(void) +{ + return cpu_do_idle(); +} + static int tegra_sleep_cpu(unsigned long v2p) { /* Switch to the identity mapping. */ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 9f6bfafdd5121..e3f2417c420e2 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -197,7 +197,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) mov r3, #CPU_RESETTABLE str r3, [r0] - bl cpu_do_idle + bl tegra_cpu_do_idle /* * cpu may be reset while in wfi, which will return through From 7b2fea1ca77fdfd5154ce0f39fca3f6f335505e8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 25 Apr 2013 17:10:04 +0200 Subject: [PATCH 69/70] ARM: orion5x: include linux/cpu.h The linux/cpu.h header is no longer implictly included in this file, so we need to an #include statement to avoid this build warning: arch/arm/mach-orion5x/common.c:339:3: error: implicit declaration of function 'cpu_idle_poll_ctrl' [-Werror=implicit-function-declaration] Signed-off-by: Arnd Bergmann Acked-by: Jason Cooper Cc: Andrew Lunn --- arch/arm/mach-orion5x/common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index d068f1431c402..e13d7732cfe96 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include From e74fc973b6e531fef1fce8b101ffff05ecfb774c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 15 Feb 2013 21:23:58 +0100 Subject: [PATCH 70/70] Turn off -Wmaybe-uninitialized when building with -Os gcc-4.7 and higher add a lot of false positive warnings about potential uses of uninitialized warnings, but only when optimizing for size (-Os). This is the default when building allyesconfig, which turns on CONFIG_CC_OPTIMIZE_FOR_SIZE. In order to avoid getting a lot of patches that initialize such variables and accidentally hide real errors along the way, let's just turn off this warning on the respective gcc versions when building with size optimizations. The -Wmaybe-uninitialized option was introduced in the same gcc version (4.7) that is now causing the false positives, so there is no effect on older compilers. A side effect is that when building with CONFIG_CC_OPTIMIZE_FOR_SIZE, we might now see /fewer/ warnings about possibly uninitialized warnings than with -O2, but that is still much better than seeing warnings known to be bogus. Signed-off-by: Arnd Bergmann --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 58a165b02af1e..8004421a93d13 100644 --- a/Makefile +++ b/Makefile @@ -570,7 +570,7 @@ endif # $(dot-config) all: vmlinux ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE -KBUILD_CFLAGS += -Os +KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) else KBUILD_CFLAGS += -O2 endif