ARM: dts: Add missing smartreflex node and binding for omap4

We are missing smartreflex device tree nodes for omap4 with
their related "ti,hwmods" properties that the SoC interconnect
code needs.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

And since we're missing the device tree binding for smartreflex,
let's also add it and document the existing omap3 use too.

Note that the related driver also needs to be updated to probe
using device tree and get the platform data passed to it using
auxdata with arch/arm/mach-omap2/pdata-quirks.c.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Documentation/devicetree/bindings/power/ti-smartreflex.txt

@@ -0,0 +1,47 @@
+Texas Instruments SmartReflex binding
+
+SmartReflex is used to set and adjust the SoC operating points.
+
+
+Required properties:
+
+compatible: Shall be one of the following:
+	    "ti,omap3-smartreflex-core"
+	    "ti,omap3-smartreflex-iva"
+	    "ti,omap4-smartreflex-core"
+	    "ti,omap4-smartreflex-mpu"
+	    "ti,omap4-smartreflex-iva"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+	   by the SoC
+
+
+Example:
+
+	smartreflex_iva: smartreflex@4a0db000 {
+		compatible = "ti,omap4-smartreflex-iva";
+		reg = <0x4a0db000 0x80>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "smartreflex_iva";
+	};
+
+	smartreflex_core: smartreflex@4a0dd000 {
+		compatible = "ti,omap4-smartreflex-core";
+		reg = <0x4a0dd000 0x80>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "smartreflex_core";
+	};
+
+	smartreflex_mpu: smartreflex@4a0d9000 {
+		compatible = "ti,omap4-smartreflex-mpu";
+		reg = <0x4a0d9000 0x80>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		ti,hwmods = "smartreflex_mpu";
+	};

arch/arm/boot/dts/omap4.dtsi

@@ -442,6 +442,27 @@
 			clock-frequency = <48000000>;
 		};
 
+		smartreflex_iva: smartreflex@4a0db000 {
+			compatible = "ti,omap4-smartreflex-iva";
+			reg = <0x4a0db000 0x80>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "smartreflex_iva";
+		};
+
+		smartreflex_core: smartreflex@4a0dd000 {
+			compatible = "ti,omap4-smartreflex-core";
+			reg = <0x4a0dd000 0x80>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "smartreflex_core";
+		};
+
+		smartreflex_mpu: smartreflex@4a0d9000 {
+			compatible = "ti,omap4-smartreflex-mpu";
+			reg = <0x4a0d9000 0x80>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "smartreflex_mpu";
+		};
+
 		hwspinlock: spinlock@4a0f6000 {
 			compatible = "ti,omap4-hwspinlock";
 			reg = <0x4a0f6000 0x1000>;