From 0be123cafc06eed0fd1227166a66e786434b0c50 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:10 +0100 Subject: [PATCH 01/27] drm/mediatek: mtk_hdmi: Unregister audio platform device on failure The probe function of this driver may fail after registering the audio platform device: in that case, the state is not getting cleaned up, leaving this device registered. Adding up to the mix, should the probe function of this driver return a probe deferral for N times, we're registering up to N audio platform devices and, again, never freeing them up. To fix this, add a pointer to the audio platform device in the mtk_hdmi structure, and add a devm action to unregister it upon driver removal or probe failure. Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-18-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index ca82bc829cb96..1018a9a7433f9 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -173,6 +173,7 @@ struct mtk_hdmi { unsigned int sys_offset; void __iomem *regs; enum hdmi_colorspace csp; + struct platform_device *audio_pdev; struct hdmi_audio_param aud_param; bool audio_enable; bool powered; @@ -1662,6 +1663,11 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, }; +static void mtk_hdmi_unregister_audio_driver(void *data) +{ + platform_device_unregister(data); +} + static int mtk_hdmi_register_audio_driver(struct device *dev) { struct mtk_hdmi *hdmi = dev_get_drvdata(dev); @@ -1672,13 +1678,20 @@ static int mtk_hdmi_register_audio_driver(struct device *dev) .data = hdmi, .no_capture_mute = 1, }; - struct platform_device *pdev; + int ret; - pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, - PLATFORM_DEVID_AUTO, &codec_data, - sizeof(codec_data)); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); + hdmi->audio_pdev = platform_device_register_data(dev, + HDMI_CODEC_DRV_NAME, + PLATFORM_DEVID_AUTO, + &codec_data, + sizeof(codec_data)); + if (IS_ERR(hdmi->audio_pdev)) + return PTR_ERR(hdmi->audio_pdev); + + ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver, + hdmi->audio_pdev); + if (ret) + return ret; DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); return 0; From 72fcb88e7bbc053ed4fc74cebb0315b98a0f20c3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:12 +0100 Subject: [PATCH 02/27] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member Rename member aud_sampe_size of struct hdmi_audio_param to aud_sample_size to fix a typo and enhance readability. This commit brings no functional changes. Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-20-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 1018a9a7433f9..250ad0d4027d6 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -137,7 +137,7 @@ enum hdmi_aud_channel_swap_type { struct hdmi_audio_param { enum hdmi_audio_coding_type aud_codec; - enum hdmi_audio_sample_size aud_sampe_size; + enum hdmi_audio_sample_size aud_sample_size; enum hdmi_aud_input_type aud_input_type; enum hdmi_aud_i2s_fmt aud_i2s_fmt; enum hdmi_aud_mclk aud_mclk; @@ -1075,7 +1075,7 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) hdmi->csp = HDMI_COLORSPACE_RGB; aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; - aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; + aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; @@ -1573,14 +1573,14 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, switch (daifmt->fmt) { case HDMI_I2S: hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; - hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; + hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; break; case HDMI_SPDIF: hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; - hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; + hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; break; default: From 471a9c224bf2942fdc1c163396c66527690e7f8c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:09 +0100 Subject: [PATCH 03/27] drm/mediatek: mtk_hdmi: Compress of_device_id array entries Compress the entries found in the of_device_id array to improve readability of this file and to make that consistent with other kernel drivers. Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-17-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 250ad0d4027d6..892bfbccf754b 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1794,15 +1794,10 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = { }; static const struct of_device_id mtk_hdmi_of_ids[] = { - { .compatible = "mediatek,mt2701-hdmi", - .data = &mtk_hdmi_conf_mt2701, - }, - { .compatible = "mediatek,mt8167-hdmi", - .data = &mtk_hdmi_conf_mt8167, - }, - { .compatible = "mediatek,mt8173-hdmi", - }, - {} + { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 }, + { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 }, + { .compatible = "mediatek,mt8173-hdmi" }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids); From e2e4f07f0661b070383d386746dafaa863cec99c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:17 +0100 Subject: [PATCH 04/27] drm/mediatek: mtk_hdmi: Move vendor/product strings to drm_bridge Move the vendor and product strings to the appropriate entries of struct drm_bridge and use that in mtk_hdmi_setup_spd_infoframe instead of having the same as function parameters. While at it, also beautify the strings, setting them to read "MediaTek On-Chip HDMI". Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-25-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 892bfbccf754b..f5979b9367e87 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -988,15 +988,14 @@ static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, return 0; } -static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, - const char *vendor, - const char *product) +static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi) { + struct drm_bridge *bridge = &hdmi->bridge; struct hdmi_spd_infoframe frame; u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; ssize_t err; - err = hdmi_spd_infoframe_init(&frame, vendor, product); + err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product); if (err < 0) { dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", err); @@ -1378,7 +1377,7 @@ static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, { mtk_hdmi_setup_audio_infoframe(hdmi); mtk_hdmi_setup_avi_infoframe(hdmi, mode); - mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); + mtk_hdmi_setup_spd_infoframe(hdmi); if (mode->flags & DRM_MODE_FLAG_3D_MASK) mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); } @@ -1737,6 +1736,8 @@ static int mtk_hdmi_probe(struct platform_device *pdev) hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + hdmi->bridge.vendor = "MediaTek"; + hdmi->bridge.product = "On-Chip HDMI"; drm_bridge_add(&hdmi->bridge); ret = mtk_hdmi_clk_enable_audio(hdmi); From 89dcc9e0becd2633df983e66845d7192def445df Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:20 +0100 Subject: [PATCH 05/27] drm/mediatek: mtk_hdmi: Remove unused members of struct mtk_hdmi The hdmi_colorspace csp member of struct mtk_hdmi is initialized once but then it's never used at all. Remove said member and the only assignment to it as a cleanup. Also remove the ibias, ibias_up, min_clock, max_clock, min_hdisplay and max_vdisplay members, as those were really completely unused. This commit brings no functional changes. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-28-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index f5979b9367e87..2d24fcadce6ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -163,16 +163,9 @@ struct mtk_hdmi { struct clk *clk[MTK_HDMI_CLK_COUNT]; struct drm_display_mode mode; bool dvi_mode; - u32 min_clock; - u32 max_clock; - u32 max_hdisplay; - u32 max_vdisplay; - u32 ibias; - u32 ibias_up; struct regmap *sys_regmap; unsigned int sys_offset; void __iomem *regs; - enum hdmi_colorspace csp; struct platform_device *audio_pdev; struct hdmi_audio_param aud_param; bool audio_enable; @@ -1072,7 +1065,6 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) { struct hdmi_audio_param *aud_param = &hdmi->aud_param; - hdmi->csp = HDMI_COLORSPACE_RGB; aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; From eb8779b2641374c140c7e55f251900d71837759f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:22 +0100 Subject: [PATCH 06/27] drm/mediatek: mtk_hdmi: Use devm managed version of drm_bridge_add Simplify the probe/remove functions by using devm_drm_bridge_add() as now there is no more need to manually remove the bridge. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-30-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 2d24fcadce6ba..4035666f8f6a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1730,14 +1730,15 @@ static int mtk_hdmi_probe(struct platform_device *pdev) hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; hdmi->bridge.vendor = "MediaTek"; hdmi->bridge.product = "On-Chip HDMI"; - drm_bridge_add(&hdmi->bridge); + + ret = devm_drm_bridge_add(dev, &hdmi->bridge); + if (ret) + return dev_err_probe(dev, ret, "Failed to add bridge\n"); ret = mtk_hdmi_clk_enable_audio(hdmi); - if (ret) { - drm_bridge_remove(&hdmi->bridge); + if (ret) return dev_err_probe(dev, ret, "Failed to enable audio clocks\n"); - } return 0; } @@ -1746,7 +1747,6 @@ static void mtk_hdmi_remove(struct platform_device *pdev) { struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); - drm_bridge_remove(&hdmi->bridge); mtk_hdmi_clk_disable_audio(hdmi); } From 900f5b37a93d19820398a2cb9e5bb36f506344bf Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:23 +0100 Subject: [PATCH 07/27] drm/mediatek: mtk_hdmi: Remove ifdef for CONFIG_PM_SLEEP Since the SIMPLE_DEV_PM_OPS macro and the pm pointer are anyway defined when CONFIG_PM_SLEEP is not set, remove the ifdef for it and indicate that the mtk_hdmi_{remove,suspend} functions may be unused (as they are, in case PM support is not built-in). While at it, to improve readability, also compress the SIMPLE_DEV_PM_OPS declaration as it even fits in less than 80 columns. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-31-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 4035666f8f6a1..2ff025e9151bd 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1750,8 +1750,7 @@ static void mtk_hdmi_remove(struct platform_device *pdev) mtk_hdmi_clk_disable_audio(hdmi); } -#ifdef CONFIG_PM_SLEEP -static int mtk_hdmi_suspend(struct device *dev) +static __maybe_unused int mtk_hdmi_suspend(struct device *dev) { struct mtk_hdmi *hdmi = dev_get_drvdata(dev); @@ -1760,7 +1759,7 @@ static int mtk_hdmi_suspend(struct device *dev) return 0; } -static int mtk_hdmi_resume(struct device *dev) +static __maybe_unused int mtk_hdmi_resume(struct device *dev) { struct mtk_hdmi *hdmi = dev_get_drvdata(dev); int ret = 0; @@ -1773,9 +1772,8 @@ static int mtk_hdmi_resume(struct device *dev) return 0; } -#endif -static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, - mtk_hdmi_suspend, mtk_hdmi_resume); + +static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume); static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = { .tz_disabled = true, From bc3cbc0cf0f3a28afcd5f02b45697706241cf102 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:24 +0100 Subject: [PATCH 08/27] drm/mediatek: mtk_hdmi: Remove goto in mtk_hdmi_clk_enable_audio() If the clk_prepare_enable() call for the SPDIF clock fails, just disable and unprepare the clock in the error check branch and return immediately instead of jumping to the end with a goto, slightly reducing code size. This commit brings no functional changes. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-32-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 2ff025e9151bd..aa4009156ae58 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1159,13 +1159,12 @@ static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) return ret; ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); - if (ret) - goto err; + if (ret) { + clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); + return ret; + } return 0; -err: - clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); - return ret; } static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) From cb288d20c4d543dd1ca223140fa72ca341a5f7af Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:25 +0100 Subject: [PATCH 09/27] drm/mediatek: mtk_hdmi: Remove driver bound to HDMI print Remove the "driver bound to HDMI" print to avoid useless spam in the kernel log, as registered and bound drivers can be debugged through debugfs. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-33-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index aa4009156ae58..eea3fbf2e2f61 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1683,7 +1683,6 @@ static int mtk_hdmi_register_audio_driver(struct device *dev) if (ret) return ret; - DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); return 0; } From 32bff1c70914f9cea6dda7dc7b0b9c0b5b7af690 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:26 +0100 Subject: [PATCH 10/27] drm/mediatek: mtk_hdmi: Cleanup function mtk_hdmi_resume() Remove the error print in case of mtk_hdmi_clk_enable_audio() failures: since the APIs will already print on their own, having one in there is redundant. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20250217154836.108895-34-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index eea3fbf2e2f61..b899a05628bdd 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1760,15 +1760,8 @@ static __maybe_unused int mtk_hdmi_suspend(struct device *dev) static __maybe_unused int mtk_hdmi_resume(struct device *dev) { struct mtk_hdmi *hdmi = dev_get_drvdata(dev); - int ret = 0; - ret = mtk_hdmi_clk_enable_audio(hdmi); - if (ret) { - dev_err(dev, "hdmi resume failed!\n"); - return ret; - } - - return 0; + return mtk_hdmi_clk_enable_audio(hdmi); } static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume); From 410462230a10b8a34c671b6dd9e52b4afe85fca7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:47:54 +0100 Subject: [PATCH 11/27] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat Add compatibles for the Digital Parallel Interface (DPI) block found in the MT8195 and MT8188 SoCs: inside of the chip, this one is directly connected to the HDMI block. Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-2-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 0f1e556dc8ef3..5670715efa5c5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8188-dp-intf - mediatek,mt8192-dpi - mediatek,mt8195-dp-intf + - mediatek,mt8195-dpi - items: - enum: - mediatek,mt6795-dpi @@ -35,6 +36,10 @@ properties: - enum: - mediatek,mt8365-dpi - const: mediatek,mt8192-dpi + - items: + - enum: + - mediatek,mt8188-dpi + - const: mediatek,mt8195-dpi reg: maxItems: 1 From 1deb6ed55ab1322e917cf48647274e72466ba046 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:47:55 +0100 Subject: [PATCH 12/27] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs This IP includes a Pattern Generator which is useful for debugging and testing purposes: add the relevant register and bits to the mtk_dpi_regs.h header, and implement support for it in mtk_dpi. Adding this required to introduce a .debugfs_init() callback for the DPI bridge, which creates a "dpi_test_pattern" file in the directory of the appropriate connector. The pattern generator can generate various internal patterns and this submission includes support for: - 256 or 1024 shades of gray in a Vertical or Horizontal Pattern - Vertical Color Bars - Frame border - Dot Moire This generator also supports filling the entire screen with one custom color, but support for that is not included in this commit. Enabling and disabling this generator can be done by sending a string to the dpi_test_pattern debugfs file; the pattern is expected to be formatted as follows: where the pattern number can be a number from 0 to 7, excluding 5. Of course 5 is excluded because that activates custom color fill which, again, is not supported in this commit. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-3-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 108 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 4 + 2 files changed, 112 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 1864eb02dbf50..fc937490feda7 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -4,8 +4,10 @@ * Author: Jie Qiu */ +#include #include #include +#include #include #include #include @@ -166,6 +168,18 @@ static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) writel(tmp, dpi->regs + offset); } +static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable) +{ + u32 val; + + if (enable) + val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN; + else + val = 0; + + mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN); +} + static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) { mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); @@ -767,6 +781,99 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, return MODE_OK; } +static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg) +{ + struct mtk_dpi *dpi = m->private; + bool en; + u32 val; + + if (!dpi) + return -EINVAL; + + val = readl(dpi->regs + DPI_PATTERN0); + en = val & DPI_PAT_EN; + val = FIELD_GET(DPI_PAT_SEL, val); + + seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled"); + + if (en) { + seq_printf(m, "Internal pattern %d: ", val); + switch (val) { + case 0: + seq_puts(m, "256 Vertical Gray\n"); + break; + case 1: + seq_puts(m, "1024 Vertical Gray\n"); + break; + case 2: + seq_puts(m, "256 Horizontal Gray\n"); + break; + case 3: + seq_puts(m, "1024 Horizontal Gray\n"); + break; + case 4: + seq_puts(m, "Vertical Color bars\n"); + break; + case 6: + seq_puts(m, "Frame border\n"); + break; + case 7: + seq_puts(m, "Dot moire\n"); + break; + default: + seq_puts(m, "Invalid selection\n"); + break; + } + } + + return 0; +} + +static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + u32 en, type; + char buf[6]; + + if (!m || !m->private || *offp || len > sizeof(buf) - 1) + return -EINVAL; + + memset(buf, 0, sizeof(buf)); + if (copy_from_user(buf, ubuf, len)) + return -EFAULT; + + if (sscanf(buf, "%u %u", &en, &type) != 2) + return -EINVAL; + + if (en < 0 || en > 1 || type < 0 || type > 7) + return -EINVAL; + + mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en); + return len; +} + +static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file) +{ + return single_open(file, mtk_dpi_debug_tp_show, inode->i_private); +} + +static const struct file_operations mtk_dpi_debug_tp_fops = { + .owner = THIS_MODULE, + .open = mtk_dpi_debug_tp_open, + .read = seq_read, + .write = mtk_dpi_debug_tp_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root) +{ + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops); +} + static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .attach = mtk_dpi_bridge_attach, .mode_set = mtk_dpi_bridge_mode_set, @@ -779,6 +886,7 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .debugfs_init = mtk_dpi_debugfs_init, }; void mtk_dpi_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 62bd4931b344e..a0b1d18bbbf7e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -235,4 +235,8 @@ #define MATRIX_SEL_RGB_TO_JPEG 0 #define MATRIX_SEL_RGB_TO_BT601 2 +#define DPI_PATTERN0 0xf00 +#define DPI_PAT_EN BIT(0) +#define DPI_PAT_SEL GENMASK(6, 4) + #endif /* __MTK_DPI_REGS_H */ From 9f163874b30ab8cd74d3858f557d0be52d3b1969 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:47:56 +0100 Subject: [PATCH 13/27] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation Setting the TVD PLL clock requires to multiply the target pixel clock by a specific constant factor to achieve the target PLL frequency, and this is done to reduce jitter to acceptable levels. On all MediaTek SoCs, the factor is not retrieved by any real kind of calculation but rather by checking if the target pixel clock is less than a specified frequency, hence assigning a function pointer for just a bunch of if branches does enlarge the code size for little reason. Remove all SoC-specific functions, add a structure `mtk_dpi_factor` that holds a clock frequency and corresponding PLL factor, and declare the constraints for each SoC in form of an array of said structure. Instead of function pointers, this structure (and its size) is then assigned to each SoC's platform data. The "calculation" is then performed with a new static function mtk_dpi_calculate_factor(dpi, mode_clk) that iterates through all of the entries of the aforementioned array and returns the right factor. If no factor is found, the lowest possible factor is returned, mimicking the same flow as all of the old per-SoC calculation functions. This commit brings no functional change. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-4-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 103 +++++++++++++++-------------- 1 file changed, 52 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index fc937490feda7..df350dd9994e7 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -118,9 +118,15 @@ struct mtk_dpi_yc_limit { u16 c_bottom; }; +struct mtk_dpi_factor { + u32 clock; + u8 factor; +}; + /** * struct mtk_dpi_conf - Configuration of mediatek dpi. - * @cal_factor: Callback function to calculate factor value. + * @dpi_factor: SoC-specific pixel clock PLL factor values. + * @num_dpi_factor: Number of pixel clock PLL factor values. * @reg_h_fre_con: Register address of frequency control. * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. * @edge_sel_en: Enable of edge selection. @@ -141,7 +147,8 @@ struct mtk_dpi_yc_limit { * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. */ struct mtk_dpi_conf { - unsigned int (*cal_factor)(int clock); + const struct mtk_dpi_factor *dpi_factor; + const u8 num_dpi_factor; u32 reg_h_fre_con; u32 max_clock_khz; bool edge_sel_en; @@ -516,6 +523,20 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return ret; } +static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk) +{ + const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor; + int i; + + for (i = 0; i < dpi->conf->num_dpi_factor; i++) { + if (mode_clk <= dpi_factor[i].clock) + return dpi_factor[i].factor; + } + + /* If no match try the lowest possible factor */ + return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; +} + static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { @@ -530,7 +551,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, unsigned int factor; /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ - factor = dpi->conf->cal_factor(mode->clock); + factor = mtk_dpi_calculate_factor(dpi, mode->clock); drm_display_mode_to_videomode(mode, &vm); pll_rate = vm.pixelclock * factor; @@ -965,48 +986,6 @@ static const struct component_ops mtk_dpi_component_ops = { .unbind = mtk_dpi_unbind, }; -static unsigned int mt8173_calculate_factor(int clock) -{ - if (clock <= 27000) - return 3 << 4; - else if (clock <= 84000) - return 3 << 3; - else if (clock <= 167000) - return 3 << 2; - else - return 3 << 1; -} - -static unsigned int mt2701_calculate_factor(int clock) -{ - if (clock <= 64000) - return 4; - else if (clock <= 128000) - return 2; - else - return 1; -} - -static unsigned int mt8183_calculate_factor(int clock) -{ - if (clock <= 27000) - return 8; - else if (clock <= 167000) - return 4; - else - return 2; -} - -static unsigned int mt8195_dpintf_calculate_factor(int clock) -{ - if (clock < 70000) - return 4; - else if (clock < 200000) - return 2; - else - return 1; -} - static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -1021,8 +1000,25 @@ static const u32 mt8195_output_fmts[] = { MEDIA_BUS_FMT_YUYV8_1X16, }; +static const struct mtk_dpi_factor dpi_factor_mt2701[] = { + { 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 } +}; + +static const struct mtk_dpi_factor dpi_factor_mt8173[] = { + { 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 } +}; + +static const struct mtk_dpi_factor dpi_factor_mt8183[] = { + { 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 } +}; + +static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = { + { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 } +}; + static const struct mtk_dpi_conf mt8173_conf = { - .cal_factor = mt8173_calculate_factor, + .dpi_factor = dpi_factor_mt8173, + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173), .reg_h_fre_con = 0xe0, .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, @@ -1039,7 +1035,8 @@ static const struct mtk_dpi_conf mt8173_conf = { }; static const struct mtk_dpi_conf mt2701_conf = { - .cal_factor = mt2701_calculate_factor, + .dpi_factor = dpi_factor_mt2701, + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701), .reg_h_fre_con = 0xb0, .edge_sel_en = true, .max_clock_khz = 150000, @@ -1057,7 +1054,8 @@ static const struct mtk_dpi_conf mt2701_conf = { }; static const struct mtk_dpi_conf mt8183_conf = { - .cal_factor = mt8183_calculate_factor, + .dpi_factor = dpi_factor_mt8183, + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), .reg_h_fre_con = 0xe0, .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, @@ -1074,7 +1072,8 @@ static const struct mtk_dpi_conf mt8183_conf = { }; static const struct mtk_dpi_conf mt8186_conf = { - .cal_factor = mt8183_calculate_factor, + .dpi_factor = dpi_factor_mt8183, + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), .reg_h_fre_con = 0xe0, .max_clock_khz = 150000, .output_fmts = mt8183_output_fmts, @@ -1092,7 +1091,8 @@ static const struct mtk_dpi_conf mt8186_conf = { }; static const struct mtk_dpi_conf mt8192_conf = { - .cal_factor = mt8183_calculate_factor, + .dpi_factor = dpi_factor_mt8183, + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183), .reg_h_fre_con = 0xe0, .max_clock_khz = 150000, .output_fmts = mt8183_output_fmts, @@ -1109,7 +1109,8 @@ static const struct mtk_dpi_conf mt8192_conf = { }; static const struct mtk_dpi_conf mt8195_dpintf_conf = { - .cal_factor = mt8195_dpintf_calculate_factor, + .dpi_factor = dpi_factor_mt8195_dp_intf, + .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), .max_clock_khz = 600000, .output_fmts = mt8195_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), From 41180dedcfa36768e2e8e8c7c113c964d252d0a5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:47:57 +0100 Subject: [PATCH 14/27] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function In preparation for adding support for the DPI IP found in MT8195 and in MT8188 used for HDMI, move the code flow for calculation and setting of the DPI pixel clock to a separate function called mtk_dpi_set_pixel_clk(). This was done because, on those platforms, the DPI instance that is used for HDMI will get its pixel clock from the HDMI clock, hence it is not necessary, nor desirable, to calculate or set the pixel clock in DPI. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-5-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 45 +++++++++++++++++------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index df350dd9994e7..59c2e4f32a611 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -537,26 +537,17 @@ static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk) return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; } -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, - struct drm_display_mode *mode) +static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk) { - struct mtk_dpi_polarities dpi_pol; - struct mtk_dpi_sync_param hsync; - struct mtk_dpi_sync_param vsync_lodd = { 0 }; - struct mtk_dpi_sync_param vsync_leven = { 0 }; - struct mtk_dpi_sync_param vsync_rodd = { 0 }; - struct mtk_dpi_sync_param vsync_reven = { 0 }; - struct videomode vm = { 0 }; unsigned long pll_rate; unsigned int factor; /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ - factor = mtk_dpi_calculate_factor(dpi, mode->clock); - drm_display_mode_to_videomode(mode, &vm); - pll_rate = vm.pixelclock * factor; + factor = mtk_dpi_calculate_factor(dpi, mode_clk); + pll_rate = vm->pixelclock * factor; dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm.pixelclock); + pll_rate, vm->pixelclock); clk_set_rate(dpi->tvd_clk, pll_rate); pll_rate = clk_get_rate(dpi->tvd_clk); @@ -566,20 +557,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, * pixels for each iteration: divide the clock by this number and * adjust the display porches accordingly. */ - vm.pixelclock = pll_rate / factor; - vm.pixelclock /= dpi->conf->pixels_per_iter; + vm->pixelclock = pll_rate / factor; + vm->pixelclock /= dpi->conf->pixels_per_iter; if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) - clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); + clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); else - clk_set_rate(dpi->pixel_clk, vm.pixelclock); + clk_set_rate(dpi->pixel_clk, vm->pixelclock); - - vm.pixelclock = clk_get_rate(dpi->pixel_clk); + vm->pixelclock = clk_get_rate(dpi->pixel_clk); dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm.pixelclock); + pll_rate, vm->pixelclock); +} + +static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, + struct drm_display_mode *mode) +{ + struct mtk_dpi_polarities dpi_pol; + struct mtk_dpi_sync_param hsync; + struct mtk_dpi_sync_param vsync_lodd = { 0 }; + struct mtk_dpi_sync_param vsync_leven = { 0 }; + struct mtk_dpi_sync_param vsync_rodd = { 0 }; + struct mtk_dpi_sync_param vsync_reven = { 0 }; + struct videomode vm = { 0 }; + + drm_display_mode_to_videomode(mode, &vm); + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; From 8c9da7cd0bbcc90ab444454fecf535320456a312 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:47:58 +0100 Subject: [PATCH 15/27] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence In preparation for adding support for newer DPI instances which do support direct-pin but do not have any H_FRE_CON register, like the one found in MT8195 and MT8188, add a branch to check if the reg_h_fre_con variable was declared in the mtk_dpi_conf structure for the probed SoC DPI version. As a note, this is useful specifically only for cases in which the support_direct_pin variable is true, so mt8195-dpintf is not affected by any issue. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-6-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 59c2e4f32a611..bb1a17f1384b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -431,12 +431,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) { - mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); + if (dpi->conf->reg_h_fre_con) + mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); } static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) { - if (dpi->conf->edge_sel_en) + if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } From c90876a695dd83e76680b88b40067275a5982811 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:47:59 +0100 Subject: [PATCH 16/27] drm/mediatek: mtk_dpi: Move the input_2p_en bit to platform data In preparation for adding support for MT8195's HDMI reserved DPI instance, move the input_2p_en bit for DP_INTF to platform data. While at it, remove the input_2pixel member from platform data as having this bit implies that the 2pixel feature must be enabled. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-7-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index bb1a17f1384b2..ed9aa928f5178 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -135,14 +135,14 @@ struct mtk_dpi_factor { * @is_ck_de_pol: Support CK/DE polarity. * @swap_input_support: Support input swap function. * @support_direct_pin: IP supports direct connection to dpi panels. - * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this - * config to enable this feature. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). * @channel_swap_shift: Shift value of channel swap. * @yuv422_en_bit: Enable bit of yuv422. * @csc_enable_bit: Enable bit of CSC. + * @input_2p_en_bit: Enable bit for input two pixel per round feature. + * If present, implies that the feature must be enabled. * @pixels_per_iter: Quantity of transferred pixels per iteration. * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. */ @@ -157,12 +157,12 @@ struct mtk_dpi_conf { bool is_ck_de_pol; bool swap_input_support; bool support_direct_pin; - bool input_2pixel; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit; + u32 input_2p_en_bit; u32 pixels_per_iter; bool edge_cfg_in_mmsys; }; @@ -651,9 +651,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); } - if (dpi->conf->input_2pixel) { - mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, - DPINTF_INPUT_2P_EN); + if (dpi->conf->input_2p_en_bit) { + mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit, + dpi->conf->input_2p_en_bit); } mtk_dpi_sw_reset(dpi, false); @@ -1121,12 +1121,12 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .output_fmts = mt8195_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), .pixels_per_iter = 4, - .input_2pixel = true, .dimension_mask = DPINTF_HPW_MASK, .hvsize_mask = DPINTF_HSIZE_MASK, .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE, + .input_2p_en_bit = DPINTF_INPUT_2P_EN, }; static int mtk_dpi_probe(struct platform_device *pdev) From 713ee441445af282f11e00b7ff950aa3738b0a1e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:00 +0100 Subject: [PATCH 17/27] drm/mediatek: mtk_dpi: Add support for DPI input clock from HDMI On some SoCs, like MT8195 and MT8188, the DPI instance that is reserved to the HDMI Transmitter uses a different clock topology. In this case, the DPI is clocked by the HDMI IP, and this outputs its clock to the MM input of dpi_pixel_clk, which is essential to enable register access to the DPI IP. Add a `clocked_by_hdmi` member to struct mtk_dpi_conf, and check it to avoid enabling the DPI clocks in the mediatek-drm internal .start() callback (and avoid disabing in the .stop() component callback): this will make sure that the clock configuration sequence is respected during display pipeline setup by following the bridge ops between DPI and HDMI, where the HDMI driver is expected to enable the clocks in the bridge's pre_enable(), and DPI in the enable() cb. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index ed9aa928f5178..91f3eb7962199 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -145,6 +145,8 @@ struct mtk_dpi_factor { * If present, implies that the feature must be enabled. * @pixels_per_iter: Quantity of transferred pixels per iteration. * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. + * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed + * for DPI registers access. */ struct mtk_dpi_conf { const struct mtk_dpi_factor *dpi_factor; @@ -165,6 +167,7 @@ struct mtk_dpi_conf { u32 input_2p_en_bit; u32 pixels_per_iter; bool edge_cfg_in_mmsys; + bool clocked_by_hdmi; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -585,7 +588,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct videomode vm = { 0 }; drm_display_mode_to_videomode(mode, &vm); - mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); + + if (!dpi->conf->clocked_by_hdmi) + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; @@ -920,14 +925,16 @@ void mtk_dpi_start(struct device *dev) { struct mtk_dpi *dpi = dev_get_drvdata(dev); - mtk_dpi_power_on(dpi); + if (!dpi->conf->clocked_by_hdmi) + mtk_dpi_power_on(dpi); } void mtk_dpi_stop(struct device *dev) { struct mtk_dpi *dpi = dev_get_drvdata(dev); - mtk_dpi_power_off(dpi); + if (!dpi->conf->clocked_by_hdmi) + mtk_dpi_power_off(dpi); } unsigned int mtk_dpi_encoder_index(struct device *dev) From 6e1931e541c7942afaa95db1c3aac1c0ceb865ef Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:01 +0100 Subject: [PATCH 18/27] drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller (afifo) supports outputting either one or two pixels per round regardless of the input being 1T1P or 1T2P. Add a `output_1pixel` member to struct mtk_dpi_conf which, if set, will enable outputting one pixel per clock. In case the input is two pixel per clock (1T2P), the AFIFO HW will automatically (and internally) convert it to 1T1P. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-9-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 91f3eb7962199..897ae591e61de 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -147,6 +147,8 @@ struct mtk_dpi_factor { * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed * for DPI registers access. + * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per + * round, the DPI hardware will internally transform it to 1T1P. */ struct mtk_dpi_conf { const struct mtk_dpi_factor *dpi_factor; @@ -168,6 +170,7 @@ struct mtk_dpi_conf { u32 pixels_per_iter; bool edge_cfg_in_mmsys; bool clocked_by_hdmi; + bool output_1pixel; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -653,7 +656,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, if (dpi->conf->support_direct_pin) { mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); + + /* DPI can connect to either an external bridge or the internal HDMI encoder */ + if (dpi->conf->output_1pixel) + mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN); + else + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); } if (dpi->conf->input_2p_en_bit) { diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index a0b1d18bbbf7e..61b276bce70f8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,6 +40,10 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) + +/* DPI_CON: DPI instances */ +#define DPI_OUTPUT_1T1P_EN BIT(24) +/* DPI_CON: DPINTF instances */ #define DPINTF_YUV422_EN BIT(24) #define DPINTF_CSC_ENABLE BIT(26) #define DPINTF_INPUT_2P_EN BIT(29) From 473c33f5ce651365468503c76f33158aaa1c7dd2 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:02 +0100 Subject: [PATCH 19/27] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off In preparation for adding support for MT8195's HDMI reserved DPI, add calls to clk_prepare_enable() / clk_disable_unprepare() for the TVD clock: in this particular case, the aforementioned clock is not (and cannot be) parented to neither pixel or engine clocks hence it won't get enabled automatically by the clock framework. Please note that on all of the currently supported MediaTek platforms, the TVD clock is always a parent of either pixel or engine clocks, and this means that the common clock framework is already enabling this clock before the children. On such platforms, this commit will only increase the refcount of the TVD clock without any functional change. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-10-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 897ae591e61de..14364d96f4d73 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -499,6 +499,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); + clk_disable_unprepare(dpi->tvd_clk); clk_disable_unprepare(dpi->engine_clk); } @@ -515,6 +516,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) goto err_refcount; } + ret = clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_engine; + } + ret = clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -524,6 +531,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; err_pixel: + clk_disable_unprepare(dpi->tvd_clk); +err_engine: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; From 48bfb13cc8cb231962a48f1505209c2d986bc4de Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 17 Feb 2025 16:48:03 +0100 Subject: [PATCH 20/27] drm/mediatek: Add support for MT8195 Digital Parallel Interface Add support for the DPI block found in the MT8195 and MT8188 SoCs. Inside of the SoC, this block is directly connected to the HDMI IP. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-11-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 14364d96f4d73..0fd13e6dd3f16 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -1139,6 +1139,24 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, }; +static const struct mtk_dpi_conf mt8195_conf = { + .max_clock_khz = 594000, + .output_fmts = mt8183_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .pixels_per_iter = 1, + .is_ck_de_pol = true, + .swap_input_support = true, + .support_direct_pin = true, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, + .input_2p_en_bit = DPI_INPUT_2P_EN, + .clocked_by_hdmi = true, + .output_1pixel = true, +}; + static const struct mtk_dpi_conf mt8195_dpintf_conf = { .dpi_factor = dpi_factor_mt8195_dp_intf, .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf), @@ -1242,6 +1260,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, + { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 61b276bce70f8..23eeefce8fd20 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -43,6 +43,7 @@ /* DPI_CON: DPI instances */ #define DPI_OUTPUT_1T1P_EN BIT(24) +#define DPI_INPUT_2P_EN BIT(25) /* DPI_CON: DPINTF instances */ #define DPINTF_YUV422_EN BIT(24) #define DPINTF_CSC_ENABLE BIT(26) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index f22ad2882697c..772c3d0f5d14d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -810,6 +810,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8195-dp-intf", .data = (void *)MTK_DP_INTF }, + { .compatible = "mediatek,mt8195-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", From fa5e56c57f8eac1a0877d6fc6a045f686d787e75 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Thu, 13 Feb 2025 19:19:17 -0500 Subject: [PATCH 21/27] drm/mediatek: Move to devm_platform_ioremap_resource() usage Replace platform_get_resource + devm_ioremap_resource with just devm_platform_ioremap_resource() Cc: Chun-Kuang Hu Cc: Philipp Zabel Reviewed-by: Maxime Ripard Reviewed-by: CK Hu Signed-off-by: Anusha Srivatsa Link: https://patchwork.kernel.org/project/dri-devel/patch/20250213-mem-cocci-v3-v1-4-93466d165349@redhat.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 4 +--- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 +--- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 +--- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 4 +--- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 +--- drivers/gpu/drm/mediatek/mtk_dsi.c | 4 +--- drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 +--- drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 4 +--- 8 files changed, 8 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index dd8433a38282a..39c7de4cdcc16 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -96,7 +96,6 @@ static int mtk_disp_color_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_color *priv; - struct resource *res; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -108,8 +107,7 @@ static int mtk_disp_color_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get color clk\n"); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->regs = devm_ioremap_resource(dev, res); + priv->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->regs)) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap color\n"); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index b17b11d93846f..8afd15006df2a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -256,7 +256,6 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_gamma *priv; - struct resource *res; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -268,8 +267,7 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get gamma clk\n"); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->regs = devm_ioremap_resource(dev, res); + priv->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->regs)) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap gamma\n"); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index 563b1b248fbbb..b174dda091d3f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -306,7 +306,6 @@ static const struct component_ops mtk_disp_merge_component_ops = { static int mtk_disp_merge_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *res; struct mtk_disp_merge *priv; int ret; @@ -314,8 +313,7 @@ static int mtk_disp_merge_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->regs = devm_ioremap_resource(dev, res); + priv->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->regs)) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap merge\n"); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index df82cea4bb79c..d0581c4e3c999 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -604,7 +604,6 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_ovl *priv; - struct resource *res; int irq; int ret; @@ -621,8 +620,7 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get ovl clk\n"); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->regs = devm_ioremap_resource(dev, res); + priv->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->regs)) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap ovl\n"); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index bf47790e4d6be..c9d41d75e7f2a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -313,7 +313,6 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_rdma *priv; - struct resource *res; int irq; int ret; @@ -330,8 +329,7 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get rdma clk\n"); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->regs = devm_ioremap_resource(dev, res); + priv->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->regs)) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap rdma\n"); diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 40752f2320548..f298293471de4 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1192,7 +1192,6 @@ static int mtk_dsi_probe(struct platform_device *pdev) { struct mtk_dsi *dsi; struct device *dev = &pdev->dev; - struct resource *regs; int irq_num; int ret; @@ -1217,8 +1216,7 @@ static int mtk_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->hs_clk)) return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n"); - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - dsi->regs = devm_ioremap_resource(dev, regs); + dsi->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dsi->regs)) return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n"); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index b899a05628bdd..d20c187c98548 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1416,7 +1416,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct device_node *cec_np, *remote, *i2c_np; struct platform_device *cec_pdev; struct regmap *regmap; - struct resource *mem; int ret; ret = mtk_hdmi_get_all_clk(hdmi, np); @@ -1462,8 +1461,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, } hdmi->sys_regmap = regmap; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hdmi->regs = devm_ioremap_resource(dev, mem); + hdmi->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hdmi->regs)) { ret = PTR_ERR(hdmi->regs); goto put_device; diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c index fc69ee38ce7d6..7982788ae9df5 100644 --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -291,7 +291,6 @@ static const struct component_ops mtk_mdp_rdma_component_ops = { static int mtk_mdp_rdma_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *res; struct mtk_mdp_rdma *priv; int ret = 0; @@ -299,8 +298,7 @@ static int mtk_mdp_rdma_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->regs = devm_ioremap_resource(dev, res); + priv->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->regs)) return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap rdma\n"); From 9e918c868346038e66daf700a11c78704844904b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 18 Feb 2025 10:04:27 +0100 Subject: [PATCH 22/27] dt-bindings: display: mediatek: dsc: Add MT8188 compatible Add compatible for Display Stream Compression (DSC) IP found in the display controller of the MT8188 SoC. This IP is fully compatible with the one found on MT8195. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://patchwork.kernel.org/project/dri-devel/patch/20250218090427.20318-1-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,dsc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml index 846de6c17d931..a5b88eb97e3b0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -22,6 +22,9 @@ properties: oneOf: - enum: - mediatek,mt8195-disp-dsc + - items: + - const: mediatek,mt8188-disp-dsc + - const: mediatek,mt8195-disp-dsc reg: maxItems: 1 From 4ba973c8bad04d59fd4efa62512f4d9cee131714 Mon Sep 17 00:00:00 2001 From: Jason-JH Lin Date: Mon, 24 Feb 2025 13:12:21 +0800 Subject: [PATCH 23/27] drm/mediatek: Fix config_updating flag never false when no mbox channel When CONFIG_MTK_CMDQ is enabled, if the display is controlled by the CPU while other hardware is controlled by the GCE, the display will encounter a mbox request channel failure. However, it will still enter the CONFIG_MTK_CMDQ statement, causing the config_updating flag to never be set to false. As a result, no page flip event is sent back to user space, and the screen does not update. Fixes: da03801ad08f ("drm/mediatek: Move mtk_crtc_finish_page_flip() to ddp_cmdq_cb()") Signed-off-by: Jason-JH Lin Reviewed-by: CK Hu Link: https://patchwork.kernel.org/project/dri-devel/patch/20250224051301.3538484-1-jason-jh.lin@mediatek.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_crtc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c index 5674f5707cca8..8f6fba4217ece 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -620,13 +620,16 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank) mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); + goto update_config_out; } -#else +#endif spin_lock_irqsave(&mtk_crtc->config_lock, flags); mtk_crtc->config_updating = false; spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); -#endif +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +update_config_out: +#endif mutex_unlock(&mtk_crtc->hw_lock); } From 106a6de46cf4887d535018185ec528ce822d6d84 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 16 Jan 2025 09:42:50 -0800 Subject: [PATCH 24/27] drm/mediatek: dp: drm_err => dev_err in HPD path to avoid NULL ptr The function mtk_dp_wait_hpd_asserted() may be called before the `mtk_dp->drm_dev` pointer is assigned in mtk_dp_bridge_attach(). Specifically it can be called via this callpath: - mtk_edp_wait_hpd_asserted - [panel probe] - dp_aux_ep_probe Using "drm" level prints anywhere in this callpath causes a NULL pointer dereference. Change the error message directly in mtk_dp_wait_hpd_asserted() to dev_err() to avoid this. Also change the error messages in mtk_dp_parse_capabilities(), which is called by mtk_dp_wait_hpd_asserted(). While touching these prints, also add the error code to them to make future debugging easier. Fixes: 7eacba9a083b ("drm/mediatek: dp: Add .wait_hpd_asserted() for AUX bus") Signed-off-by: Douglas Anderson Reviewed-by: CK Hu Link: https://patchwork.kernel.org/project/dri-devel/patch/20250116094249.1.I29b0b621abb613ddc70ab4996426a3909e1aa75f@changeid/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index cd385ba4c66aa..d2cf09124d108 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -1766,7 +1766,7 @@ static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); if (ret < 1) { - drm_err(mtk_dp->drm_dev, "Read mstm cap failed\n"); + dev_err(mtk_dp->dev, "Read mstm cap failed: %zd\n", ret); return ret == 0 ? -EIO : ret; } @@ -1776,7 +1776,7 @@ static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, &val); if (ret < 1) { - drm_err(mtk_dp->drm_dev, "Read irq vector failed\n"); + dev_err(mtk_dp->dev, "Read irq vector failed: %zd\n", ret); return ret == 0 ? -EIO : ret; } @@ -2059,7 +2059,7 @@ static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wa ret = mtk_dp_parse_capabilities(mtk_dp); if (ret) { - drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); + dev_err(mtk_dp->dev, "Can't parse capabilities: %d\n", ret); return ret; } From 5823f0453c2a51f9e10fdb90dd9051068fe607a2 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 10 Jan 2025 14:31:11 +0100 Subject: [PATCH 25/27] dt-bindings: display: mediatek: dpi: add power-domains example DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding example. Fixes: 9273cf7d3942 ("dt-bindings: display: mediatek: convert the dpi bindings to yaml") Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Reviewed-by: CK Hu Signed-off-by: Alexandre Mergnat Link: https://patchwork.kernel.org/project/dri-devel/patch/20231023-display-support-v7-1-6703f3e26831@baylibre.com/ Signed-off-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 5670715efa5c5..b659d79393a81 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -121,11 +121,13 @@ examples: - | #include #include + #include dpi: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = ; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; From cd5b6ba77705e633955fa38eb6559cc7fe484a3b Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 10 Jan 2025 14:31:13 +0100 Subject: [PATCH 26/27] drm/mediatek: add MT8365 SoC support Add DRM support for MT8365 SoC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu Link: https://patchwork.kernel.org/project/dri-devel/patch/20231023-display-support-v7-3-6703f3e26831@baylibre.com/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 772c3d0f5d14d..74158b9d65035 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -327,6 +327,10 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .min_height = 1, }; +static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { + .mmsys_dev_num = 1, +}; + static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, @@ -354,6 +358,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8195_vdosys0_driver_data}, { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data}, + { .compatible = "mediatek,mt8365-mmsys", + .data = &mt8365_mmsys_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); @@ -754,6 +760,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8195-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8365-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", From dcb166ee43c3d594e7b73a24f6e8cf5663eeff2c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 8 Jan 2025 12:35:57 +0300 Subject: [PATCH 27/27] drm/mediatek: dsi: fix error codes in mtk_dsi_host_transfer() There is a type bug because the return statement: return ret < 0 ? ret : recv_cnt; The issue is that ret is an int, recv_cnt is a u32 and the function returns ssize_t, which is a signed long. The way that the type promotion works is that the negative error codes are first cast to u32 and then to signed long. The error codes end up being positive instead of negative and the callers treat them as success. Fixes: 81cc7e51c4f1 ("drm/mediatek: Allow commands to be sent during video mode") Reported-by: kernel test robot Closes: https://lore.kernel.org/r/202412210801.iADw0oIH-lkp@intel.com/ Signed-off-by: Dan Carpenter Reviewed-by: Mattijs Korpershoek Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Link: https://patchwork.kernel.org/project/dri-devel/patch/b754a408-4f39-4e37-b52d-7706c132e27f@stanley.mountain/ Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index f298293471de4..cea995663b769 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1116,12 +1116,12 @@ static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg) { struct mtk_dsi *dsi = host_to_dsi(host); - u32 recv_cnt, i; + ssize_t recv_cnt; u8 read_data[16]; void *src_addr; u8 irq_flag = CMD_DONE_INT_FLAG; u32 dsi_mode; - int ret; + int ret, i; dsi_mode = readl(dsi->regs + DSI_MODE_CTRL); if (dsi_mode & MODE) { @@ -1170,7 +1170,7 @@ static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host, if (recv_cnt) memcpy(msg->rx_buf, src_addr, recv_cnt); - DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n", + DRM_INFO("dsi get %zd byte data from the panel address(0x%x)\n", recv_cnt, *((u8 *)(msg->tx_buf))); restore_dsi_mode: