From 145f8a155c3e8e6c7a4cf8ddb4c5be7b53d6adf1 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Mon, 7 Mar 2016 15:50:52 +0100
Subject: [PATCH 1/6] dt-bindings: irq: arm,versatile-fpga: add compatible
string for OX810SE SoC
Under the OX810SE, this same controller is used as "Reference Peripheral
Specification" Interrupt Controller, so add new compatible string to support
the Oxford Semiconductor OX810SE SoC Interrupt Controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/interrupt-controller/arm,versatile-fpga-irq.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
index c9cf605bb9957..2a1d16bdf834d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
@@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
instance can handle up to 32 interrupts.
Required properties:
-- compatible: "arm,versatile-fpga-irq"
+- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts. Must be 1
as the FPGA IRQ controller has no configuration options for interrupt
From cc86e3e2a3ff19c86a3c4a979d7da5a92e41c9cc Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Mar 2016 14:34:14 +0100
Subject: [PATCH 2/6] dt-bindings: Add Oxford Semiconductor to vendor prefixes
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 86740d4a270d3..53ca9a2a3d6a7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -177,6 +177,7 @@ option Option NV
ortustech Ortus Technology Co., Ltd.
ovti OmniVision Technologies
ORCL Oracle Corporation
+oxsemi Oxford Semiconductor, Ltd.
panasonic Panasonic Corporation
parade Parade Technologies Inc.
pericom Pericom Technology Inc.
From 84316f4ef141cfee1e8ccd1b5749998eba2496ee Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Mar 2016 10:52:58 +0100
Subject: [PATCH 3/6] ARM: boot: dts: Add Oxford Semiconductor OX810SE dtsi
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm/boot/dts/ox810se.dtsi | 336 +++++++++++++++++++++++++++++++++
1 file changed, 336 insertions(+)
create mode 100644 arch/arm/boot/dts/ox810se.dtsi
diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi
new file mode 100644
index 0000000000000..ce13705c38d4f
--- /dev/null
+++ b/arch/arm/boot/dts/ox810se.dtsi
@@ -0,0 +1,336 @@
+/*
+ * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "oxsemi,ox810se";
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ clocks = <&armclk>;
+ };
+ };
+
+ memory {
+ /* Max 256MB @ 0x48000000 */
+ reg = <0x48000000 0x10000000>;
+ };
+
+ clocks {
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ gmacclk: gmacclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ rpsclk: rpsclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc>;
+ };
+
+ pll400: pll400 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <733333333>;
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&pll400>;
+ };
+
+ armclk: armclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll400>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&intc>;
+
+ apb-bridge@44000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x44000000 0x1000000>;
+
+ pinctrl: pinctrl {
+ compatible = "oxsemi,ox810se-pinctrl";
+
+ /* Regmap for sys registers */
+ oxsemi,sys-ctrl = <&sys>;
+
+ pinctrl_uart0: uart0 {
+ uart0a {
+ pins = "gpio31";
+ function = "fct3";
+ };
+ uart0b {
+ pins = "gpio32";
+ function = "fct3";
+ };
+ };
+
+ pinctrl_uart0_modem: uart0_modem {
+ uart0c {
+ pins = "gpio27";
+ function = "fct3";
+ };
+ uart0d {
+ pins = "gpio28";
+ function = "fct3";
+ };
+ uart0e {
+ pins = "gpio29";
+ function = "fct3";
+ };
+ uart0f {
+ pins = "gpio30";
+ function = "fct3";
+ };
+ uart0g {
+ pins = "gpio33";
+ function = "fct3";
+ };
+ uart0h {
+ pins = "gpio34";
+ function = "fct3";
+ };
+ };
+
+ pinctrl_uart1: uart1 {
+ uart1a {
+ pins = "gpio20";
+ function = "fct3";
+ };
+ uart1b {
+ pins = "gpio22";
+ function = "fct3";
+ };
+ };
+
+ pinctrl_uart1_modem: uart1_modem {
+ uart1c {
+ pins = "gpio8";
+ function = "fct3";
+ };
+ uart1d {
+ pins = "gpio9";
+ function = "fct3";
+ };
+ uart1e {
+ pins = "gpio23";
+ function = "fct3";
+ };
+ uart1f {
+ pins = "gpio24";
+ function = "fct3";
+ };
+ uart1g {
+ pins = "gpio25";
+ function = "fct3";
+ };
+ uart1h {
+ pins = "gpio26";
+ function = "fct3";
+ };
+ };
+
+ pinctrl_uart2: uart2 {
+ uart2a {
+ pins = "gpio6";
+ function = "fct3";
+ };
+ uart2b {
+ pins = "gpio7";
+ function = "fct3";
+ };
+ };
+
+ pinctrl_uart2_modem: uart2_modem {
+ uart2c {
+ pins = "gpio0";
+ function = "fct3";
+ };
+ uart2d {
+ pins = "gpio1";
+ function = "fct3";
+ };
+ uart2e {
+ pins = "gpio2";
+ function = "fct3";
+ };
+ uart2f {
+ pins = "gpio3";
+ function = "fct3";
+ };
+ uart2g {
+ pins = "gpio4";
+ function = "fct3";
+ };
+ uart2h {
+ pins = "gpio5";
+ function = "fct3";
+ };
+ };
+ };
+
+ gpio0: gpio@000000 {
+ compatible = "oxsemi,ox810se-gpio";
+ reg = <0x000000 0x100000>;
+ interrupts = <21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <32>;
+ oxsemi,gpio-bank = <0>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+
+ gpio1: gpio@100000 {
+ compatible = "oxsemi,ox810se-gpio";
+ reg = <0x100000 0x100000>;
+ interrupts = <22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ngpios = <3>;
+ oxsemi,gpio-bank = <1>;
+ gpio-ranges = <&pinctrl 0 32 3>;
+ };
+
+ uart0: serial@200000 {
+ compatible = "ns16550a";
+ reg = <0x200000 0x100000>;
+ clocks = <&sysclk>;
+ interrupts = <23>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ resets = <&reset 17>;
+ };
+
+ uart1: serial@300000 {
+ compatible = "ns16550a";
+ reg = <0x300000 0x100000>;
+ clocks = <&sysclk>;
+ interrupts = <24>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ resets = <&reset 18>;
+ };
+
+ uart2: serial@900000 {
+ compatible = "ns16550a";
+ reg = <0x900000 0x100000>;
+ clocks = <&sysclk>;
+ interrupts = <29>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ resets = <&reset 22>;
+ };
+
+ uart3: serial@a00000 {
+ compatible = "ns16550a";
+ reg = <0xa00000 0x100000>;
+ clocks = <&sysclk>;
+ interrupts = <30>;
+ reg-shift = <0>;
+ fifo-size = <16>;
+ reg-io-width = <1>;
+ current-speed = <115200>;
+ no-loopback-test;
+ status = "disabled";
+ resets = <&reset 23>;
+ };
+ };
+
+ apb-bridge@45000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x45000000 0x1000000>;
+
+ sys: sys-ctrl@000000 {
+ compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
+ reg = <0x000000 0x100000>;
+
+ reset: reset-controller {
+ compatible = "oxsemi,ox810se-reset";
+ #reset-cells = <1>;
+ };
+
+ stdclk: stdclk {
+ compatible = "oxsemi,ox810se-stdclk";
+ #clock-cells = <1>;
+ };
+ };
+
+ rps@300000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0x300000 0x100000>;
+
+ intc: interrupt-controller@0 {
+ compatible = "oxsemi,ox810se-rps-irq";
+ interrupt-controller;
+ reg = <0 0x200>;
+ #interrupt-cells = <1>;
+ valid-mask = <0xFFFFFFFF>;
+ clear-mask = <0>;
+ };
+
+ timer0: timer@200 {
+ compatible = "oxsemi,ox810se-rps-timer";
+ reg = <0x200 0x40>;
+ clocks = <&rpsclk>;
+ interrupts = <4 5>;
+ };
+ };
+ };
+ };
+};
From 07609675add33ef34e880db05aaeef3c93d1aab2 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Mar 2016 10:45:50 +0100
Subject: [PATCH 4/6] dt-bindings: Add OXNAS bindings
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/oxnas.txt | 9 +++++++++
1 file changed, 9 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt
diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt
new file mode 100644
index 0000000000000..b9e49711ba056
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/oxnas.txt
@@ -0,0 +1,9 @@
+Oxford Semiconductor OXNAS SoCs Family device tree bindings
+-------------------------------------------
+
+Boards with the OX810SE SoC shall have the following properties:
+ Required root node property:
+ compatible: "oxsemi,ox810se"
+
+Board compatible values:
+ - "wd,mbwe" (OX810SE)
From f85d8ffbecadf72d2d80077f5fabba820ea4c55b Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Mar 2016 10:53:31 +0100
Subject: [PATCH 5/6] dt-bindings: Add Western Digital to vendor prefixes
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 53ca9a2a3d6a7..56aa17ff3a3a8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -260,6 +260,7 @@ via VIA Technologies, Inc.
virtio Virtual I/O Device Specification, developed by the OASIS consortium
vivante Vivante Corporation
voipac Voipac Technologies s.r.o.
+wd Western Digital Corp.
wexler Wexler
winbond Winbond Electronics corp.
wlf Wolfson Microelectronics
From 0767a5cb425374aafa89d33d6b1190a01d7f6b0e Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Mar 2016 10:53:57 +0100
Subject: [PATCH 6/6] ARM: boot: dts: Add Western Digital My Book World Edition
device tree
Add Western Digital My Book World Edition device tree based on
Oxford Semiconductor OX810SE SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/wd-mbwe.dts | 112 ++++++++++++++++++++++++++++++++++
2 files changed, 114 insertions(+)
create mode 100644 arch/arm/boot/dts/wd-mbwe.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923ce6fa3..7005585030aef 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -538,6 +538,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-rd88f5182-nas.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
+dtb-$(CONFIG_ARCH_OXNAS) += \
+ wd-mbwe.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
diff --git a/arch/arm/boot/dts/wd-mbwe.dts b/arch/arm/boot/dts/wd-mbwe.dts
new file mode 100644
index 0000000000000..ac3250ae8fc48
--- /dev/null
+++ b/arch/arm/boot/dts/wd-mbwe.dts
@@ -0,0 +1,112 @@
+/*
+ * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox810se.dtsi"
+
+/ {
+ model = "Western Digital My Book World Edition";
+
+ compatible = "wd,mbwe", "oxsemi,ox810se";
+
+ chosen {
+ bootargs = "console=ttyS1,115200n8 earlyprintk=serial";
+ };
+
+ memory {
+ /* 128Mbytes DDR */
+ reg = <0x48000000 0x8000000>;
+ };
+
+ aliases {
+ serial1 = &uart1;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ power {
+ label = "power";
+ gpios = <&gpio0 0 1>;
+ linux,code = <0x198>;
+ };
+
+ recovery {
+ label = "recovery";
+ gpios = <&gpio0 4 1>;
+ linux,code = <0xab>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ a0 {
+ label = "activity0";
+ gpios = <&gpio0 25 0>;
+ default-state = "keep";
+ };
+
+ a1 {
+ label = "activity1";
+ gpios = <&gpio0 26 0>;
+ default-state = "keep";
+ };
+
+ a2 {
+ label = "activity2";
+ gpios = <&gpio0 5 0>;
+ default-state = "keep";
+ };
+
+ a3 {
+ label = "activity3";
+ gpios = <&gpio0 6 0>;
+ default-state = "keep";
+ };
+
+ a4 {
+ label = "activity4";
+ gpios = <&gpio0 7 0>;
+ default-state = "keep";
+ };
+
+ a5 {
+ label = "activity5";
+ gpios = <&gpio1 2 0>;
+ default-state = "keep";
+ };
+ };
+
+ i2c-gpio {
+ compatible = "i2c-gpio";
+ gpios = <&gpio0 3 0 /* sda */
+ &gpio0 2 0 /* scl */
+ >;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc0: rtc@48 {
+ compatible = "st,m41t00";
+ reg = <0x68>;
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};