From 76c0ce831a045fd8e2a6bb1984689f0b50b758b4 Mon Sep 17 00:00:00 2001
From: Hongkun Zhang <Hongkun.Zhang@amd.com>
Date: Tue, 29 Nov 2022 10:31:14 +0800
Subject: [PATCH] Revert "drm/amd/display: Only use ODM2:1 policy for high
pixel rate displays"
This reverts commit 8df9afa4f42c8807e5fd22c6cd28389f23ccba61.
Reviwed-by: Feifei Xu <feifxu@amd.com>
Signed-off-by: Hongkun Zhang <hongkun.zhang@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 34c9751d03239..66302e37bf382 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1915,7 +1915,6 @@ int dcn32_populate_dml_pipes_from_context(
context->stream_status[0].plane_count <= 1 &&
!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
- pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&
dc->debug.enable_single_display_2to1_odm_policy) {
pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index f6bc9bd5da311..9bece745f9b92 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -37,7 +37,6 @@
#define DCN3_2_MBLK_WIDTH 128
#define DCN3_2_MBLK_HEIGHT_4BPE 128
#define DCN3_2_MBLK_HEIGHT_8BPE 64
-#define DCN3_2_VMIN_DISPCLK_HZ 717000000
#define TO_DCN32_RES_POOL(pool)\
container_of(pool, struct dcn32_resource_pool, base)