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gpu: ipu-v3: image-convert: move tile alignment helpers
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Move tile_width_align and tile_height_align up so they
can be used by the tile edge position calculation code.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Steve Longerbeam <slongerbeam@gmail.com>
Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
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Philipp Zabel committed Nov 5, 2018
1 parent 26ddd03 commit 76e77bf
Showing 1 changed file with 27 additions and 27 deletions.
54 changes: 27 additions & 27 deletions drivers/gpu/ipu-v3/ipu-image-convert.c
Original file line number Diff line number Diff line change
Expand Up @@ -432,6 +432,33 @@ static int calc_image_resize_coefficients(struct ipu_image_convert_ctx *ctx,
return 0;
}

/*
* We have to adjust the tile width such that the tile physaddrs and
* U and V plane offsets are multiples of 8 bytes as required by
* the IPU DMA Controller. For the planar formats, this corresponds
* to a pixel alignment of 16 (but use a more formal equation since
* the variables are available). For all the packed formats, 8 is
* good enough.
*/
static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt)
{
return fmt->planar ? 8 * fmt->uv_width_dec : 8;
}

/*
* For tile height alignment, we have to ensure that the output tile
* heights are multiples of 8 lines if the IRT is required by the
* given rotation mode (the IRT performs rotations on 8x8 blocks
* at a time). If the IRT is not used, or for input image tiles,
* 2 lines are good enough.
*/
static inline u32 tile_height_align(enum ipu_image_convert_type type,
enum ipu_rotate_mode rot_mode)
{
return (type == IMAGE_CONVERT_OUT &&
ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2;
}

static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *image)
{
Expand Down Expand Up @@ -1487,33 +1514,6 @@ static unsigned int clamp_align(unsigned int x, unsigned int min,
return x;
}

/*
* We have to adjust the tile width such that the tile physaddrs and
* U and V plane offsets are multiples of 8 bytes as required by
* the IPU DMA Controller. For the planar formats, this corresponds
* to a pixel alignment of 16 (but use a more formal equation since
* the variables are available). For all the packed formats, 8 is
* good enough.
*/
static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt)
{
return fmt->planar ? 8 * fmt->uv_width_dec : 8;
}

/*
* For tile height alignment, we have to ensure that the output tile
* heights are multiples of 8 lines if the IRT is required by the
* given rotation mode (the IRT performs rotations on 8x8 blocks
* at a time). If the IRT is not used, or for input image tiles,
* 2 lines are good enough.
*/
static inline u32 tile_height_align(enum ipu_image_convert_type type,
enum ipu_rotate_mode rot_mode)
{
return (type == IMAGE_CONVERT_OUT &&
ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2;
}

/* Adjusts input/output images to IPU restrictions */
void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode)
Expand Down

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