From dd014803f260b337daaabcde259daf70d5b26b5e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:23 +0200 Subject: [PATCH 01/36] interconnect: qcom: icc-rpm: Add AB/IB calculations coefficients Presumably due to the hardware being so complex, some nodes (or busses) have different (usually higher) requirements for bandwidth than what the usual calculations would suggest. Looking at the available downstream files, it seems like AB values are adjusted per-bus and IB values are adjusted per-node. With that in mind, introduce percentage-based coefficient struct members and use them in the calculations. One thing to note is that the IB coefficient is inverse (100/ib_percent) which feels a bit backwards, but it's necessary for precision.. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-1-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 18 +++++++++++++++--- drivers/interconnect/qcom/icc-rpm.h | 6 ++++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 2c16917ba1fda..8b02aa8aa96a7 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -298,7 +298,8 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, */ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_rate) { - u64 agg_avg_rate, agg_rate; + struct qcom_icc_provider *qp = to_qcom_provider(provider); + u64 agg_avg_rate, agg_peak_rate, agg_rate; struct qcom_icc_node *qn; struct icc_node *node; int i; @@ -315,8 +316,19 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_r else agg_avg_rate = qn->sum_avg[i]; - agg_rate = max_t(u64, agg_avg_rate, qn->max_peak[i]); - do_div(agg_rate, qn->buswidth); + if (qp->ab_coeff) { + agg_avg_rate = agg_avg_rate * qp->ab_coeff; + agg_avg_rate = div_u64(agg_avg_rate, 100); + } + + if (qp->ib_coeff) { + agg_peak_rate = qn->max_peak[i] * 100; + agg_peak_rate = div_u64(qn->max_peak[i], qp->ib_coeff); + } else { + agg_peak_rate = qn->max_peak[i]; + } + + agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); agg_clk_rate[i] = max_t(u64, agg_clk_rate[i], agg_rate); } diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index eed3451af3e6e..5e7d6a4fd2f3f 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -44,6 +44,8 @@ struct rpm_clk_resource { * @type: the ICC provider type * @regmap: regmap for QoS registers read/write access * @qos_offset: offset to QoS registers + * @ab_coeff: a percentage-based coefficient for compensating the AB calculations + * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations * @bus_clk_rate: bus clock rate in Hz * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks * @bus_clk: a pointer to a HLOS-owned bus clock @@ -57,6 +59,8 @@ struct qcom_icc_provider { enum qcom_icc_type type; struct regmap *regmap; unsigned int qos_offset; + u16 ab_coeff; + u16 ib_coeff; u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; const struct rpm_clk_resource *bus_clk_desc; struct clk *bus_clk; @@ -123,6 +127,8 @@ struct qcom_icc_desc { enum qcom_icc_type type; const struct regmap_config *regmap_cfg; unsigned int qos_offset; + u16 ab_coeff; + u16 ib_coeff; }; /* Valid for all bus types */ From db8fc1002c53bc17a3ca6fad2c524de42b77c146 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:24 +0200 Subject: [PATCH 02/36] interconnect: qcom: icc-rpm: Separate out clock rate calulcations In preparation for also setting per-node clock rates, separate out the logic that computes it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-2-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 53 ++++++++++++++++------------- 1 file changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 8b02aa8aa96a7..8c1bfd65d774a 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -291,6 +291,32 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, return 0; } +static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node *qn, int ctx) +{ + u64 agg_avg_rate, agg_peak_rate, agg_rate; + + if (qn->channels) + agg_avg_rate = div_u64(qn->sum_avg[ctx], qn->channels); + else + agg_avg_rate = qn->sum_avg[ctx]; + + if (qp->ab_coeff) { + agg_avg_rate = agg_avg_rate * qp->ab_coeff; + agg_avg_rate = div_u64(agg_avg_rate, 100); + } + + if (qp->ib_coeff) { + agg_peak_rate = qn->max_peak[ctx] * 100; + agg_peak_rate = div_u64(qn->max_peak[ctx], qp->ib_coeff); + } else { + agg_peak_rate = qn->max_peak[ctx]; + } + + agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); + + return div_u64(agg_rate, qn->buswidth); +} + /** * qcom_icc_bus_aggregate - calculate bus clock rates by traversing all nodes * @provider: generic interconnect provider @@ -299,10 +325,9 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_rate) { struct qcom_icc_provider *qp = to_qcom_provider(provider); - u64 agg_avg_rate, agg_peak_rate, agg_rate; struct qcom_icc_node *qn; struct icc_node *node; - int i; + int ctx; /* * Iterate nodes on the provider, aggregate bandwidth requests for @@ -310,27 +335,9 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider, u64 *agg_clk_r */ list_for_each_entry(node, &provider->nodes, node_list) { qn = node->data; - for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) { - if (qn->channels) - agg_avg_rate = div_u64(qn->sum_avg[i], qn->channels); - else - agg_avg_rate = qn->sum_avg[i]; - - if (qp->ab_coeff) { - agg_avg_rate = agg_avg_rate * qp->ab_coeff; - agg_avg_rate = div_u64(agg_avg_rate, 100); - } - - if (qp->ib_coeff) { - agg_peak_rate = qn->max_peak[i] * 100; - agg_peak_rate = div_u64(qn->max_peak[i], qp->ib_coeff); - } else { - agg_peak_rate = qn->max_peak[i]; - } - - agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate); - - agg_clk_rate[i] = max_t(u64, agg_clk_rate[i], agg_rate); + for (ctx = 0; ctx < QCOM_SMD_RPM_STATE_NUM; ctx++) { + agg_clk_rate[ctx] = max_t(u64, agg_clk_rate[ctx], + qcom_icc_calc_rate(qp, qn, ctx)); } } } From 919791d82d3b878094e9edc39b0d9a4eafcc0860 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:25 +0200 Subject: [PATCH 03/36] interconnect: qcom: icc-rpm: Let nodes drive their own bus clock If this hardware couldn't get messier, some nodes are supposed to drive their own bus clock.. Presumably to connect to some intermediate interface between the node itself and the bus it's (supposed to be) connected to. Expand the node struct with the necessary data and hook up the allocations & calculations. Note that the node-specific AB/IB coefficients contribute (by design) to both the node-level and the bus-level aggregation. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-3-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 27 +++++++++++++++++++++++++++ drivers/interconnect/qcom/icc-rpm.h | 4 ++++ 2 files changed, 31 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 8c1bfd65d774a..1d3af4e9ead86 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -414,6 +414,33 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; } + /* Handle the node-specific clock */ + if (!src_qn->bus_clk_desc) + return 0; + + active_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_ACTIVE_STATE); + sleep_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_SLEEP_STATE); + + if (active_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]) { + ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_ACTIVE_STATE, + active_rate); + if (ret) + return ret; + + /* Cache the rate after we've successfully committed it to RPM */ + src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate; + } + + if (sleep_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE]) { + ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_SLEEP_STATE, + sleep_rate); + if (ret) + return ret; + + /* Cache the rate after we've successfully committed it to RPM */ + src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; + } + return 0; } diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 5e7d6a4fd2f3f..725e0d4840e42 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -97,11 +97,13 @@ struct qcom_icc_qos { * @num_links: the total number of @links * @channels: number of channels at this node (e.g. DDR channels) * @buswidth: width of the interconnect between a node and the bus (bytes) + * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks * @sum_avg: current sum aggregate value of all avg bw requests * @max_peak: current max aggregate value of all peak bw requests * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves * @qos: NoC QoS setting parameters + * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz */ struct qcom_icc_node { unsigned char *name; @@ -110,11 +112,13 @@ struct qcom_icc_node { u16 num_links; u16 channels; u16 buswidth; + const struct rpm_clk_resource *bus_clk_desc; u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; int mas_rpm_id; int slv_rpm_id; struct qcom_icc_qos qos; + u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; }; struct qcom_icc_desc { From ba3f826639782587b70a684dae79d39f6d3c433e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:26 +0200 Subject: [PATCH 04/36] interconnect: qcom: icc-rpm: Check for node-specific rate coefficients Some nodes may have different coefficients than the general values for bus they're attached to. Check for that and use them if present. See [1], [2] for reference. [1] https://github.com/sonyxperiadev/kernel/commit/7456d9779af9ad6bb9c7ee6f33d5c5a8d3648e24 [2] https://github.com/artem/android_kernel_sony_msm8996/commit/bf7a8985dcaf0eab5bc2562d2d6775e7e29c0f30 Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-4-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 14 ++++++++++---- drivers/interconnect/qcom/icc-rpm.h | 4 ++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 1d3af4e9ead86..9c40314e03b53 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -300,14 +300,14 @@ static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node else agg_avg_rate = qn->sum_avg[ctx]; - if (qp->ab_coeff) { - agg_avg_rate = agg_avg_rate * qp->ab_coeff; + if (qn->ab_coeff) { + agg_avg_rate = agg_avg_rate * qn->ab_coeff; agg_avg_rate = div_u64(agg_avg_rate, 100); } - if (qp->ib_coeff) { + if (qn->ib_coeff) { agg_peak_rate = qn->max_peak[ctx] * 100; - agg_peak_rate = div_u64(qn->max_peak[ctx], qp->ib_coeff); + agg_peak_rate = div_u64(qn->max_peak[ctx], qn->ib_coeff); } else { agg_peak_rate = qn->max_peak[ctx]; } @@ -563,6 +563,12 @@ int qnoc_probe(struct platform_device *pdev) for (i = 0; i < num_nodes; i++) { size_t j; + if (!qnodes[i]->ab_coeff) + qnodes[i]->ab_coeff = qp->ab_coeff; + + if (!qnodes[i]->ib_coeff) + qnodes[i]->ib_coeff = qp->ib_coeff; + node = icc_node_create(qnodes[i]->id); if (IS_ERR(node)) { ret = PTR_ERR(node); diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 725e0d4840e42..4abf99ce2690f 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -103,6 +103,8 @@ struct qcom_icc_qos { * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves * @qos: NoC QoS setting parameters + * @ab_coeff: a percentage-based coefficient for compensating the AB calculations + * @ib_coeff: an inverse-percentage-based coefficient for compensating the IB calculations * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz */ struct qcom_icc_node { @@ -118,6 +120,8 @@ struct qcom_icc_node { int mas_rpm_id; int slv_rpm_id; struct qcom_icc_qos qos; + u16 ab_coeff; + u16 ib_coeff; u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; }; From fa35757ae0a5a88bd1b7df8578ee9dac9d147c64 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:27 +0200 Subject: [PATCH 05/36] interconnect: qcom: qcm2290: Hook up MAS_APPS_PROC's bus clock This single node has its own clock which seems to be responsible for transactions between CPUSS (CPU + some stuff) and the GNOC. See [1] for reference. Define it and hook it up. [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/02f8c342b23c20a5cf967df649814be37a08227c%5E%21/#F0 Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-5-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm-clocks.c | 6 ++++++ drivers/interconnect/qcom/icc-rpm.h | 1 + drivers/interconnect/qcom/qcm2290.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpm-clocks.c b/drivers/interconnect/qcom/icc-rpm-clocks.c index 63c82a91bbc75..ac1677de7dfd8 100644 --- a/drivers/interconnect/qcom/icc-rpm-clocks.c +++ b/drivers/interconnect/qcom/icc-rpm-clocks.c @@ -25,6 +25,12 @@ const struct rpm_clk_resource bimc_clk = { }; EXPORT_SYMBOL_GPL(bimc_clk); +const struct rpm_clk_resource mem_1_clk = { + .resource_type = QCOM_SMD_RPM_MEM_CLK, + .clock_id = 1, +}; +EXPORT_SYMBOL_GPL(mem_1_clk); + const struct rpm_clk_resource bus_0_clk = { .resource_type = QCOM_SMD_RPM_BUS_CLK, .clock_id = 0, diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 4abf99ce2690f..a13768cfd2311 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -152,6 +152,7 @@ extern const struct rpm_clk_resource bimc_clk; extern const struct rpm_clk_resource bus_0_clk; extern const struct rpm_clk_resource bus_1_clk; extern const struct rpm_clk_resource bus_2_clk; +extern const struct rpm_clk_resource mem_1_clk; extern const struct rpm_clk_resource mmaxi_0_clk; extern const struct rpm_clk_resource mmaxi_1_clk; extern const struct rpm_clk_resource qup_clk; diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 5bc4b7516608b..026e4c82d6d4b 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -112,6 +112,9 @@ static struct qcom_icc_node mas_appss_proc = { .qos.qos_mode = NOC_QOS_MODE_FIXED, .qos.prio_level = 0, .qos.areq_prio = 0, + .bus_clk_desc = &mem_1_clk, + .ab_coeff = 159, + .ib_coeff = 96, .mas_rpm_id = 0, .slv_rpm_id = -1, .num_links = ARRAY_SIZE(mas_appss_proc_links), From 8657ed471196f4dc8e7917453a39363e0014840c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:28 +0200 Subject: [PATCH 06/36] interconnect: qcom: qcm2290: Set AB coefficients Some buses need additional manual adjustments atop the usual calculations. Fill in the missing coefficients. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-6-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/qcm2290.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 026e4c82d6d4b..7abc0c449220d 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -1202,6 +1202,7 @@ static const struct qcom_icc_desc qcm2290_bimc = { .keep_alive = true, /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ .qos_offset = 0x8000, + .ab_coeff = 153, }; static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { @@ -1332,6 +1333,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .regmap_cfg = &qcm2290_snoc_regmap_config, .keep_alive = true, .qos_offset = 0x15000, + .ab_coeff = 142, }; static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { @@ -1348,6 +1350,7 @@ static const struct qcom_icc_desc qcm2290_mmrt_virt = { .regmap_cfg = &qcm2290_snoc_regmap_config, .keep_alive = true, .qos_offset = 0x15000, + .ab_coeff = 139, }; static const struct of_device_id qcm2290_noc_of_match[] = { From 550064a85ba564cfb508a995f45e39a6ad0e26ed Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:29 +0200 Subject: [PATCH 07/36] interconnect: qcom: qcm2290: Update EBI channel configuration QCM2290 can support two memory configurations: single-channel, 32-bit wide LPDDR3 @ up to 933MHz (bus clock) or dual-channel, 16-bit wide LPDDR4X @ up to 1804 MHz. The interconnect driver in its current form seems to gravitate towards the first one, however there are no LPDDR3- equipped boards upstream and we still don't have a great way to discern the DDR generations on the kernel side. To make DDR scaling possible on the only currently-supported 2290 board, stick with the LPDDR4X config by default. The side effect on any potential LPDDR3 board would be that the requested bus clock rate is too high (but still capped to the firmware-configured FMAX). Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-7-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/qcm2290.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 7abc0c449220d..b88cf9a022e03 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -678,7 +678,8 @@ static struct qcom_icc_node mas_gfx3d = { static struct qcom_icc_node slv_ebi1 = { .name = "slv_ebi1", .id = QCM2290_SLAVE_EBI1, - .buswidth = 8, + .buswidth = 4, + .channels = 2, .mas_rpm_id = -1, .slv_rpm_id = 0, }; From a4a9251760185af9ca7ff1592a05a0eabfe0cd00 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:30 +0200 Subject: [PATCH 08/36] interconnect: qcom: sdm660: Set AB/IB coefficients Some buses and nodes need additional manual adjustments atop the usual calculations. Fill in the missing coefficients. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-8-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdm660.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 36962f7bd7bbf..7392bebba3344 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -602,6 +602,7 @@ static struct qcom_icc_node mas_mdp_p0 = { .name = "mas_mdp_p0", .id = SDM660_MASTER_MDP_P0, .buswidth = 16, + .ib_coeff = 50, .mas_rpm_id = 8, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -621,6 +622,7 @@ static struct qcom_icc_node mas_mdp_p1 = { .name = "mas_mdp_p1", .id = SDM660_MASTER_MDP_P1, .buswidth = 16, + .ib_coeff = 50, .mas_rpm_id = 61, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -1540,6 +1542,7 @@ static const struct qcom_icc_desc sdm660_bimc = { .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), .bus_clk_desc = &bimc_clk, .regmap_cfg = &sdm660_bimc_regmap_config, + .ab_coeff = 153, }; static struct qcom_icc_node * const sdm660_cnoc_nodes[] = { @@ -1659,6 +1662,7 @@ static const struct qcom_icc_desc sdm660_mnoc = { .intf_clocks = mm_intf_clocks, .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), .regmap_cfg = &sdm660_mnoc_regmap_config, + .ab_coeff = 153, }; static struct qcom_icc_node * const sdm660_snoc_nodes[] = { From 1255f23c219a74f2577c9ca5521abeb36db35d3b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 25 Aug 2023 17:38:31 +0200 Subject: [PATCH 09/36] interconnect: qcom: msm8996: Set AB/IB coefficients Some buses and nodes need additional manual adjustments atop the usual calculations. Fill in the missing coefficients. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-9-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/msm8996.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index 88683dfa468f6..b73566c9b21f9 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -448,6 +448,7 @@ static struct qcom_icc_node mas_mdp_p0 = { .name = "mas_mdp_p0", .id = MSM8996_MASTER_MDP_PORT0, .buswidth = 32, + .ib_coeff = 25, .mas_rpm_id = 8, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -463,6 +464,7 @@ static struct qcom_icc_node mas_mdp_p1 = { .name = "mas_mdp_p1", .id = MSM8996_MASTER_MDP_PORT1, .buswidth = 32, + .ib_coeff = 25, .mas_rpm_id = 61, .slv_rpm_id = -1, .qos.ap_owned = true, @@ -1889,7 +1891,8 @@ static const struct qcom_icc_desc msm8996_bimc = { .nodes = bimc_nodes, .num_nodes = ARRAY_SIZE(bimc_nodes), .bus_clk_desc = &bimc_clk, - .regmap_cfg = &msm8996_bimc_regmap_config + .regmap_cfg = &msm8996_bimc_regmap_config, + .ab_coeff = 154, }; static struct qcom_icc_node * const cnoc_nodes[] = { @@ -2004,7 +2007,8 @@ static const struct qcom_icc_desc msm8996_mnoc = { .bus_clk_desc = &mmaxi_0_clk, .intf_clocks = mm_intf_clocks, .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), - .regmap_cfg = &msm8996_mnoc_regmap_config + .regmap_cfg = &msm8996_mnoc_regmap_config, + .ab_coeff = 154, }; static struct qcom_icc_node * const pnoc_nodes[] = { From 400e531bcdf1dc702c9d560f57cea3b9547030fc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:27 +0200 Subject: [PATCH 10/36] dt-bindings: interconnect: qcom: Introduce qcom,rpm-common The current RPM interconnect bindings are messy. Start cleaning them up with a common include. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-1-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,qcm2290.yaml | 18 ++++++------ .../interconnect/qcom,rpm-common.yaml | 28 +++++++++++++++++++ 2 files changed, 36 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpm-common.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml index f65a2fe846dea..df89f390a9b09 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml @@ -13,6 +13,9 @@ description: | The Qualcomm QCM2290 interconnect providers support adjusting the bandwidth requirements between the various NoC fabrics. +allOf: + - $ref: qcom,rpm-common.yaml# + properties: reg: maxItems: 1 @@ -23,9 +26,6 @@ properties: - qcom,qcm2290-cnoc - qcom,qcm2290-snoc - '#interconnect-cells': - const: 1 - clock-names: items: - const: bus @@ -44,6 +44,9 @@ patternProperties: The interconnect providers do not have a separate QoS register space, but share parent's space. + allOf: + - $ref: qcom,rpm-common.yaml# + properties: compatible: enum: @@ -51,9 +54,6 @@ patternProperties: - qcom,qcm2290-mmrt-virt - qcom,qcm2290-mmnrt-virt - '#interconnect-cells': - const: 1 - clock-names: items: - const: bus @@ -66,20 +66,18 @@ patternProperties: required: - compatible - - '#interconnect-cells' - clock-names - clocks - additionalProperties: false + unevaluatedProperties: false required: - compatible - reg - - '#interconnect-cells' - clock-names - clocks -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm-common.yaml new file mode 100644 index 0000000000000..1ea52b0916093 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm-common.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,rpm-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect + +maintainers: + - Konrad Dybcio + +description: + RPM interconnect providers support for managing system bandwidth requirements + through manual requests based on either predefined values or as indicated by + the bus monitor hardware. Each provider node represents a NoC bus master, + driven by a dedicated clock source. + +properties: + '#interconnect-cells': + oneOf: + - const: 2 + - const: 1 + deprecated: true + +required: + - '#interconnect-cells' + +additionalProperties: true From 5d4268b31ef060a18ce0e7af7e8f7ccf815456ff Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:28 +0200 Subject: [PATCH 11/36] dt-bindings: interconnect: qcom: qcm2290: Remove RPM bus clocks After the recent reshuffling, bus clocks are no longer exposed as RPM clocks. Remove the old description. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-2-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,qcm2290.yaml | 42 ------------------- 1 file changed, 42 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml index df89f390a9b09..b6c15314c5c5a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml @@ -26,16 +26,6 @@ properties: - qcom,qcm2290-cnoc - qcom,qcm2290-snoc - clock-names: - items: - - const: bus - - const: bus_a - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - # Child node's properties patternProperties: '^interconnect-[a-z0-9]+$': @@ -54,28 +44,14 @@ patternProperties: - qcom,qcm2290-mmrt-virt - qcom,qcm2290-mmnrt-virt - clock-names: - items: - - const: bus - - const: bus_a - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - required: - compatible - - clock-names - - clocks unevaluatedProperties: false required: - compatible - reg - - clock-names - - clocks unevaluatedProperties: false @@ -87,32 +63,20 @@ examples: compatible = "qcom,qcm2290-snoc"; reg = <0x01880000 0x60200>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; qup_virt: interconnect-qup { compatible = "qcom,qcm2290-qup-virt"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_QUP_CLK>, - <&rpmcc RPM_SMD_QUP_A_CLK>; }; mmnrt_virt: interconnect-mmnrt { compatible = "qcom,qcm2290-mmnrt-virt"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, - <&rpmcc RPM_SMD_MMNRT_A_CLK>; }; mmrt_virt: interconnect-mmrt { compatible = "qcom,qcm2290-mmrt-virt"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_MMRT_CLK>, - <&rpmcc RPM_SMD_MMRT_A_CLK>; }; }; @@ -120,16 +84,10 @@ examples: compatible = "qcom,qcm2290-cnoc"; reg = <0x01900000 0x8200>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; }; bimc: interconnect@4480000 { compatible = "qcom,qcm2290-bimc"; reg = <0x04480000 0x80000>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; }; From c19bcc762796a128beafffa77558f9c1fdc50398 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:29 +0200 Subject: [PATCH 12/36] dt-bindings: interconnect: qcom: Fix and separate out SDM660 Separate out SDM660 icc bindings from the common file and fix the clocks description by removing the wrong internal RPM bus clock representation that we've been carrying for years. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-3-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,rpm.yaml | 40 ------- .../bindings/interconnect/qcom,sdm660.yaml | 108 ++++++++++++++++++ 2 files changed, 108 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 4f95d512012af..59895cca6a8c9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -37,12 +37,6 @@ properties: - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc - - qcom,sdm660-a2noc - - qcom,sdm660-bimc - - qcom,sdm660-cnoc - - qcom,sdm660-gnoc - - qcom,sdm660-mnoc - - qcom,sdm660-snoc '#interconnect-cells': description: | @@ -123,10 +117,6 @@ allOf: - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc - - qcom,sdm660-bimc - - qcom,sdm660-cnoc - - qcom,sdm660-gnoc - - qcom,sdm660-snoc then: properties: @@ -146,7 +136,6 @@ allOf: contains: enum: - qcom,msm8996-mnoc - - qcom,sdm660-mnoc then: properties: @@ -209,35 +198,6 @@ allOf: - description: Aggregate2 NoC UFS AXI Clock - description: UFS AXI Clock - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm660-a2noc - - then: - properties: - clock-names: - items: - - const: bus - - const: bus_a - - const: ipa - - const: ufs_axi - - const: aggre2_ufs_axi - - const: aggre2_usb3_axi - - const: cfg_noc_usb2_axi - - clocks: - items: - - description: Bus Clock. - - description: Bus A Clock. - - description: IPA Clock. - - description: UFS AXI Clock. - - description: Aggregate2 UFS AXI Clock. - - description: Aggregate2 USB3 AXI Clock. - - description: Config NoC USB2 AXI Clock. - - if: not: properties: diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml new file mode 100644 index 0000000000000..8f6bc6399626b --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 Network-On-Chip interconnect + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm SDM660 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,sdm660-a2noc + - qcom,sdm660-bimc + - qcom,sdm660-cnoc + - qcom,sdm660-gnoc + - qcom,sdm660-mnoc + - qcom,sdm660-snoc + + reg: + maxItems: 1 + + clock-names: + minItems: 1 + maxItems: 5 + + clocks: + minItems: 1 + maxItems: 5 + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,sdm660-mnoc + + then: + properties: + clocks: + items: + - description: CPU-NoC High-performance Bus Clock. + + clock-names: + const: iface + + - if: + properties: + compatible: + const: qcom,sdm660-a2noc + + then: + properties: + clocks: + items: + - description: IPA Clock. + - description: UFS AXI Clock. + - description: Aggregate2 UFS AXI Clock. + - description: Aggregate2 USB3 AXI Clock. + - description: Config NoC USB2 AXI Clock. + + clock-names: + items: + - const: ipa + - const: ufs_axi + - const: aggre2_ufs_axi + - const: aggre2_usb3_axi + - const: cfg_noc_usb2_axi + +examples: + - | + #include + #include + #include + + bimc: interconnect@1008000 { + compatible = "qcom,sdm660-bimc"; + reg = <0x01008000 0x78000>; + #interconnect-cells = <1>; + }; + + a2noc: interconnect@1704000 { + compatible = "qcom,sdm660-a2noc"; + reg = <0x01704000 0xc100>; + #interconnect-cells = <1>; + clocks = <&rpmcc RPM_SMD_IPA_CLK>, + <&gcc GCC_UFS_AXI_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; + clock-names = "ipa", + "ufs_axi", + "aggre2_ufs_axi", + "aggre2_usb3_axi", + "cfg_noc_usb2_axi"; + }; From d03374a61b0fce165ec51529652ec55ed0ac305c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:30 +0200 Subject: [PATCH 13/36] dt-bindings: interconnect: qcom: Fix and separate out MSM8996 Separate out MSM8996 icc bindings from the common file and fix the clocks description by removing the wrong internal RPM bus clock representation that we've been carrying for years. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-4-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,msm8996.yaml | 126 ++++++++++++++++++ .../bindings/interconnect/qcom,rpm.yaml | 81 ----------- 2 files changed, 126 insertions(+), 81 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm8996.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8996.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8996.yaml new file mode 100644 index 0000000000000..e3f964aaad1b5 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8996.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8996.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8996 Network-On-Chip interconnect + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm MSM8996 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,msm8996-a0noc + - qcom,msm8996-a1noc + - qcom,msm8996-a2noc + - qcom,msm8996-bimc + - qcom,msm8996-cnoc + - qcom,msm8996-mnoc + - qcom,msm8996-pnoc + - qcom,msm8996-snoc + + reg: + maxItems: 1 + + clock-names: + minItems: 1 + maxItems: 3 + + clocks: + minItems: 1 + maxItems: 3 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,msm8996-a0noc + + then: + properties: + clocks: + items: + - description: Aggregate0 System NoC AXI Clock. + - description: Aggregate0 Config NoC AHB Clock. + - description: Aggregate0 NoC MPU Clock. + + clock-names: + items: + - const: aggre0_snoc_axi + - const: aggre0_cnoc_ahb + - const: aggre0_noc_mpu_cfg + + required: + - power-domains + + - if: + properties: + compatible: + const: qcom,msm8996-mnoc + + then: + properties: + clocks: + items: + - description: CPU-NoC High-performance Bus Clock. + + clock-names: + const: iface + + - if: + properties: + compatible: + const: qcom,msm8996-a2noc + + then: + properties: + clocks: + items: + - description: Aggregate2 NoC UFS AXI Clock + - description: UFS AXI Clock + + clock-names: + items: + - const: aggre2_ufs_axi + - const: ufs_axi + +examples: + - | + #include + #include + #include + + bimc: interconnect@408000 { + compatible = "qcom,msm8996-bimc"; + reg = <0x00408000 0x5a000>; + #interconnect-cells = <1>; + }; + + a0noc: interconnect@543000 { + compatible = "qcom,msm8996-a0noc"; + reg = <0x00543000 0x6000>; + #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, + <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, + <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; + clock-names = "aggre0_snoc_axi", + "aggre0_cnoc_ahb", + "aggre0_noc_mpu_cfg"; + power-domains = <&gcc AGGRE0_NOC_GDSC>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 59895cca6a8c9..3e1bcbbdb532b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -26,14 +26,6 @@ properties: - qcom,msm8939-bimc - qcom,msm8939-pcnoc - qcom,msm8939-snoc - - qcom,msm8996-a0noc - - qcom,msm8996-a1noc - - qcom,msm8996-a2noc - - qcom,msm8996-bimc - - qcom,msm8996-cnoc - - qcom,msm8996-mnoc - - qcom,msm8996-pnoc - - qcom,msm8996-snoc - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc @@ -109,11 +101,6 @@ allOf: - qcom,msm8939-bimc - qcom,msm8939-pcnoc - qcom,msm8939-snoc - - qcom,msm8996-a1noc - - qcom,msm8996-bimc - - qcom,msm8996-cnoc - - qcom,msm8996-pnoc - - qcom,msm8996-snoc - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc @@ -130,74 +117,6 @@ allOf: - description: Bus Clock - description: Bus A Clock - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8996-mnoc - - then: - properties: - clock-names: - items: - - const: bus - - const: bus_a - - const: iface - - clocks: - items: - - description: Bus Clock. - - description: Bus A Clock. - - description: CPU-NoC High-performance Bus Clock. - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8996-a0noc - - then: - properties: - clock-names: - items: - - const: aggre0_snoc_axi - - const: aggre0_cnoc_ahb - - const: aggre0_noc_mpu_cfg - - clocks: - items: - - description: Aggregate0 System NoC AXI Clock. - - description: Aggregate0 Config NoC AHB Clock. - - description: Aggregate0 NoC MPU Clock. - - required: - - power-domains - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8996-a2noc - - then: - properties: - clock-names: - items: - - const: bus - - const: bus_a - - const: aggre2_ufs_axi - - const: ufs_axi - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - - description: Aggregate2 NoC UFS AXI Clock - - description: UFS AXI Clock - - if: not: properties: From 462baaf4c6281550b0d57131f95d51e6949889ec Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:31 +0200 Subject: [PATCH 14/36] dt-bindings: interconnect: qcom: Fix and separate out MSM8939 Separate out MSM8939 icc bindings from the common file and fix the clocks description by removing the wrong internal RPM bus clock representation that we've been carrying for years. This was the final one, so also retire the shared file. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-5-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,msm8939.yaml | 74 +++++++++++++++++++ .../bindings/interconnect/qcom,rpm.yaml | 49 ------------ 2 files changed, 74 insertions(+), 49 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml new file mode 100644 index 0000000000000..fd15ab5014fb5 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8939.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,msm8939.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8939 Network-On-Chip interconnect + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm MSM8939 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +allOf: + - $ref: qcom,rpm-common.yaml# + +properties: + compatible: + enum: + - qcom,msm8939-bimc + - qcom,msm8939-pcnoc + - qcom,msm8939-snoc + + reg: + maxItems: 1 + +patternProperties: + '^interconnect-[a-z0-9\-]+$': + type: object + $ref: qcom,rpm-common.yaml# + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpm-common.yaml# + + properties: + compatible: + const: qcom,msm8939-snoc-mm + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + snoc: interconnect@580000 { + compatible = "qcom,msm8939-snoc"; + reg = <0x00580000 0x14000>; + #interconnect-cells = <1>; + }; + + bimc: interconnect@400000 { + compatible = "qcom,msm8939-bimc"; + reg = <0x00400000 0x62000>; + #interconnect-cells = <1>; + + snoc_mm: interconnect-snoc { + compatible = "qcom,msm8939-snoc-mm"; + #interconnect-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 3e1bcbbdb532b..72856b1c4210e 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -23,9 +23,6 @@ properties: - qcom,msm8916-bimc - qcom,msm8916-pcnoc - qcom,msm8916-snoc - - qcom,msm8939-bimc - - qcom,msm8939-pcnoc - - qcom,msm8939-snoc - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc @@ -48,38 +45,6 @@ properties: power-domains: maxItems: 1 -# Child node's properties -patternProperties: - '^interconnect-[a-z0-9]+$': - type: object - additionalProperties: false - description: - snoc-mm is a child of snoc, sharing snoc's register address space. - - properties: - compatible: - enum: - - qcom,msm8939-snoc-mm - - '#interconnect-cells': - const: 1 - - clock-names: - items: - - const: bus - - const: bus_a - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - - required: - - compatible - - '#interconnect-cells' - - clock-names - - clocks - required: - compatible - reg @@ -98,9 +63,6 @@ allOf: - qcom,msm8916-bimc - qcom,msm8916-pcnoc - qcom,msm8916-snoc - - qcom,msm8939-bimc - - qcom,msm8939-pcnoc - - qcom,msm8939-snoc - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc @@ -117,17 +79,6 @@ allOf: - description: Bus Clock - description: Bus A Clock - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,msm8939-snoc - then: - patternProperties: - '^interconnect-[a-z0-9]+$': false - examples: - | #include From df786235af03eeb09e5dc139ad8dcbba6346e357 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:32 +0200 Subject: [PATCH 15/36] dt-bindings: interconnect: qcom: rpm: Clean up the file Following the recent cleanups and untanglements, remove abusive direct references to RPM bus clocks, include the rpm-common YAML and update Georgi's email. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-6-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,rpm.yaml | 62 ++----------------- 1 file changed, 5 insertions(+), 57 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 72856b1c4210e..157efd47904d8 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -7,13 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm RPM Network-On-Chip Interconnect maintainers: - - Georgi Djakov + - Georgi Djakov description: | RPM interconnect providers support system bandwidth requirements through RPM processor. The provider is able to communicate with the RPM through the RPM shared memory device. +allOf: + - $ref: qcom,rpm-common.yaml# + properties: reg: maxItems: 1 @@ -27,57 +30,11 @@ properties: - qcom,qcs404-pcnoc - qcom,qcs404-snoc - '#interconnect-cells': - description: | - Value: <1> is one cell in an interconnect specifier for the - interconnect node id, <2> requires the interconnect node id and an - extra path tag. - enum: [ 1, 2 ] - - clocks: - minItems: 2 - maxItems: 7 - - clock-names: - minItems: 2 - maxItems: 7 - - power-domains: - maxItems: 1 - required: - compatible - reg - - '#interconnect-cells' - - clock-names - - clocks - -additionalProperties: false - -allOf: - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8916-bimc - - qcom,msm8916-pcnoc - - qcom,msm8916-snoc - - qcom,qcs404-bimc - - qcom,qcs404-pcnoc - - qcom,qcs404-snoc - - then: - properties: - clock-names: - items: - - const: bus - - const: bus_a - clocks: - items: - - description: Bus Clock - - description: Bus A Clock +unevaluatedProperties: false examples: - | @@ -87,25 +44,16 @@ examples: compatible = "qcom,msm8916-bimc"; reg = <0x00400000 0x62000>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; }; pcnoc: interconnect@500000 { compatible = "qcom,msm8916-pcnoc"; reg = <0x00500000 0x11000>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, - <&rpmcc RPM_SMD_PCNOC_A_CLK>; }; snoc: interconnect@580000 { compatible = "qcom,msm8916-snoc"; reg = <0x00580000 0x14000>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; }; From 1ecbcc0d5be444415c139d2c8d84dd9bf94845cb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 24 Jul 2023 16:06:33 +0200 Subject: [PATCH 16/36] dt-bindings: interconnect: qcom: rpm: Clean up the example One example is enough, remove the others and fix up the indentation while at it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230721-topic-icc_bindings-v2-7-e33d5acbf3bd@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,rpm.yaml | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 157efd47904d8..08c1c6b9d7cf8 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -41,19 +41,7 @@ examples: #include bimc: interconnect@400000 { - compatible = "qcom,msm8916-bimc"; - reg = <0x00400000 0x62000>; - #interconnect-cells = <1>; - }; - - pcnoc: interconnect@500000 { - compatible = "qcom,msm8916-pcnoc"; - reg = <0x00500000 0x11000>; - #interconnect-cells = <1>; - }; - - snoc: interconnect@580000 { - compatible = "qcom,msm8916-snoc"; - reg = <0x00580000 0x14000>; - #interconnect-cells = <1>; + compatible = "qcom,msm8916-bimc"; + reg = <0x00400000 0x62000>; + #interconnect-cells = <1>; }; From 8517824f0e94d52ab82742106314f0b8875e03c4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:44 +0200 Subject: [PATCH 17/36] interconnect: qcom: qdu1000: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 1f51339f7dd0 ("interconnect: qcom: Add QDU1000/QRU1000 interconnect driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-1-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/qdu1000.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index bf800dd7d4ba1..a7392eb73d4a9 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -769,6 +769,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .num_nodes = 1, .nodes = { &ebi }, }; From 1ad83c4792722fe134c1352591420702ff7b9091 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:45 +0200 Subject: [PATCH 18/36] interconnect: qcom: sc7180: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 2d1f95ab9feb ("interconnect: qcom: Add SC7180 interconnect provider driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-2-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc7180.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index d94ab9b39f3db..af2be15438403 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1238,6 +1238,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From 437b8e7fcd5df792cb8b8095e9f6eccefec6c099 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:46 +0200 Subject: [PATCH 19/36] interconnect: qcom: sc7280: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 46bdcac533cc ("interconnect: qcom: Add SC7280 interconnect provider driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-3-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc7280.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 6592839b4d94b..a626dbc719995 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1285,6 +1285,7 @@ static struct qcom_icc_node srvc_snoc = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .num_nodes = 1, .nodes = { &ebi }, }; From 0fcaaed3ff4b99e5b688b799f48989f1e4bb8a8b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:47 +0200 Subject: [PATCH 20/36] interconnect: qcom: sc8180x: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 9c8c6bac1ae8 ("interconnect: qcom: Add SC8180x providers") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-4-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc8180x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 0fb4898dabcfe..bdd3471d4ac89 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1345,6 +1345,7 @@ static struct qcom_icc_node slv_qup_core_2 = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .num_nodes = 1, .nodes = { &slv_ebi } }; From 688ffb3dcf85fc4b7ea82af842493013747a9e2c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:48 +0200 Subject: [PATCH 21/36] interconnect: qcom: sc8280xp: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: f29dabda7917 ("interconnect: qcom: Add SC8280XP interconnect provider") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-5-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sc8280xp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index b82c5493cbb56..0270f6c64481a 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -1712,6 +1712,7 @@ static struct qcom_icc_node srvc_snoc = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .num_nodes = 1, .nodes = { &ebi }, }; From 7b85ea8b9300be5c2818e1f61a274ff2c4c063ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:49 +0200 Subject: [PATCH 22/36] interconnect: qcom: sdm670: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 7e438e18874e ("interconnect: qcom: add sdm670 interconnects") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-6-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdm670.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index 540a2108b77c1..907e1ff4ff817 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1047,6 +1047,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From f8fe97a9fd2098de0570387029065eef657d50ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:50 +0200 Subject: [PATCH 23/36] interconnect: qcom: sdm845: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: b5d2f741077a ("interconnect: qcom: Add sdm845 interconnect provider driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-7-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sdm845.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index b9243c0aa626c..855802be93fea 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1265,6 +1265,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From fe7a3abf4111992af3de51d22383a8e8a0affe1e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:51 +0200 Subject: [PATCH 24/36] interconnect: qcom: sm6350: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 6a6eff73a954 ("interconnect: qcom: Add SM6350 driver support") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-8-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm6350.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 49aed492e9b80..f41d7e19ba269 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1164,6 +1164,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From 7ed42176406e5a2c9a5767d0d75690c7d1588027 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:52 +0200 Subject: [PATCH 25/36] interconnect: qcom: sm8150: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: a09b817c8bad ("interconnect: qcom: Add SM8150 interconnect provider driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-9-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8150.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index c7c9cf7f746b0..edfe824cad353 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1282,6 +1282,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From 9434c6896123141ac1f8f18b3d1751abbecdd03f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:53 +0200 Subject: [PATCH 26/36] interconnect: qcom: sm8250: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: 6df5b349491e ("interconnect: qcom: Add SM8250 interconnect provider driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-10-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8250.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index d4a4ecef11f01..661dc18d99dba 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -1397,6 +1397,7 @@ static struct qcom_icc_node qup2_core_slave = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From df1b8356a80ab47a7623e08facf36fe434ea9722 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Aug 2023 01:20:54 +0200 Subject: [PATCH 27/36] interconnect: qcom: sm8350: Set ACV enable_mask ACV expects an enable_mask corresponding to the APPS RSC, fill it in. Fixes: d26a56674497 ("interconnect: qcom: Add SM8350 interconnect provider driver") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-acv-v2-11-765ad70e539a@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/sm8350.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index bdf75839e6d17..562322d4fc3c4 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1356,6 +1356,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .enable_mask = BIT(3), .keepalive = false, .num_nodes = 1, .nodes = { &ebi }, From 956329ec7c5eba430211b48cca1b0372b4a4d702 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 13 Sep 2023 19:40:55 +0530 Subject: [PATCH 28/36] dt-bindings: interconnect: Add compatibles for SDX75 Add dt-bindings compatibles and interconnect IDs for Qualcomm SDX75 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1694614256-24109-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Georgi Djakov --- .../interconnect/qcom,sdx75-rpmh.yaml | 92 ++++++++++++++++ include/dt-bindings/interconnect/qcom,sdx75.h | 102 ++++++++++++++++++ 2 files changed, 194 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,sdx75.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml new file mode 100644 index 0000000000000..71cf7e252bfc8 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75 + +maintainers: + - Rohit Agarwal + +description: + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + compatible: + enum: + - qcom,sdx75-clk-virt + - qcom,sdx75-dc-noc + - qcom,sdx75-gem-noc + - qcom,sdx75-mc-virt + - qcom,sdx75-pcie-anoc + - qcom,sdx75-system-noc + + '#interconnect-cells': true + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx75-clk-virt + - qcom,sdx75-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx75-clk-virt + then: + properties: + clocks: + items: + - description: RPMH CC QPIC Clock + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + + clk_virt: interconnect-0 { + compatible = "qcom,sdx75-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + }; + + system_noc: interconnect@1640000 { + compatible = "qcom,sdx75-system-noc"; + reg = <0x1640000 0x4b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/include/dt-bindings/interconnect/qcom,sdx75.h b/include/dt-bindings/interconnect/qcom,sdx75.h new file mode 100644 index 0000000000000..e903f5f3dd8f6 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdx75.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H + +#define MASTER_QPIC_CORE 0 +#define MASTER_QUP_CORE_0 1 +#define SLAVE_QPIC_CORE 2 +#define SLAVE_QUP_CORE_0 3 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LAGG_CFG 1 +#define SLAVE_MCCC_MASTER 2 +#define SLAVE_GEM_NOC_CFG 3 +#define SLAVE_SNOOP_BWMON 4 + +#define MASTER_SYS_TCU 0 +#define MASTER_APPSS_PROC 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_MSS_PROC 3 +#define MASTER_ANOC_PCIE_GEM_NOC 4 +#define MASTER_SNOC_SF_MEM_NOC 5 +#define MASTER_GIC 6 +#define MASTER_IPA_PCIE 7 +#define SLAVE_GEM_NOC_CNOC 8 +#define SLAVE_LLCC 9 +#define SLAVE_MEM_NOC_PCIE_SNOC 10 +#define SLAVE_SERVICE_GEM_NOC 11 + +#define MASTER_PCIE_0 0 +#define MASTER_PCIE_1 1 +#define MASTER_PCIE_2 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 + +#define MASTER_AUDIO 0 +#define MASTER_GIC_AHB 1 +#define MASTER_PCIE_RSCC 2 +#define MASTER_QDSS_BAM 3 +#define MASTER_QPIC 4 +#define MASTER_QUP_0 5 +#define MASTER_ANOC_SNOC 6 +#define MASTER_GEM_NOC_CNOC 7 +#define MASTER_GEM_NOC_PCIE_SNOC 8 +#define MASTER_SNOC_CFG 9 +#define MASTER_PCIE_ANOC_CFG 10 +#define MASTER_CRYPTO 11 +#define MASTER_IPA 12 +#define MASTER_MVMSS 13 +#define MASTER_EMAC_0 14 +#define MASTER_EMAC_1 15 +#define MASTER_QDSS_ETR 16 +#define MASTER_QDSS_ETR_1 17 +#define MASTER_SDCC_1 18 +#define MASTER_SDCC_4 19 +#define MASTER_USB3_0 20 +#define SLAVE_ETH0_CFG 21 +#define SLAVE_ETH1_CFG 22 +#define SLAVE_AUDIO 23 +#define SLAVE_CLK_CTL 24 +#define SLAVE_CRYPTO_0_CFG 25 +#define SLAVE_IMEM_CFG 26 +#define SLAVE_IPA_CFG 27 +#define SLAVE_IPC_ROUTER_CFG 28 +#define SLAVE_CNOC_MSS 29 +#define SLAVE_ICBDI_MVMSS_CFG 30 +#define SLAVE_PCIE_0_CFG 31 +#define SLAVE_PCIE_1_CFG 32 +#define SLAVE_PCIE_2_CFG 33 +#define SLAVE_PCIE_RSC_CFG 34 +#define SLAVE_PDM 35 +#define SLAVE_PRNG 36 +#define SLAVE_QDSS_CFG 37 +#define SLAVE_QPIC 38 +#define SLAVE_QUP_0 39 +#define SLAVE_SDCC_1 40 +#define SLAVE_SDCC_4 41 +#define SLAVE_SPMI_VGI_COEX 42 +#define SLAVE_TCSR 43 +#define SLAVE_TLMM 44 +#define SLAVE_USB3 45 +#define SLAVE_USB3_PHY_CFG 46 +#define SLAVE_A1NOC_CFG 47 +#define SLAVE_DDRSS_CFG 48 +#define SLAVE_SNOC_GEM_NOC_SF 49 +#define SLAVE_SNOC_CFG 50 +#define SLAVE_PCIE_ANOC_CFG 51 +#define SLAVE_IMEM 52 +#define SLAVE_SERVICE_PCIE_ANOC 53 +#define SLAVE_SERVICE_SNOC 54 +#define SLAVE_PCIE_0 55 +#define SLAVE_PCIE_1 56 +#define SLAVE_PCIE_2 57 +#define SLAVE_QDSS_STM 58 +#define SLAVE_TCU 59 + +#endif From 3642b4e5cbfe480892858f0209c6fd0a3172a103 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 13 Sep 2023 19:40:56 +0530 Subject: [PATCH 29/36] interconnect: qcom: Add SDX75 interconnect provider driver Add driver for the Qualcomm interconnect buses found in SDX75. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1694614256-24109-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sdx75.c | 1107 ++++++++++++++++++++++++++++ drivers/interconnect/qcom/sdx75.h | 97 +++ 4 files changed, 1215 insertions(+) create mode 100644 drivers/interconnect/qcom/sdx75.c create mode 100644 drivers/interconnect/qcom/sdx75.h diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 825b647d91696..62b516d38d03f 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -182,6 +182,15 @@ config INTERCONNECT_QCOM_SDX65 This is a driver for the Qualcomm Network-on-Chip on sdx65-based platforms. +config INTERCONNECT_QCOM_SDX75 + tristate "Qualcomm SDX75 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sdx75-based + platforms. + config INTERCONNECT_QCOM_SM6350 tristate "Qualcomm SM6350 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 80d9d2da95d14..c5320e293960a 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -23,6 +23,7 @@ qnoc-sdm670-objs := sdm670.o qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o qnoc-sdx65-objs := sdx65.o +qnoc-sdx75-objs := sdx75.o qnoc-sm6350-objs := sm6350.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o @@ -51,6 +52,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o +obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c new file mode 100644 index 0000000000000..7ef1f17f3292e --- /dev/null +++ b/drivers/interconnect/qcom/sdx75.c @@ -0,0 +1,1107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" +#include "sdx75.h" + +static struct qcom_icc_node qpic_core_master = { + .name = "qpic_core_master", + .id = SDX75_MASTER_QPIC_CORE, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_QPIC_CORE }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SDX75_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SDX75_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 4, + .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER, + SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SDX75_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SDX75_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, + SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = SDX75_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SERVICE_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .id = SDX75_MASTER_MSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, + SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SDX75_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, + SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SDX75_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_ipa2pcie = { + .name = "xm_ipa2pcie", + .id = SDX75_MASTER_IPA_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDX75_MASTER_LLCC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SDX75_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SDX75_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_2 = { + .name = "xm_pcie3_2", + .id = SDX75_MASTER_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qhm_audio = { + .name = "qhm_audio", + .id = SDX75_MASTER_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .id = SDX75_MASTER_GIC_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qhm_pcie_rscc = { + .name = "qhm_pcie_rscc", + .id = SDX75_MASTER_PCIE_RSCC, + .channels = 1, + .buswidth = 4, + .num_links = 31, + .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, + SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, + SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, + SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, + SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, + SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, + SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM, + SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG, + SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0, + SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4, + SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR, + SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3, + SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG, + SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG, + SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM, + SDX75_SLAVE_TCU }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDX75_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = SDX75_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SDX75_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = SDX75_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SDX75_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 32, + .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, + SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, + SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, + SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, + SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, + SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, + SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG, + SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG, + SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC, + SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1, + SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX, + SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM, + SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG, + SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG, + SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM, + SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1, + SDX75_SLAVE_PCIE_2 }, +}; + +static struct qcom_icc_node qnm_system_noc_cfg = { + .name = "qnm_system_noc_cfg", + .id = SDX75_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_system_noc_pcie_cfg = { + .name = "qnm_system_noc_pcie_cfg", + .id = SDX75_MASTER_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDX75_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SDX75_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qxm_mvmss = { + .name = "qxm_mvmss", + .id = SDX75_MASTER_MVMSS, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_emac_0 = { + .name = "xm_emac_0", + .id = SDX75_MASTER_EMAC_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_emac_1 = { + .name = "xm_emac_1", + .id = SDX75_MASTER_EMAC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_qdss_etr0 = { + .name = "xm_qdss_etr0", + .id = SDX75_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_qdss_etr1 = { + .name = "xm_qdss_etr1", + .id = SDX75_MASTER_QDSS_ETR_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SDX75_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SDX75_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = SDX75_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_SLAVE_A1NOC_CFG }, +}; + +static struct qcom_icc_node qpic_core_slave = { + .name = "qpic_core_slave", + .id = SDX75_SLAVE_QPIC_CORE, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SDX75_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lagg = { + .name = "qhs_lagg", + .id = SDX75_SLAVE_LAGG_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mccc_master = { + .name = "qhs_mccc_master", + .id = SDX75_SLAVE_MCCC_MASTER, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SDX75_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qss_snoop_bwmon = { + .name = "qss_snoop_bwmon", + .id = SDX75_SLAVE_SNOOP_BWMON, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc_cnoc = { + .name = "qns_gemnoc_cnoc", + .id = SDX75_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDX75_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SDX75_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDX75_SLAVE_EBI1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_pcie_gemnoc = { + .name = "qns_pcie_gemnoc", + .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node ps_eth0_cfg = { + .name = "ps_eth0_cfg", + .id = SDX75_SLAVE_ETH0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node ps_eth1_cfg = { + .name = "ps_eth1_cfg", + .id = SDX75_SLAVE_ETH1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_audio = { + .name = "qhs_audio", + .id = SDX75_SLAVE_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDX75_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_crypto_cfg = { + .name = "qhs_crypto_cfg", + .id = SDX75_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDX75_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDX75_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SDX75_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SDX75_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mvmss_cfg = { + .name = "qhs_mvmss_cfg", + .id = SDX75_SLAVE_ICBDI_MVMSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SDX75_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SDX75_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie2_cfg = { + .name = "qhs_pcie2_cfg", + .id = SDX75_SLAVE_PCIE_2_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie_rscc = { + .name = "qhs_pcie_rscc", + .id = SDX75_SLAVE_PCIE_RSC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDX75_SLAVE_PDM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDX75_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDX75_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = SDX75_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SDX75_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SDX75_SLAVE_SDCC_1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SDX75_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex = { + .name = "qhs_spmi_vgi_coex", + .id = SDX75_SLAVE_SPMI_VGI_COEX, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDX75_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SDX75_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SDX75_SLAVE_USB3, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3_phy = { + .name = "qhs_usb3_phy", + .id = SDX75_SLAVE_USB3_PHY_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a1noc = { + .name = "qns_a1noc", + .id = SDX75_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX75_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SDX75_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SDX75_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX75_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_system_noc_cfg = { + .name = "qns_system_noc_cfg", + .id = SDX75_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qns_system_noc_pcie_cfg = { + .name = "qns_system_noc_pcie_cfg", + .id = SDX75_SLAVE_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX75_MASTER_PCIE_ANOC_CFG }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDX75_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_pcie_system_noc = { + .name = "srvc_pcie_system_noc", + .id = SDX75_SLAVE_SERVICE_PCIE_ANOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_system_noc = { + .name = "srvc_system_noc", + .id = SDX75_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SDX75_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SDX75_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_2 = { + .name = "xs_pcie_2", + .id = SDX75_SLAVE_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDX75_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDX75_SLAVE_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 39, + .nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc, + &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc1, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_usb3, &qhs_usb3_phy, + &qns_ddrss_cfg, &qns_system_noc_cfg, + &qns_system_noc_pcie_cfg, &qxs_imem, + &srvc_pcie_system_noc, &srvc_system_noc, + &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_qp0 = { + .name = "QP0", + .num_nodes = 1, + .nodes = { &qpic_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .num_nodes = 10, + .nodes = { &alm_sys_tcu, &chm_apps, + &qnm_gemnoc_cfg, &qnm_mdsp, + &qnm_snoc_sf, &xm_gic, + &xm_ipa2pcie, &qns_gemnoc_cnoc, + &qns_pcie, &srvc_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 21, + .nodes = { &xm_pcie3_0, &xm_pcie3_1, + &xm_pcie3_2, &qhm_audio, + &qhm_gic, &qhm_qdss_bam, + &qhm_qpic, &qhm_qup0, + &qnm_gemnoc_pcie, &qnm_system_noc_cfg, + &qnm_system_noc_pcie_cfg, &qxm_crypto, + &qxm_ipa, &qxm_mvmss, + &xm_emac_0, &xm_emac_1, + &xm_qdss_etr0, &xm_qdss_etr1, + &xm_sdc1, &xm_sdc4, + &xm_usb3 }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 2, + .nodes = { &qnm_aggre_noc, &qns_a1noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 2, + .nodes = { &qnm_pcie, &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qp0, + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QPIC_CORE] = &qpic_core_master, + [MASTER_QUP_CORE_0] = &qup0_core_master, + [SLAVE_QPIC_CORE] = &qpic_core_slave, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, +}; + +static const struct qcom_icc_desc sdx75_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qnm_cnoc, + [SLAVE_LAGG_CFG] = &qhs_lagg, + [SLAVE_MCCC_MASTER] = &qhs_mccc_master, + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, + [SLAVE_SNOOP_BWMON] = &qss_snoop_bwmon, +}; + +static const struct qcom_icc_desc sdx75_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, + &bcm_sn4, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_GIC] = &xm_gic, + [MASTER_IPA_PCIE] = &xm_ipa2pcie, + [SLAVE_GEM_NOC_CNOC] = &qns_gemnoc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, + [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, +}; + +static const struct qcom_icc_desc sdx75_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sdx75_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn1, + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [MASTER_PCIE_2] = &xm_pcie3_2, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, +}; + +static const struct qcom_icc_desc sdx75_pcie_anoc = { + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_ce0, + &bcm_cn0, + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_AUDIO] = &qhm_audio, + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_PCIE_RSCC] = &qhm_pcie_rscc, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QPIC] = &qhm_qpic, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_ANOC_SNOC] = &qnm_aggre_noc, + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [MASTER_SNOC_CFG] = &qnm_system_noc_cfg, + [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_MVMSS] = &qxm_mvmss, + [MASTER_EMAC_0] = &xm_emac_0, + [MASTER_EMAC_1] = &xm_emac_1, + [MASTER_QDSS_ETR] = &xm_qdss_etr0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr1, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_USB3_0] = &xm_usb3, + [SLAVE_ETH0_CFG] = &ps_eth0_cfg, + [SLAVE_ETH1_CFG] = &ps_eth1_cfg, + [SLAVE_AUDIO] = &qhs_audio, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QPIC] = &qhs_qpic, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_SDCC_1] = &qhs_sdc1, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, + [SLAVE_A1NOC_CFG] = &qns_a1noc, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SNOC_CFG] = &qns_system_noc_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc, + [SLAVE_SERVICE_SNOC] = &srvc_system_noc, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_PCIE_2] = &xs_pcie_2, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sdx75_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sdx75-clk-virt", .data = &sdx75_clk_virt }, + { .compatible = "qcom,sdx75-dc-noc", .data = &sdx75_dc_noc }, + { .compatible = "qcom,sdx75-gem-noc", .data = &sdx75_gem_noc }, + { .compatible = "qcom,sdx75-mc-virt", .data = &sdx75_mc_virt }, + { .compatible = "qcom,sdx75-pcie-anoc", .data = &sdx75_pcie_anoc }, + { .compatible = "qcom,sdx75-system-noc", .data = &sdx75_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sdx75", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("SDX75 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h new file mode 100644 index 0000000000000..24e8871599201 --- /dev/null +++ b/drivers/interconnect/qcom/sdx75.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H +#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H + +#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0 +#define SDX75_MASTER_ANOC_SNOC 1 +#define SDX75_MASTER_APPSS_PROC 2 +#define SDX75_MASTER_AUDIO 3 +#define SDX75_MASTER_CNOC_DC_NOC 4 +#define SDX75_MASTER_CRYPTO 5 +#define SDX75_MASTER_EMAC_0 6 +#define SDX75_MASTER_EMAC_1 7 +#define SDX75_MASTER_GEM_NOC_CFG 8 +#define SDX75_MASTER_GEM_NOC_CNOC 9 +#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10 +#define SDX75_MASTER_GIC 11 +#define SDX75_MASTER_GIC_AHB 12 +#define SDX75_MASTER_IPA 13 +#define SDX75_MASTER_IPA_PCIE 14 +#define SDX75_MASTER_LLCC 15 +#define SDX75_MASTER_MSS_PROC 16 +#define SDX75_MASTER_MVMSS 17 +#define SDX75_MASTER_PCIE_0 18 +#define SDX75_MASTER_PCIE_1 19 +#define SDX75_MASTER_PCIE_2 20 +#define SDX75_MASTER_PCIE_ANOC_CFG 21 +#define SDX75_MASTER_PCIE_RSCC 22 +#define SDX75_MASTER_QDSS_BAM 23 +#define SDX75_MASTER_QDSS_ETR 24 +#define SDX75_MASTER_QDSS_ETR_1 25 +#define SDX75_MASTER_QPIC 26 +#define SDX75_MASTER_QPIC_CORE 27 +#define SDX75_MASTER_QUP_0 28 +#define SDX75_MASTER_QUP_CORE_0 29 +#define SDX75_MASTER_SDCC_1 30 +#define SDX75_MASTER_SDCC_4 31 +#define SDX75_MASTER_SNOC_CFG 32 +#define SDX75_MASTER_SNOC_SF_MEM_NOC 33 +#define SDX75_MASTER_SYS_TCU 34 +#define SDX75_MASTER_USB3_0 35 +#define SDX75_SLAVE_A1NOC_CFG 36 +#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37 +#define SDX75_SLAVE_AUDIO 38 +#define SDX75_SLAVE_CLK_CTL 39 +#define SDX75_SLAVE_CRYPTO_0_CFG 40 +#define SDX75_SLAVE_CNOC_MSS 41 +#define SDX75_SLAVE_DDRSS_CFG 42 +#define SDX75_SLAVE_EBI1 43 +#define SDX75_SLAVE_ETH0_CFG 44 +#define SDX75_SLAVE_ETH1_CFG 45 +#define SDX75_SLAVE_GEM_NOC_CFG 46 +#define SDX75_SLAVE_GEM_NOC_CNOC 47 +#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48 +#define SDX75_SLAVE_IMEM 49 +#define SDX75_SLAVE_IMEM_CFG 50 +#define SDX75_SLAVE_IPA_CFG 51 +#define SDX75_SLAVE_IPC_ROUTER_CFG 52 +#define SDX75_SLAVE_LAGG_CFG 53 +#define SDX75_SLAVE_LLCC 54 +#define SDX75_SLAVE_MCCC_MASTER 55 +#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56 +#define SDX75_SLAVE_PCIE_0 57 +#define SDX75_SLAVE_PCIE_1 58 +#define SDX75_SLAVE_PCIE_2 59 +#define SDX75_SLAVE_PCIE_0_CFG 60 +#define SDX75_SLAVE_PCIE_1_CFG 61 +#define SDX75_SLAVE_PCIE_2_CFG 62 +#define SDX75_SLAVE_PCIE_ANOC_CFG 63 +#define SDX75_SLAVE_PCIE_RSC_CFG 64 +#define SDX75_SLAVE_PDM 65 +#define SDX75_SLAVE_PRNG 66 +#define SDX75_SLAVE_QDSS_CFG 67 +#define SDX75_SLAVE_QDSS_STM 68 +#define SDX75_SLAVE_QPIC 69 +#define SDX75_SLAVE_QPIC_CORE 70 +#define SDX75_SLAVE_QUP_0 71 +#define SDX75_SLAVE_QUP_CORE_0 72 +#define SDX75_SLAVE_SDCC_1 73 +#define SDX75_SLAVE_SDCC_4 74 +#define SDX75_SLAVE_SERVICE_GEM_NOC 75 +#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76 +#define SDX75_SLAVE_SERVICE_SNOC 77 +#define SDX75_SLAVE_SNOC_CFG 78 +#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79 +#define SDX75_SLAVE_SNOOP_BWMON 80 +#define SDX75_SLAVE_SPMI_VGI_COEX 81 +#define SDX75_SLAVE_TCSR 82 +#define SDX75_SLAVE_TCU 83 +#define SDX75_SLAVE_TLMM 84 +#define SDX75_SLAVE_USB3 85 +#define SDX75_SLAVE_USB3_PHY_CFG 86 + +#endif From 80f5fef01beeda54ec9c1f9049d331e480be80e8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 20 Sep 2023 18:34:32 +0300 Subject: [PATCH 30/36] interconnect: imx: Replace custom implementation of COUNT_ARGS() Replace custom and non-portable implementation of COUNT_ARGS(). Fixes: f0d8048525d7 ("interconnect: Add imx core driver") Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230920153432.2067664-1-andriy.shevchenko@linux.intel.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/imx.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h index 895907cdcb3bc..4ec9bc5f383ea 100644 --- a/drivers/interconnect/imx/imx.h +++ b/drivers/interconnect/imx/imx.h @@ -10,6 +10,7 @@ #ifndef __DRIVERS_INTERCONNECT_IMX_H #define __DRIVERS_INTERCONNECT_IMX_H +#include #include #include @@ -89,7 +90,7 @@ struct imx_icc_noc_setting { .id = _id, \ .name = _name, \ .adj = _adj, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .num_links = COUNT_ARGS(__VA_ARGS__), \ .links = { __VA_ARGS__ }, \ } From e753741421965e5033c5bf6264fc8370ad01a400 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 20 Sep 2023 18:41:31 +0300 Subject: [PATCH 31/36] interconnect: msm8974: Replace custom implementation of COUNT_ARGS() Replace custom and non-portable implementation of COUNT_ARGS(). Fixes: 4e60a9568dc6 ("interconnect: qcom: add msm8974 driver") Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230920154131.2071112-1-andriy.shevchenko@linux.intel.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/msm8974.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index 885ca9d6d4ed8..21f6c852141e3 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -28,6 +28,8 @@ */ #include + +#include #include #include #include @@ -231,7 +233,7 @@ struct msm8974_icc_desc { .buswidth = _buswidth, \ .mas_rpm_id = _mas_rpm_id, \ .slv_rpm_id = _slv_rpm_id, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .num_links = COUNT_ARGS(__VA_ARGS__), \ .links = { __VA_ARGS__ }, \ } From 577a3c5af1fe87b65931ea94d5515266da301f56 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 20 Sep 2023 18:49:27 +0300 Subject: [PATCH 32/36] interconnect: qcom: osm-l3: Replace custom implementation of COUNT_ARGS() Replace custom and non-portable implementation of COUNT_ARGS(). Fixes: 5bc9900addaf ("interconnect: qcom: Add OSM L3 interconnect provider support") Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230920154927.2090732-1-andriy.shevchenko@linux.intel.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/osm-l3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index dc321bb86d0be..e97478bbc2825 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -3,6 +3,7 @@ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -78,7 +79,7 @@ enum { .name = #_name, \ .id = _id, \ .buswidth = _buswidth, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .num_links = COUNT_ARGS(__VA_ARGS__), \ .links = { __VA_ARGS__ }, \ } From 273f74a2e7d15a5c216a4a26b84b1563c7092c9d Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 3 Aug 2023 21:05:21 +0800 Subject: [PATCH 33/36] interconnect: fix error handling in qnoc_probe() Add missing clk_disable_unprepare() and clk_bulk_disable_unprepare() in the error path in qnoc_probe(). And when qcom_icc_qos_set() fails, it needs remove nodes and disable clks. Fixes: 2e2113c8a64f ("interconnect: qcom: rpm: Handle interface clocks") Signed-off-by: Yang Yingliang Link: https://lore.kernel.org/r/20230803130521.959487-1-yangyingliang@huawei.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 2c16917ba1fda..e76356f91125f 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -497,7 +497,7 @@ int qnoc_probe(struct platform_device *pdev) ret = devm_clk_bulk_get(dev, qp->num_intf_clks, qp->intf_clks); if (ret) - return ret; + goto err_disable_unprepare_clk; provider = &qp->provider; provider->dev = dev; @@ -512,13 +512,15 @@ int qnoc_probe(struct platform_device *pdev) /* If this fails, bus accesses will crash the platform! */ ret = clk_bulk_prepare_enable(qp->num_intf_clks, qp->intf_clks); if (ret) - return ret; + goto err_disable_unprepare_clk; for (i = 0; i < num_nodes; i++) { size_t j; node = icc_node_create(qnodes[i]->id); if (IS_ERR(node)) { + clk_bulk_disable_unprepare(qp->num_intf_clks, + qp->intf_clks); ret = PTR_ERR(node); goto err_remove_nodes; } @@ -534,8 +536,11 @@ int qnoc_probe(struct platform_device *pdev) if (qnodes[i]->qos.ap_owned && qnodes[i]->qos.qos_mode != NOC_QOS_MODE_INVALID) { ret = qcom_icc_qos_set(node); - if (ret) - return ret; + if (ret) { + clk_bulk_disable_unprepare(qp->num_intf_clks, + qp->intf_clks); + goto err_remove_nodes; + } } data->nodes[i] = node; @@ -563,6 +568,7 @@ int qnoc_probe(struct platform_device *pdev) icc_provider_deregister(provider); err_remove_nodes: icc_nodes_remove(provider); +err_disable_unprepare_clk: clk_disable_unprepare(qp->bus_clk); return ret; From 6548ecdfc16327aafeaa1f1d97f63c79995a56cb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 20 Sep 2023 18:36:45 +0300 Subject: [PATCH 34/36] interconnect: imx: Replace inclusion of kernel.h in the header The kernel.h is not used here directly, replace it with proper set of headers. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230920153645.2068193-1-andriy.shevchenko@linux.intel.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/imx.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h index 4ec9bc5f383ea..d4d0e98886557 100644 --- a/drivers/interconnect/imx/imx.h +++ b/drivers/interconnect/imx/imx.h @@ -11,8 +11,12 @@ #define __DRIVERS_INTERCONNECT_IMX_H #include +#include +#include + #include -#include + +struct platform_device; #define IMX_ICC_MAX_LINKS 4 From 4d8784d84e17529f0f0774d3a946fd07057cd9a4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 27 Aug 2023 13:40:26 +0200 Subject: [PATCH 35/36] dt-bindings: interconnect: qcom,rpmh: do not require reg on SDX65 MC virt The MC virt interconnect in SDX65 DTSI does not have reg. Similarly in the downstream DTS, thus assume this is an interconnect without own dedicated IO address space. This fixes dtbs_check warnings like: qcom-sdx65-mtp.dtb: interconnect-mc-virt: 'reg' is a required property Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230827114026.47806-1-krzysztof.kozlowski@linaro.org Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index a46497af1fd8d..74ab080249ff8 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -113,6 +113,7 @@ allOf: properties: compatible: enum: + - qcom,sdx65-mc-virt - qcom,sm8250-qup-virt then: required: From c8fd5a37340f9dfb02f7c340d7b602bd2f7ec449 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 15 Oct 2023 15:59:56 +0200 Subject: [PATCH 36/36] interconnect: qcom: Convert to platform remove callback returning void MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Several drivers use qcom_icc_rpmh_remove() as remove callback which returns zero unconditionally. Make it return void and use .remove_new in the drivers. There is no change in behaviour. Signed-off-by: Uwe Kleine-König Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231015135955.1537751-2-u.kleine-koenig@pengutronix.de Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpmh.c | 4 +--- drivers/interconnect/qcom/icc-rpmh.h | 2 +- drivers/interconnect/qcom/qdu1000.c | 2 +- drivers/interconnect/qcom/sa8775p.c | 2 +- drivers/interconnect/qcom/sc7180.c | 2 +- drivers/interconnect/qcom/sc7280.c | 2 +- drivers/interconnect/qcom/sc8180x.c | 2 +- drivers/interconnect/qcom/sc8280xp.c | 2 +- drivers/interconnect/qcom/sdm670.c | 2 +- drivers/interconnect/qcom/sdm845.c | 2 +- drivers/interconnect/qcom/sdx55.c | 2 +- drivers/interconnect/qcom/sdx65.c | 2 +- drivers/interconnect/qcom/sdx75.c | 2 +- drivers/interconnect/qcom/sm6350.c | 2 +- drivers/interconnect/qcom/sm8150.c | 2 +- drivers/interconnect/qcom/sm8250.c | 2 +- drivers/interconnect/qcom/sm8350.c | 2 +- drivers/interconnect/qcom/sm8450.c | 2 +- drivers/interconnect/qcom/sm8550.c | 2 +- 19 files changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index b9f27ce3b6075..c1aa265c1f4ef 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -253,14 +253,12 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) } EXPORT_SYMBOL_GPL(qcom_icc_rpmh_probe); -int qcom_icc_rpmh_remove(struct platform_device *pdev) +void qcom_icc_rpmh_remove(struct platform_device *pdev) { struct qcom_icc_provider *qp = platform_get_drvdata(pdev); icc_provider_deregister(&qp->provider); icc_nodes_remove(&qp->provider); - - return 0; } EXPORT_SYMBOL_GPL(qcom_icc_rpmh_remove); diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 5f0af8b1fc439..2de29460e8082 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -126,6 +126,6 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst); int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev); void qcom_icc_pre_aggregate(struct icc_node *node); int qcom_icc_rpmh_probe(struct platform_device *pdev); -int qcom_icc_rpmh_remove(struct platform_device *pdev); +void qcom_icc_rpmh_remove(struct platform_device *pdev); #endif diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index bf800dd7d4ba1..4a5089002364c 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -1045,7 +1045,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-qdu1000", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index ef1b5e326089d..dd6281db08adf 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -2519,7 +2519,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sa8775p", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index d94ab9b39f3db..3f1a0f358e0d2 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1806,7 +1806,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc7180", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 6592839b4d94b..6292af8242d49 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1834,7 +1834,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc7280", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 0fb4898dabcfe..6eaf4e1e43840 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1887,7 +1887,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8180x", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index b82c5493cbb56..633b5740b9a39 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -2390,7 +2390,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8280xp", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index 540a2108b77c1..900ee47b2b870 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1532,7 +1532,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdm670", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index b9243c0aa626c..5176addf347b5 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1801,7 +1801,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdm845", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 4117db046fa00..e97f28b8d2b25 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -913,7 +913,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx55", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index d3a6c6c148e5d..2f3f5479d8a51 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -897,7 +897,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx65", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c index 7ef1f17f3292e..7f422c27488d3 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -1083,7 +1083,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx75", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 49aed492e9b80..f1907cb9891f8 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1701,7 +1701,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm6350", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index c7c9cf7f746b0..ce2ebbd404f6b 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1863,7 +1863,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8150", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index d4a4ecef11f01..4db468f3ec397 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -1990,7 +1990,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8250", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index bdf75839e6d17..046e20046054a 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1960,7 +1960,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8350", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index eb7e17df32ba6..b3cd0087377ca 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1884,7 +1884,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8450", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index a10c8b6549ee6..629faa4c9aaee 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -2219,7 +2219,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove = qcom_icc_rpmh_remove, + .remove_new = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8550", .of_match_table = qnoc_of_match,