From 8041edb5920902adc9b28f2fcd9ccce395434ead Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Wed, 8 May 2019 00:17:55 +0200 Subject: [PATCH] MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA The config0 register in the Xburst CPUs with a processor ID of PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, but they don't actually support this ISA. Signed-off-by: Paul Cercueil Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: od@zcrc.me Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- arch/mips/kernel/cpu-probe.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index d5e335e6846a9..6126b77d5a62b 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1973,6 +1973,14 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) panic("Unknown Ingenic Processor ID!"); break; } + + /* + * The config0 register in the Xburst CPUs with a processor ID of + * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, + * but they don't actually support this ISA. + */ + if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0) + c->isa_level &= ~MIPS_CPU_ISA_M32R2; } static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)