From 3db59e1ca693455d0710dc217455fe81d0d32dce Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 Apr 2023 20:31:57 +0200 Subject: [PATCH 01/44] ARM: dts: stm32: add part number for STM32MP15x The STM32MP15x Device Part Number is located in the first 8 bits of OTP4, this patch add its description as the NVMEM cell. Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 63f4c78fcc1dc..664825418c32c 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1620,6 +1620,9 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + part_number_otp: part-number-otp@4 { + reg = <0x4 0x1>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; From 04127a3d30bd7ef7956b894724ca031728154e54 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 16 May 2023 12:31:11 +0200 Subject: [PATCH 02/44] ARM: dts: stm32: remove extra space in stm32mp15xx-dkx.dtsi Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi. Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index cefeeb00fc228..0f1110e42c939 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -379,21 +379,21 @@ regulator-always-on; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = ; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - }; + }; - vbus_sw: pwr_sw2 { + vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; regulator-active-discharge = <1>; - }; + }; }; onkey { From e0040abb8d5bb2215f8ee08e0e2d05052a004288 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 7 Apr 2023 23:01:52 +0200 Subject: [PATCH 03/44] ARM: dts: stm32: Replace deprecated st,hw-flow-ctrl with uart-has-rtscts Replace deprecated st,hw-flow-ctrl with uart-has-rtscts . No functional change. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h750i-art-pi.dts | 2 +- arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 4 ++-- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts index f3e70d3b65ac4..44c307f8b09cf 100644 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts @@ -208,7 +208,7 @@ dmas = <&dmamux1 45 0x400 0x05>, <&dmamux1 46 0x400 0x05>; dma-names = "rx", "tx"; - st,hw-flow-ctrl; + uart-has-rtscts; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index 3a36f7fe0a2c3..5f85598cc7c6b 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -287,7 +287,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&usart2_pins_b>; pinctrl-1 = <&usart2_sleep_pins_b>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; @@ -297,7 +297,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_c>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 50af4a27d6be4..8232bbbae379c 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -452,7 +452,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; From 9660efc2af37f3c12dc6e6a5511ad99e0addc297 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 5 May 2023 23:37:29 +0200 Subject: [PATCH 04/44] ARM: dts: stm32: Move ethernet MAC EEPROM from SoM to carrier boards The ethernet MAC EEPROM is not populated on the SoM itself, it has to be populated on each carrier board. Move the EEPROM into the correct place in DTs, i.e. the carrier board DTs. Add label to the EEPROM too. Fixes: 7e76f82acd9e1 ("ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 ++++++ arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi | 6 ++++++ arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 6 ------ arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 8 ++++++++ 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 8232bbbae379c..302efac5d26f0 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -321,6 +321,12 @@ }; }; }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; <dc { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi index c32c160f97f20..39af79dc654cc 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -192,6 +192,12 @@ reg = <0x50>; pagesize = <16>; }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &sdmmc1 { /* MicroSD */ diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index bb40fb46da81d..bba19f21e5277 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -213,12 +213,6 @@ status = "disabled"; }; }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; }; &ipcc { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi index 5fdb74b652aca..faed31b6d84a1 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -90,6 +90,14 @@ }; }; +&i2c4 { + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; From 7a5f349e592c254f3c1ac34665b6c3905576efc2 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 16 May 2023 10:52:19 +0200 Subject: [PATCH 05/44] ARM: dts: stm32: use RCC macro for CRC node on stm32f746 The patch replaces the number 12 with the appropriate numerical constant already defined in the file stm32f7-rcc.h. Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f746.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index dc868e6da40e0..e3564b74a7791 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -515,7 +515,7 @@ crc: crc@40023000 { compatible = "st,stm32f7-crc"; reg = <0x40023000 0x400>; - clocks = <&rcc 0 12>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; status = "disabled"; }; From 303f3fe1d88f7e45e0ab63f37c0949953b69fc10 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:49 +0200 Subject: [PATCH 06/44] ARM: dts: stm32: Add alternate pinmux for ethernet for stm32mp15 Add another option for the ethernet0 pins. It is almost identical to ethernet0_rgmii_pins_c apart from TXD0/1. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 ++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e86d989dd351d..c20d59919fc9b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -341,6 +341,56 @@ }; }; + ethernet0_rgmii_pins_d: rgmii-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ From ab7a5cba8231306fce1125b4aadc9edda076902c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:50 +0200 Subject: [PATCH 07/44] ARM: dts: stm32: Add alternate pinmux for sai2b on stm32mp15 Add another option for the SAI2B pins. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Reviewed-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index c20d59919fc9b..f6661951258a1 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1491,6 +1491,30 @@ }; }; + sai2b_pins_d: sai2b-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + ; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_d: sai2b-sleep-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + , /* SAI2_MCLK_B */ + ; /* SAI2_SD_B */ + }; + }; + sai4a_pins_a: sai4a-0 { pins { pinmux = ; /* SAI4_SD_A */ From 8b8d017f5334f01646ab04bf4c5c33d9886f0d5c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:51 +0200 Subject: [PATCH 08/44] ARM: dts: stm32: Add new pinmux for sdmmc1_b4 on stm32mp15 Add another option for the SDMMC_B4 pins. It is almost identical to sdmmc1_b4_pins_a but the SDMMC1_D2 pin. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 54 ++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f6661951258a1..b4f36520f51bb 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1596,6 +1596,60 @@ }; }; + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = , /* SDMMC1_D0DIR */ From 2f18e152217d9d784e3ca8270547917cfc7d7440 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:52 +0200 Subject: [PATCH 09/44] ARM: dts: stm32: Add new pinmux for sdmmc2_d47 on stm32mp15 Add another option for the SDMMC_D47 pins. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index b4f36520f51bb..a1a994c9a48e1 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1887,6 +1887,27 @@ }; }; + sdmmc2_d47_pins_e: sdmmc2-d47-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ From 559b33d2a8c546c06a4e398da064e4a787ea4aab Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:53 +0200 Subject: [PATCH 10/44] ARM: dts: stm32: Add pinmux for USART1 pins on stm32mp15 Add a mux option for the USART1 pins. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 57 ++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a1a994c9a48e1..527c76c8be581 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2273,6 +2273,33 @@ }; }; + usart1_pins_a: usart1-0 { + pins1 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_CTS_NSS */ + bias-disable; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -2612,4 +2639,34 @@ bias-disable; }; }; + + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = ; /* USART1_TX */ + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; }; From 37f92e6930bd68830f3299f905fa8f208cc7a250 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:54 +0200 Subject: [PATCH 11/44] ARM: dts: stm32: Add idle/sleep pinmux for USART3 on stm32mp15 Add idle and sleep mux option for the USART3 pins_a. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 527c76c8be581..358cbe9ec9961 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2402,6 +2402,23 @@ }; }; + usart3_idle_pins_a: usart3-idle-0 { + pins1 { + pinmux = ; /* USART3_TX */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_a: usart3-sleep-0 { + pins { + pinmux = , /* USART3_TX */ + ; /* USART3_RX */ + }; + }; + usart3_pins_b: usart3-1 { pins1 { pinmux = , /* USART3_TX */ From d4b5f1a5a099d28169e05e138c91e69e00e5ab11 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:55 +0200 Subject: [PATCH 12/44] ARM: dts: stm32: Add sleep pinmux for SPI1 pins_a on stm32mp15 Add a sleep mux option for the SPI1 pins_a mux. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 358cbe9ec9961..06e969aa5fdb9 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2657,6 +2657,14 @@ }; }; + spi1_sleep_pins_a: spi1-sleep-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MISO */ + ; /* SPI1_MOSI */ + }; + }; + usart1_pins_b: usart1-1 { pins1 { pinmux = ; /* USART1_TX */ From e90227f0f3837ae2552196f26cbd48e576690d70 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:56 +0200 Subject: [PATCH 13/44] dt-bindings: arm: stm32: Add Phytec STM32MP1 board The Phytec STM32MP1 based SoMs feature up to 1 GB DDR3LP RAM, up to 1 GB eMMC, up to 16 MB QSPI and up to 128 GB NAND flash. Signed-off-by: Steffen Trumtrar Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 13e34241145b4..4af5b8f4f8032 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -155,6 +155,12 @@ properties: - const: seeed,stm32mp157c-odyssey-som - const: st,stm32mp157 + - description: Phytec STM32MP1 SoM based Boards + items: + - const: phytec,phycore-stm32mp1-3 + - const: phytec,phycore-stm32mp157c-som + - const: st,stm32mp157 + additionalProperties: true ... From 27538a18a4fcc7e8e20c9f71f9a622685a9d7c7b Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:57 +0200 Subject: [PATCH 14/44] ARM: dts: stm32: add STM32MP1-based Phytec SoM The Phytec STM32MP1 based SoMs feature up to 1 GB DDR3LP RAM, up to 1 GB eMMC, up to 16 MB QSPI and up to 128 GB NAND flash. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- .../stm32mp157c-phycore-stm32mp15-som.dtsi | 577 ++++++++++++++++++ 1 file changed, 577 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi new file mode 100644 index 0000000000000..4e8b2d2b30c7a --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi @@ -0,0 +1,577 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp15-pinctrl.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP15 SOM"; + compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + rtc0 = &i2c4_rtc; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-enter { + label = "Enter"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-PHYCORE"; + routing = + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ + "Capture", "MCLK"; + dais = <&sai2b_port>, + <&sai2a_port>; + }; + + regulator_vin: regulator { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rgmii_pins_d>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + st,eth-clk-sel; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + + codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + + ai3x-micbias-vg = <2>; + + AVDD-supply = <&v3v3>; + IOVDD-supply = <&v3v3>; + DRVDD-supply = <&v3v3>; + DVDD-supply = <&v1v8_audio>; + + clocks = <&sai2b>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tlv320_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + + tlv320_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touch@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + vio-supply = <&v3v3>; + vcc-supply = <&v3v3>; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + type = ; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <®ulator_vin>; + buck2-supply = <®ulator_vin>; + buck3-supply = <®ulator_vin>; + buck4-supply = <®ulator_vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <®ulator_vin>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + boost-supply = <®ulator_vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + vdd_eth_2v5: ldo2 { + regulator-name = "dd_eth_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + vdd_eth_1v0: ldo6 { + regulator-name = "vdd_eth_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , + ; + interrupt-names = "onkey-falling", + "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + }; + }; + + i2c4_eeprom: eeprom@50 { + compatible = "microchip,24c32", + "atmel,24c32"; + reg = <0x50>; + }; + + i2c4_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + status = "okay"; + + flash0: flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; + pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; + status = "okay"; +}; + +&sai2a { + dma-names = "rx"; + st,sync = <&sai2b 2>; + clocks = <&rcc SAI2_K>, <&sai2b>; + clock-names = "sai_ck", "MCLK"; + #clock-cells = <0>; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&tlv320_rx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sai2b { + dma-names = "tx"; + #clock-cells = <0>; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&tlv320_tx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; + cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + pinctrl-3 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_a>; + pinctrl-1 = <&usart3_sleep_pins_a>; + pinctrl-2 = <&usart3_idle_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; From b195a9d7f72139fe5c51e81684a698c7a8a5f34f Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:58 +0200 Subject: [PATCH 15/44] ARM: dts: stm32: add STM32MP1-based Phytec board Add the Phytec STM32MP1-3 Dev board. The devboard uses a Phytec stm32m157c-som. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 +- .../dts/stm32mp157c-phycore-stm32mp1-3.dts | 60 +++++++++++++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..4c1c96000f3bf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1266,7 +1266,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-ev1.dtb \ stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ - stm32mp157c-odyssey.dtb + stm32mp157c-odyssey.dtb \ + stm32mp157c-phycore-stm32mp1-3.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts new file mode 100644 index 0000000000000..28d7203264cea --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +/dts-v1/; + +#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp157c-phycore-stm32mp15-som.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; + compatible = "phytec,phycore-stm32mp1-3", + "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &usart1; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +&fmc { + status = "disabled"; +}; + +&gpu { + status = "okay"; +}; + +&i2c4_eeprom { + status = "okay"; +}; + +&i2c4_rtc { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&sdmmc2 { + status = "okay"; +}; From 9c994fcf52284ac4cdeee1633373d69e05e30b23 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 17 May 2023 09:48:29 +0200 Subject: [PATCH 16/44] ARM: dts: stm32: Update Cortex-M4 reset declarations on stm32mp15 Since the introduction of the SCMI for the management of the MCU hold boot in OP-TEE, management of the hold boot by SMC call is deprecated. - Clean the st,syscfg-tz which allows to determine if the trust zone is enable. - Add reset-names properties to be able to differentiate the MCU reset and the MCU HOLD BOOT. Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 664825418c32c..a98ae58e2c1c8 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1823,8 +1823,8 @@ <0x30000000 0x40000>, <0x38000000 0x10000>; resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; From 3b1583868691b6fb7d5f7452711cba0481e72292 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 17 May 2023 09:48:30 +0200 Subject: [PATCH 17/44] ARM: dts: stm32: fix m4_rproc references to use SCMI for stm32mp15 Fixes stm32mp15*-scmi DTS files introduced in [1]: This patch fixes the node which uses the MCU reset and adds the missing HOLD_BOOT which is also handled by the SCMI reset service. This change cannot be applied as a fix on commit [1], the management of the hold boot impacts also the stm32_rproc driver. [1] 'commit 5b7e58313a77 ("ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)")' Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 7 +++++-- arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 7 +++++-- arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 7 +++++-- arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 7 +++++-- 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts index e539cc80bef81..afcd6285890cc 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -55,8 +55,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts index 97e4f94b0a24e..39358d9020003 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -61,8 +61,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts index 9cf0a44d2f47e..07ea765a4553a 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -60,8 +60,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts index 3b9dd6f4ccc96..813086ec24895 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -66,8 +66,11 @@ resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { From 0cf765e598712addec34d0208cc1418c151fefb2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 May 2023 02:42:32 +0200 Subject: [PATCH 18/44] ARM: dts: stm32: Shorten the AV96 HDMI sound card name Fix the following error in kernel log due to too long sound card name: " asoc-audio-graph-card sound: ASoC: driver name too long 'STM32MP1-AV96-HDMI' -> 'STM32MP1-AV96-H' " Fixes: e027da342772 ("ARM: dts: stm32: Add bindings for audio on AV96") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 302efac5d26f0..2b52515457e4b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -87,7 +87,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-AV96-HDMI"; + label = "STM32-AV96-HDMI"; dais = <&sai2a_port>; status = "okay"; }; From 0c211488ef36db3d52c8b8ae9931e508272f5a11 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:56 +0200 Subject: [PATCH 19/44] ARM: dts: stm32: fix warnings on stm32f469-disco board Several warnings appear when building and checking stm32f429 device-tree: arch/arm/boot/dts/stm32f469-disco.dts:182.28-184.5: Warning (unit_address_vs_reg): /soc/display-controller@40016800/port/endpoint@0: node has a unit name, but no reg or ranges property .../arch/arm/boot/dts/stm32f469-disco.dtb: dsi@40016c00: Unevaluated properties are not allowed ('panel-dsi@0' was unexpected) From schema: .../Documentation/devicetree/bindings/display/st,stm32-dsi.yaml Fix those. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f469-disco.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 5a0daf8e8b118..cbbd521bf0108 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -160,7 +160,7 @@ }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; /* dsi virtual channel (0..3) */ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; @@ -179,7 +179,7 @@ status = "okay"; port { - ltdc_out_dsi: endpoint@0 { + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in>; }; }; From 45e418bd528f5c1ed6b8de7596cf523f10f74b7b Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:57 +0200 Subject: [PATCH 20/44] dt-bindings: display: st,stm32-dsi: Remove unnecessary fields "#address-cells" and "#size-cells" are two properties that are not mandatory. For instance, the DSI could refer to a bridge outside the scope of the node rather than include a 'panel@0' subnode. By doing so, address and size fields become then unnecessary, creating a warning at build time. Signed-off-by: Raphael Gallais-Pou Acked-by: Conor Dooley Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/display/st,stm32-dsi.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index c488308d7be13..53560052aaf00 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -74,8 +74,6 @@ properties: - const: 2 required: - - "#address-cells" - - "#size-cells" - compatible - reg - clocks From f7164b346a9009e5b70671bb72e32e1cc22a90b4 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:58 +0200 Subject: [PATCH 21/44] ARM: dts: stm32: fix dsi warnings on stm32mp15 boards Fixes DSI related warnings: * "#size-cells" and "#address-cells" wrongly used * Changed 'panel-dsi@0' to 'panel@0' according to dsi-controller.yaml Signed-off-by: Raphael Gallais-Pou Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157.dtsi | 7 ------- .../boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 3 +++ arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 3 +++ arch/arm/boot/dts/stm32mp157c-dk2.dts | 5 +++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 7 ++++++- 5 files changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi index 54e73ccea4464..5e733cd16ff9e 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/stm32mp157.dtsi @@ -24,14 +24,7 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 9a2a4bc7d0793..47d03bd9ef0b7 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -49,6 +49,9 @@ phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index 390ee8c057547..d2f68997a471b 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -49,6 +49,9 @@ phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in_ltdc: endpoint { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index ab13e340f4ef5..0067c6248cd18 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -31,10 +31,15 @@ }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index ba8e9d9a42faf..67c6b9440878e 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -101,9 +101,14 @@ &dsi { phy-dsi-supply = <®18>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { @@ -119,7 +124,7 @@ }; }; - panel-dsi@0 { + panel@0 { compatible = "raydium,rm68200"; reg = <0>; reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; From 5364e37799c83d405175b2e1e1065c7c247949b3 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:59 +0200 Subject: [PATCH 22/44] ARM: dts: stm32: fix ltdc warnings in stm32mp15 boards Those concern: * "#size-cells" and "#address-cells" wrongly used * residual "reg" property appearing on endpoints where it could be avoided Signed-off-by: Raphael Gallais-Pou Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 ----- .../boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 3 +-- arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 3 +-- .../dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 3 +-- arch/arm/boot/dts/stm32mp157c-dk2.dts | 3 +++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 3 +-- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 3 +-- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 +----- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 3 +-- 9 files changed, 10 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index a98ae58e2c1c8..bf3830dca7428 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1529,11 +1529,6 @@ clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - }; }; iwdg2: watchdog@5a002000 { diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 47d03bd9ef0b7..4279b26547dfd 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -107,8 +107,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index d2f68997a471b..efba542898207 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -107,8 +107,7 @@ status = "okay"; port { - ltdc_out_dsi: endpoint@0 { - reg = <0>; + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in_ltdc>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 0d7560ba2950f..5116a77852013 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -81,8 +81,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&panel_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 0067c6248cd18..4bef2300ed7ca 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -87,6 +87,9 @@ status = "okay"; port { + #address-cells = <1>; + #size-cells = <0>; + ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 67c6b9440878e..49ca94c19b02b 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -244,8 +244,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 407ed3952f75d..eada9cf257be9 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -161,8 +161,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&panel_input>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 2b52515457e4b..cdd4902b59a97 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -336,11 +336,7 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&adv7513_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 0f1110e42c939..a6e2e20f12fa0 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -457,8 +457,7 @@ status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&sii9022_in>; }; }; From 04d28eb48ff30c059069e27689c4638c8a17134e Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:29 +0200 Subject: [PATCH 23/44] ARM: dts: stm32: add adc internal channels to stm32mp15 Add STM32 ADC2 internal channels VREFINT and VDDCORE to STM32MP15x SoCs. VBAT internal channel is not defined by default in SoC DT, and has be defined in board DT when needed, instead. This avoids unwanted current consumption on battery, when ADC conversions are performed on any other channels. The internal channels are defined in STM32MP15 SoC DT according to the generic IIO channel bindings. The STM32 driver does not support a mixed use of legacy and generic channels. When generic channels are defined, legacy channels are ignored. This involves that the board device trees using legacy bindings for ADC2, have to be reworked. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bf3830dca7428..7b360ee1ba2b4 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1093,6 +1093,8 @@ adc1: adc@0 { compatible = "st,stm32mp1-adc"; #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x0>; interrupt-parent = <&adc>; interrupts = <0>; @@ -1104,12 +1106,22 @@ adc2: adc@100 { compatible = "st,stm32mp1-adc"; #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x100>; interrupt-parent = <&adc>; interrupts = <1>; dmas = <&dmamux1 10 0x400 0x01>; dma-names = "rx"; status = "disabled"; + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; }; }; From 5988bd535975486a0a550fa8fe8a4ca2fd9231c9 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:30 +0200 Subject: [PATCH 24/44] ARM: dts: stm32: add vrefint calibration on stm32mp15 Describe vrefint calibration cell to be retrieved through bsec. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7b360ee1ba2b4..3d0c39d847b5f 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1630,6 +1630,9 @@ part_number_otp: part-number-otp@4 { reg = <0x4 0x1>; }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; From 95ee314b387d1eb30cb75022f6098845ae59a5b0 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:31 +0200 Subject: [PATCH 25/44] ARM: dts: stm32: add vrefint support to adc2 on stm32mp15 Set STM32 ADC2 as a consumer of BSEC on STM32MP15, to retrieve vrefint calibration data saved in OTP. During the calibration process vrefp is set to 3.3V and the data acquired is saved to the OTP. This data is used by the ADC driver to calculated the actual value of vrefp according to the formula: vrefp = 3.3 x vrefint_cal / vrefint_data The vrefint channel provides the actual value of vrefp, which can be used to correct ADC acquisition data. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3d0c39d847b5f..61508917521c3 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1113,6 +1113,8 @@ interrupts = <1>; dmas = <&dmamux1 10 0x400 0x01>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@13 { reg = <13>; From 7ea81ea58d61aed271afb83fef5935232ee43cd4 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:32 +0200 Subject: [PATCH 26/44] ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards U-Boot enables ADC1&2 to support USB power measurement and ADC calibration on STM32MP15x Disco boards. When leaving U-boot the ADCs do not return to power down state to keep ADC linear calibration available for kernel. Enable ADC1&2 by default on STM32MP15xx-DKx boards to align kernel DT with Uboot. This avoids to shutdown the ADCs VDDA, while the ADCs are not in power down. Use STM32 ADC generic bindings instead of legacy bindings on STM32MP15xx-DKx boards. The ADC pins on Arduino connector are not set by default. These pins are added in A7 Disco example DTs only. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 29 ++++++++++++++++++-------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index a6e2e20f12fa0..e78ba956b9d0f 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -93,28 +93,39 @@ &adc { pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; + pinctrl-0 = <&adc12_usb_cc_pins_a>; vdd-supply = <&vdd>; vdda-supply = <&vdd>; vref-supply = <&vrefbuf>; - status = "disabled"; + status = "okay"; adc1: adc@0 { + status = "okay"; /* * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: * 5 * (56 + 47kOhms) * 5pF => 2.5us. * Use arbitrary margin here (e.g. 5us). */ - st,min-sample-time-nsecs = <5000>; - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 6 13 18 19>; - status = "okay"; + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 2 6 18 19>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + /* USB Type-C CC1 & CC2 */ + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; }; }; From 765ce359d67fc089281bc5317230c310122f7a32 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:33 +0200 Subject: [PATCH 27/44] ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1 Use STM32 ADC generic bindings instead of legacy bindings on STM32MP157c-ed1 board. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 8beb901be5065..66ed5f9921ba1 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -103,10 +103,20 @@ vref-supply = <&vdda>; status = "disabled"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-nsecs = <400>; status = "okay"; + channel@0 { + reg = <0>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-ns = <400>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <400>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <400>; + }; }; }; From c46e9b6cc98245f7264a8d15394d1f95d433abec Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:34 +0200 Subject: [PATCH 28/44] ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon Use STM32 ADC generic bindings instead of legacy bindings on emtrion GmbH Argon boards. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index b01470a9a3d53..94e38141af672 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -97,9 +97,11 @@ adc1: adc@0 { pinctrl-names = "default"; pinctrl-0 = <&adc1_in6_pins_a>; - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <6>; status = "disabled"; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { From 1866e1f96cda9237d21e3028f036eb62e1e36d6e Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:35 +0200 Subject: [PATCH 29/44] ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc Use STM32 ADC generic bindings instead of legacy bindings on DHCOR DRC Compact board. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- .../dts/stm32mp15xx-dhcor-drc-compact.dtsi | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi index 39af79dc654cc..92d906bfd5d7d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -57,15 +57,35 @@ status = "okay"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; }; }; From 84cb6d8a0aafabe484203fc5fd63984a5aea8747 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:36 +0200 Subject: [PATCH 30/44] ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench Use STM32 ADC generic bindings instead of legacy bindings on DHCOR Testbench board. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- .../boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi index faed31b6d84a1..ab7f0ba496396 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -41,15 +41,35 @@ status = "okay"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; }; }; From 9bcfc3cdc903485a52c6f471f4ae96a41fa51803 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 30 May 2023 14:45:37 +0200 Subject: [PATCH 31/44] ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems The generic ADC channel binding is recommended over legacy one, update the DT to the modern binding. No functional change. For further details, see commit which adds the generic binding to STM32 ADC binding document: '664b9879f56e ("dt-bindings: iio: stm32-adc: add generic channel binding")' Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 18 +++++---- .../boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 38 +++++++++++++++---- 2 files changed, 40 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index c06edd2eacb0c..e61df23d361a7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -80,17 +80,19 @@ vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; +}; - adc1: adc@0 { - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <0>; - status = "okay"; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; }; +}; - adc2: adc@100 { - st,adc-channels = <1>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; +&adc2 { + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index cdd4902b59a97..0069ad75d55e5 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -111,17 +111,39 @@ vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; +}; - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; }; - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; +}; + +&adc2 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; }; }; From 9da2bf3bcd8bbc0b700b44886a8e2a0036216748 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 1 Jun 2023 08:52:21 +0200 Subject: [PATCH 32/44] ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1 Correct the following warnings by adding the required supplies (AVDD, DVDD) for the ov5640 node. arch/arm/boot/dts/stm32mp157c-ev1.dtb: camera@3c: 'AVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/stm32mp157c-ev1.dtb: camera@3c: 'DVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 49ca94c19b02b..af3800501875c 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -190,7 +190,9 @@ reg = <0x3c>; clocks = <&clk_ext_camera>; clock-names = "xclk"; + AVDD-supply = <&v2v8>; DOVDD-supply = <&v2v8>; + DVDD-supply = <&v2v8>; powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; rotation = <180>; From e3f2778b1b6ced649bffdc7cbb05b80bb92f2108 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jun 2023 20:01:12 +0200 Subject: [PATCH 33/44] ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2 The audio routing flow is not correct, the flow should be from source (second element in the pair) to sink (first element in the pair). The flow now is from "HP_OUT" to "Playback", where "Playback" is source and "HP_OUT" is sink, i.e. the direction is swapped and there is no direct link between the two either. Fill in the correct routing, where "HP_OUT" supplies the "Headphone Jack", "Line In Jack" supplies "LINE_IN" input, "Microphone Jack" supplies "MIC_IN" input and "Mic Bias" supplies "Microphone Jack". Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 4709677151aac..46b87a27d8b37 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -137,10 +137,13 @@ sound { compatible = "audio-graph-card"; - routing = - "MIC_IN", "Capture", - "Capture", "Mic Bias", - "Playback", "HP_OUT"; + widgets = "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Microphone", "Microphone Jack"; + routing = "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; dais = <&sai2a_port &sai2b_port>; status = "okay"; }; From 076c74c592cabe4a47537fe5205b5b678bed010d Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 6 Jun 2023 13:56:04 +0200 Subject: [PATCH 34/44] ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx Use "dai-format" to configure DAI audio format as specified in audio-graph-port.yaml bindings. Fixes: 144d1ba70548 ("ARM: dts: stm32: Adapt STM32MP157 DK boards to stm32 DT diversity") Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index e78ba956b9d0f..511113f2e3992 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -446,7 +446,7 @@ i2s2_port: port { i2s2_endpoint: endpoint { remote-endpoint = <&sii9022_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; }; }; From a45645472f7762df7c5ee4fabde3a86581012ae4 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 6 Apr 2022 15:39:28 +0200 Subject: [PATCH 35/44] dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages Add support for st,stm32mp257-pinctrl and st,stm32mp257-z-pinctrl. Add packages AI, AK and AL (values : 0x100, 0x400 and 0x800) Signed-off-by: Alexandre Torgue Reviewed-by: Conor Dooley Reviewed-by: Linus Walleij --- .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 4 +++- include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 1ab0f8dde4770..2120ef71a78d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -27,6 +27,8 @@ properties: - st,stm32mp135-pinctrl - st,stm32mp157-pinctrl - st,stm32mp157-z-pinctrl + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl '#address-cells': const: 1 @@ -56,7 +58,7 @@ properties: Indicates the SOC package used. More details in include/dt-bindings/pinctrl/stm32-pinfunc.h $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800] patternProperties: '^gpio@[0-9a-f]*$': diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4d3..28ad0235086a6 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -37,6 +37,9 @@ #define STM32MP_PKG_AB 0x2 #define STM32MP_PKG_AC 0x4 #define STM32MP_PKG_AD 0x8 +#define STM32MP_PKG_AI 0x100 +#define STM32MP_PKG_AK 0x400 +#define STM32MP_PKG_AL 0x800 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ From 619f8ca4a73d376bee4307948aea6cd6177aa1df Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 24 May 2023 15:33:57 +0200 Subject: [PATCH 36/44] pinctrl: stm32: add stm32mp257 pinctrl support Add stm32mp257 pinctrl support. Signed-off-by: Alexandre Torgue Reviewed-by: Linus Walleij --- drivers/pinctrl/stm32/Kconfig | 6 + drivers/pinctrl/stm32/Makefile | 1 + drivers/pinctrl/stm32/pinctrl-stm32.h | 3 + drivers/pinctrl/stm32/pinctrl-stm32mp257.c | 2581 ++++++++++++++++++++ 4 files changed, 2591 insertions(+) create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32mp257.c diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig index d532f3c6f670d..2656d3d3ae402 100644 --- a/drivers/pinctrl/stm32/Kconfig +++ b/drivers/pinctrl/stm32/Kconfig @@ -51,4 +51,10 @@ config PINCTRL_STM32MP157 depends on OF && HAS_IOMEM default MACH_STM32MP157 select PINCTRL_STM32 + +config PINCTRL_STM32MP257 + bool "STMicroelectronics STM32MP257 pin control" if COMPILE_TEST && !MACH_STM32MP25 + depends on OF && HAS_IOMEM + default MACH_STM32MP25 + select PINCTRL_STM32 endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 619629ee9944d..7b17464d8de1d 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STM32F769) += pinctrl-stm32f769.o obj-$(CONFIG_PINCTRL_STM32H743) += pinctrl-stm32h743.o obj-$(CONFIG_PINCTRL_STM32MP135) += pinctrl-stm32mp135.o obj-$(CONFIG_PINCTRL_STM32MP157) += pinctrl-stm32mp157.o +obj-$(CONFIG_PINCTRL_STM32MP257) += pinctrl-stm32mp257.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index e0c31c4c8bca8..5e5de92ddd58c 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -24,6 +24,9 @@ #define STM32MP_PKG_AB BIT(1) #define STM32MP_PKG_AC BIT(2) #define STM32MP_PKG_AD BIT(3) +#define STM32MP_PKG_AI BIT(8) +#define STM32MP_PKG_AK BIT(10) +#define STM32MP_PKG_AL BIT(11) struct stm32_desc_function { const char *name; diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp257.c b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c new file mode 100644 index 0000000000000..73f091cd827e6 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32mp257.c @@ -0,0 +1,2581 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32mp257_pins[] = { + STM32_PIN_PKG( + PINCTRL_PIN(0, "PA0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "UART8_CTS"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "UART5_TX"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(8, "TIM3_ETR"), + STM32_FUNCTION(9, "TIM5_CH2"), + STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(1, "PA1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(3, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_SD_A"), + STM32_FUNCTION(6, "USART1_RTS"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(8, "TIM4_CH2"), + STM32_FUNCTION(9, "I2C4_SDA"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(12, "LCD_R3"), + STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(15, "ETH3_PHY_INTN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(2, "PA2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "LPTIM2_IN1"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "I3C1_SDA"), + STM32_FUNCTION(11, "I2C1_SDA"), + STM32_FUNCTION(12, "LCD_B0"), + STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(15, "ETH3_RGMII_RX_CTL ETH3_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(3, "PA3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "I3C1_SCL"), + STM32_FUNCTION(10, "I2C7_SMBA"), + STM32_FUNCTION(11, "I2C1_SCL"), + STM32_FUNCTION(12, "LCD_B1"), + STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(15, "ETH3_RGMII_TX_CTL ETH3_RMII_TX_EN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(4, "PA4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(7, "USART2_TX"), + STM32_FUNCTION(8, "FDCAN2_TX"), + STM32_FUNCTION(9, "TIM2_CH1"), + STM32_FUNCTION(11, "LCD_R1"), + STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"), + STM32_FUNCTION(15, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(5, "PA5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(4, "SPI4_MOSI"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "SAI2_SD_B"), + STM32_FUNCTION(7, "USART2_RTS"), + STM32_FUNCTION(8, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM2_CH4"), + STM32_FUNCTION(11, "LCD_G0"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(15, "ETH3_RGMII_RX_CLK ETH3_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(6, "PA6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(4, "SPI4_SCK"), + STM32_FUNCTION(5, "SAI2_FS_B"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(9, "TIM2_ETR"), + STM32_FUNCTION(11, "LCD_G4"), + STM32_FUNCTION(13, "FMC_NE1"), + STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD0 ETH3_RMII_TXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(7, "PA7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(3, "AUDIOCLK"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "TIM4_ETR"), + STM32_FUNCTION(9, "I2C2_SMBA"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(11, "LCD_B5"), + STM32_FUNCTION(12, "I2C3_SMBA"), + STM32_FUNCTION(13, "I2C4_SMBA"), + STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD1 ETH3_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(8, "PA8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(2, "LPTIM2_CH2"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "USART2_RX"), + STM32_FUNCTION(10, "I2C5_SCL"), + STM32_FUNCTION(13, "LCD_B2"), + STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(9, "PA9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(4, "SPI4_NSS"), + STM32_FUNCTION(5, "SAI2_SCK_B"), + STM32_FUNCTION(7, "USART2_CTS"), + STM32_FUNCTION(8, "LPTIM5_ETR"), + STM32_FUNCTION(9, "TIM2_CH3"), + STM32_FUNCTION(11, "ETH1_MDC"), + STM32_FUNCTION(13, "LCD_G7"), + STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD0 ETH3_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(10, "PA10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(4, "SPI4_MISO"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(7, "USART2_RX"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(9, "TIM2_CH2"), + STM32_FUNCTION(11, "ETH1_MDIO"), + STM32_FUNCTION(13, "LCD_R6"), + STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD1 ETH3_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(11, "PA11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "SPI8_SCK"), + STM32_FUNCTION(3, "LPTIM2_CH1"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(6, "MDF1_SDI4"), + STM32_FUNCTION(11, "ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(12, "PA12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(3, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_FS_A"), + STM32_FUNCTION(8, "TIM4_CH1"), + STM32_FUNCTION(9, "I2C4_SCL"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(11, "ETH1_PHY_INTN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(13, "PA13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(2, "SPI8_RDY"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "LPTIM2_ETR"), + STM32_FUNCTION(6, "MDF1_CKI3"), + STM32_FUNCTION(7, "USART2_CTS"), + STM32_FUNCTION(10, "I2C7_SMBA"), + STM32_FUNCTION(11, "ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(14, "PA14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(2, "SPI8_NSS"), + STM32_FUNCTION(3, "LPTIM2_CH2"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(6, "MDF1_CCK1"), + STM32_FUNCTION(11, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(15, "PA15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "USART2_RX"), + STM32_FUNCTION(10, "I2C7_SDA"), + STM32_FUNCTION(11, "ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(16, "PB0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(8, "TIM16_CH1"), + STM32_FUNCTION(9, "TIM20_CH4N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(17, "PB1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "TIM16_CH1N"), + STM32_FUNCTION(9, "TIM20_CH3N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO1"), + STM32_FUNCTION(13, "FMC_NCE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(18, "PB2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(6, "MDF1_CKI3"), + STM32_FUNCTION(7, "TIM17_BKIN"), + STM32_FUNCTION(8, "TIM16_BKIN"), + STM32_FUNCTION(9, "TIM20_CH2N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(19, "PB3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI3"), + STM32_FUNCTION(9, "TIM20_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO3"), + STM32_FUNCTION(13, "FMC_NCE3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(20, "PB4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(4, "UART4_CTS"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(6, "MDF1_SDI4"), + STM32_FUNCTION(7, "TIM14_CH1"), + STM32_FUNCTION(9, "TIM20_CH2"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO4"), + STM32_FUNCTION(14, "I3C2_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(21, "PB5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(4, "UART4_RTS"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(6, "MDF1_CKI4"), + STM32_FUNCTION(9, "TIM20_CH1"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO5"), + STM32_FUNCTION(13, "FMC_AD8 FMC_D8"), + STM32_FUNCTION(14, "I3C2_SCL"), + STM32_FUNCTION(15, "SDMMC3_D123DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(22, "PB6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "UART4_RX"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(9, "TIM20_CH1N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO6"), + STM32_FUNCTION(13, "FMC_AD9 FMC_D9"), + STM32_FUNCTION(15, "SDMMC3_D0DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(23, "PB7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(2, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(4, "UART4_TX"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(9, "TIM20_ETR"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P2_IO7"), + STM32_FUNCTION(13, "FMC_AD10 FMC_D10"), + STM32_FUNCTION(15, "SDMMC3_CDIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(24, "PB8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(2, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(8, "TIM17_CH1"), + STM32_FUNCTION(9, "TIM20_CH4"), + STM32_FUNCTION(11, "OCTOSPIM_P2_NCS1"), + STM32_FUNCTION(13, "FMC_AD12 FMC_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(25, "PB9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(2, "SPI3_RDY"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM20_BKIN"), + STM32_FUNCTION(10, "TIM10_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P2_DQS"), + STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(13, "FMC_AD13 FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(26, "PB10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(8, "TIM17_CH1N"), + STM32_FUNCTION(11, "OCTOSPIM_P2_CLK"), + STM32_FUNCTION(13, "FMC_AD15 FMC_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(27, "PB11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "I2S3_MCK"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM20_BKIN2"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(11, "OCTOSPIM_P2_NCLK"), + STM32_FUNCTION(12, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(13, "FMC_AD14 FMC_D14"), + STM32_FUNCTION(14, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(28, "PB12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(6, "UART8_CTS"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(10, "DSI_TE"), + STM32_FUNCTION(11, "SDMMC3_D2"), + STM32_FUNCTION(12, "FMC_NWAIT"), + STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(29, "PB13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(6, "UART8_RX"), + STM32_FUNCTION(11, "SDMMC3_CK"), + STM32_FUNCTION(12, "FMC_AD5 FMC_D5"), + STM32_FUNCTION(13, "FMC_AD0 FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(30, "PB14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(10, "TIM4_CH2"), + STM32_FUNCTION(11, "SDMMC3_D0"), + STM32_FUNCTION(12, "FMC_AD7 FMC_D7"), + STM32_FUNCTION(13, "FMC_AD2 FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(31, "PB15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(4, "UART8_RTS"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(6, "UART5_RX"), + STM32_FUNCTION(8, "TIM3_CH2"), + STM32_FUNCTION(9, "TIM5_CH1"), + STM32_FUNCTION(11, "ETH1_PPS_OUT"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(32, "PC0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(4, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_MCLK_B"), + STM32_FUNCTION(6, "USART6_TX"), + STM32_FUNCTION(10, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(12, "ETH1_MII_TX_CLK"), + STM32_FUNCTION(13, "ETH1_RGMII_GTX_CLK"), + STM32_FUNCTION(14, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(33, "PC1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(7, "USART2_TX"), + STM32_FUNCTION(10, "I2C7_SCL"), + STM32_FUNCTION(11, "ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(34, "PC2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(2, "SPI8_MOSI"), + STM32_FUNCTION(3, "LPTIM2_IN1"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(6, "MDF1_SDI3"), + STM32_FUNCTION(7, "USART2_RTS"), + STM32_FUNCTION(11, "ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(35, "PC3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(2, "LPTIM1_IN2"), + STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(7, "USART6_RTS"), + STM32_FUNCTION(8, "FDCAN2_TX"), + STM32_FUNCTION(11, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(14, "LCD_G6"), + STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(36, "PC4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_FS_B"), + STM32_FUNCTION(11, "ETH2_MII_TX_EN ETH2_RGMII_TX_CTL ETH2_RMII_TX_EN"), + STM32_FUNCTION(13, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(37, "PC5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(3, "SPDIFRX1_IN1"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(10, "I2C4_SDA"), + STM32_FUNCTION(11, "ETH2_MDIO"), + STM32_FUNCTION(12, "ETH1_MII_COL"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(14, "ETH1_PPS_OUT"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(38, "PC6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(3, "SPDIFRX1_IN0"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(10, "I2C4_SCL"), + STM32_FUNCTION(11, "ETH2_MDC"), + STM32_FUNCTION(12, "ETH1_MII_CRS"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(14, "ETH1_PHY_INTN"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(39, "PC7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_SD_B"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(11, "ETH2_MII_TXD0 ETH2_RGMII_TXD0 ETH2_RMII_TXD0"), + STM32_FUNCTION(12, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(14, "LCD_B4"), + STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(40, "PC8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(4, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_SCK_B"), + STM32_FUNCTION(7, "USART6_CTS"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(11, "ETH2_MII_TXD1 ETH2_RGMII_TXD1 ETH2_RMII_TXD1"), + STM32_FUNCTION(12, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(41, "PC9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(8, "TIM13_CH1"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(10, "USBH_HS_OVRCUR"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(12, "USB3DR_OVRCUR"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "LCD_G2"), + STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(42, "PC10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(3, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(10, "USBH_HS_VBUSEN"), + STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(12, "USB3DR_VBUSEN"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(43, "PC11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(2, "LPTIM1_CH1"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(5, "SAI2_MCLK_A"), + STM32_FUNCTION(6, "UART5_RTS"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "TIM3_CH1"), + STM32_FUNCTION(9, "TIM5_ETR"), + STM32_FUNCTION(11, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "LCD_R2"), + STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(44, "PC12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(2, "LPTIM1_CH2"), + STM32_FUNCTION(4, "I3C3_SCL"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "ETH2_MII_RXD1 ETH2_RGMII_RXD1 ETH2_RMII_RXD1"), + STM32_FUNCTION(12, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(14, "LCD_G1"), + STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(45, "PC13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(48, "PD0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(4, "SAI1_D2"), + STM32_FUNCTION(6, "SAI4_FS_A"), + STM32_FUNCTION(7, "UART7_RX"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_CLK"), + STM32_FUNCTION(14, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(49, "PD1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SAI1_CK2"), + STM32_FUNCTION(6, "SAI4_SD_A"), + STM32_FUNCTION(7, "UART7_RTS"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(10, "FDCAN3_RX"), + STM32_FUNCTION(11, "OCTOSPIM_P1_NCLK"), + STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(13, "OCTOSPIM_P2_NCS2"), + STM32_FUNCTION(14, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(50, "PD2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(4, "SAI1_CK1"), + STM32_FUNCTION(6, "SAI4_SCK_A"), + STM32_FUNCTION(7, "UART7_CTS"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(10, "FDCAN3_TX"), + STM32_FUNCTION(11, "OCTOSPIM_P1_DQS"), + STM32_FUNCTION(12, "OCTOSPIM_P1_NCS2"), + STM32_FUNCTION(14, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(51, "PD3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(2, "SAI1_MCLK_A"), + STM32_FUNCTION(3, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(4, "SAI1_D1"), + STM32_FUNCTION(6, "SAI4_MCLK_A"), + STM32_FUNCTION(7, "UART7_TX"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "OCTOSPIM_P1_NCS1"), + STM32_FUNCTION(14, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(52, "PD4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "SPI4_MISO"), + STM32_FUNCTION(3, "HDP3"), + STM32_FUNCTION(4, "SAI1_D3"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(10, "TIM4_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO0"), + STM32_FUNCTION(14, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(53, "PD5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "SPI4_NSS"), + STM32_FUNCTION(3, "HDP4"), + STM32_FUNCTION(4, "SAI1_D4"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(10, "TIM4_CH2"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO1"), + STM32_FUNCTION(14, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(54, "PD6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "SPI4_MOSI"), + STM32_FUNCTION(3, "HDP5"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(10, "TIM4_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO2"), + STM32_FUNCTION(14, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(55, "PD7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "SPI4_SCK"), + STM32_FUNCTION(3, "SPI1_RDY"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(10, "TIM4_CH4"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO3"), + STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(56, "PD8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "SPI4_RDY"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(4, "SAI1_FS_A"), + STM32_FUNCTION(5, "UART4_CTS"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(10, "TIM4_ETR"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO4"), + STM32_FUNCTION(12, "SDMMC1_D7"), + STM32_FUNCTION(13, "SDMMC1_D123DIR"), + STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(57, "PD9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(4, "SAI1_SD_A"), + STM32_FUNCTION(5, "UART4_RTS"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO5"), + STM32_FUNCTION(12, "SDMMC1_D6"), + STM32_FUNCTION(13, "SDMMC1_D0DIR"), + STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(58, "PD10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(4, "SAI1_SCK_A"), + STM32_FUNCTION(5, "UART4_RX"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "I2C4_SDA"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO6"), + STM32_FUNCTION(12, "SDMMC1_D5"), + STM32_FUNCTION(13, "SDMMC1_CDIR"), + STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(59, "PD11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SAI1_MCLK_A"), + STM32_FUNCTION(5, "UART4_TX"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(7, "I2C4_SCL"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "OCTOSPIM_P1_IO7"), + STM32_FUNCTION(12, "SDMMC1_D4"), + STM32_FUNCTION(13, "SDMMC1_CKIN"), + STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(60, "PD12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(2, "SPI7_MISO"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN2"), + STM32_FUNCTION(6, "UART8_RTS"), + STM32_FUNCTION(10, "TIM4_ETR"), + STM32_FUNCTION(11, "SDMMC3_CMD"), + STM32_FUNCTION(12, "FMC_AD6 FMC_D6"), + STM32_FUNCTION(13, "FMC_AD1 FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(61, "PD13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(10, "TIM4_CH4"), + STM32_FUNCTION(11, "SDMMC3_D1"), + STM32_FUNCTION(12, "FMC_AD11 FMC_D11"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(62, "PD14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "I2C7_SDA"), + STM32_FUNCTION(12, "FMC_AD4 FMC_D4"), + STM32_FUNCTION(13, "SDMMC3_D3"), + STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(63, "PD15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(2, "SPI1_RDY"), + STM32_FUNCTION(6, "DSI_TE"), + STM32_FUNCTION(7, "I2C5_SDA"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "TIM5_ETR"), + STM32_FUNCTION(11, "I2C7_SCL"), + STM32_FUNCTION(12, "FMC_AD3 FMC_D3"), + STM32_FUNCTION(13, "SDMMC3_CKIN"), + STM32_FUNCTION(14, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(64, "PE0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "LPTIM2_CH1"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPI3_RDY"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(11, "SDMMC1_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(65, "PE1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "LPTIM2_CH2"), + STM32_FUNCTION(3, "I2S1_MCK"), + STM32_FUNCTION(4, "I2S3_MCK"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(11, "SDMMC1_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(66, "PE2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(2, "LPTIM2_ETR"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SPI3_MOSI I2S3_SDO"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(11, "SDMMC1_CMD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(67, "PE3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SPI1_RDY"), + STM32_FUNCTION(4, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "SDMMC1_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(68, "PE4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "LPTIM2_IN1"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(4, "SPI3_MISO I2S3_SDI"), + STM32_FUNCTION(5, "SAI1_SD_B"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(11, "SDMMC1_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(69, "PE5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "LPTIM2_IN2"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(4, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(5, "SAI1_FS_B"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(11, "SDMMC1_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(70, "PE6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(2, "SPI4_RDY"), + STM32_FUNCTION(5, "SPDIFRX1_IN2"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(12, "FMC_AD1 FMC_D1"), + STM32_FUNCTION(13, "SDMMC2_D6"), + STM32_FUNCTION(14, "SDMMC2_D0DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(71, "PE7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(4, "SAI4_D4"), + STM32_FUNCTION(5, "SPDIFRX1_IN3"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(11, "TIM14_CH1"), + STM32_FUNCTION(12, "FMC_AD2 FMC_D2"), + STM32_FUNCTION(13, "SDMMC2_D7"), + STM32_FUNCTION(14, "SDMMC2_D123DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(72, "PE8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "SPI4_MOSI"), + STM32_FUNCTION(4, "SAI4_CK1"), + STM32_FUNCTION(5, "SAI4_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(12, "FMC_A17 FMC_ALE"), + STM32_FUNCTION(13, "SDMMC2_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(73, "PE9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "SPI4_MISO"), + STM32_FUNCTION(4, "SAI4_D2"), + STM32_FUNCTION(5, "SAI4_FS_A"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(12, "FMC_AD0 FMC_D0"), + STM32_FUNCTION(13, "SDMMC2_D5"), + STM32_FUNCTION(14, "SDMMC2_CDIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(74, "PE10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "SPI4_SCK"), + STM32_FUNCTION(4, "SAI4_D1"), + STM32_FUNCTION(5, "SAI4_SD_A"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(11, "FMC_NE3"), + STM32_FUNCTION(12, "FMC_NCE2"), + STM32_FUNCTION(13, "SDMMC2_D4"), + STM32_FUNCTION(14, "SDMMC2_CKIN"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(75, "PE11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(4, "SAI4_D3"), + STM32_FUNCTION(5, "SAI1_FS_A"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(12, "FMC_A16 FMC_CLE"), + STM32_FUNCTION(13, "SDMMC2_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(76, "PE12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "SPI4_NSS"), + STM32_FUNCTION(4, "SAI4_CK2"), + STM32_FUNCTION(5, "SAI4_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(11, "FMC_NE2"), + STM32_FUNCTION(12, "FMC_NCE1"), + STM32_FUNCTION(13, "SDMMC2_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(77, "PE13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(5, "SAI1_SD_A"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(12, "FMC_RNB"), + STM32_FUNCTION(13, "SDMMC2_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(78, "PE14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI1_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(12, "FMC_NWE"), + STM32_FUNCTION(13, "SDMMC2_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(79, "PE15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(5, "SAI1_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(12, "FMC_NOE"), + STM32_FUNCTION(13, "SDMMC2_CMD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(80, "PF0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM12_CH2"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "ETH1_MDC"), + STM32_FUNCTION(12, "ETH2_MII_CRS"), + STM32_FUNCTION(14, "I3C2_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(81, "PF1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(2, "SPI8_MISO"), + STM32_FUNCTION(3, "LPTIM2_IN2"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(6, "MDF1_CKI4"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(11, "ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(82, "PF2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(3, "SPI3_RDY"), + STM32_FUNCTION(7, "I2C4_SMBA"), + STM32_FUNCTION(9, "TIM12_CH1"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "ETH1_MDIO"), + STM32_FUNCTION(12, "ETH2_MII_COL"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(14, "I3C2_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(83, "PF3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(4, "UART8_RX"), + STM32_FUNCTION(5, "SAI2_SCK_B"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(8, "TIM3_CH4"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(84, "PF4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(3, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_SCK_A"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(8, "TIM4_CH4"), + STM32_FUNCTION(9, "ETH1_MDC"), + STM32_FUNCTION(10, "ETH2_CLK"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(12, "ETH1_PPS_OUT"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(85, "PF5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(3, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_MCLK_A"), + STM32_FUNCTION(7, "USART6_TX"), + STM32_FUNCTION(8, "TIM4_CH3"), + STM32_FUNCTION(9, "ETH1_MDIO"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(12, "ETH1_PHY_INTN"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(86, "PF6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(2, "RTC_OUT2"), + STM32_FUNCTION(4, "SAI3_MCLK_B"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(8, "TIM12_CH1"), + STM32_FUNCTION(10, "I2C3_SMBA"), + STM32_FUNCTION(11, "ETH2_MII_RX_CLK ETH2_RGMII_RX_CLK ETH2_RMII_REF_CLK"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(87, "PF7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(3, "SPDIFRX1_IN1"), + STM32_FUNCTION(4, "SPI6_SCK"), + STM32_FUNCTION(5, "SAI3_SD_A"), + STM32_FUNCTION(8, "TIM2_ETR"), + STM32_FUNCTION(11, "ETH2_RGMII_GTX_CLK"), + STM32_FUNCTION(12, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(14, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(88, "PF8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(4, "SAI3_SCK_B"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(8, "TIM12_CH2"), + STM32_FUNCTION(10, "ETH1_CLK"), + STM32_FUNCTION(11, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH2_MII_RX_ER"), + STM32_FUNCTION(13, "ETH2_MII_RX_DV ETH2_RGMII_RX_CTL ETH2_RMII_CRS_DV"), + STM32_FUNCTION(14, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(89, "PF9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(4, "SAI3_SD_B"), + STM32_FUNCTION(5, "SAI2_SD_A"), + STM32_FUNCTION(6, "MDF1_SDI5"), + STM32_FUNCTION(7, "UART8_RTS"), + STM32_FUNCTION(8, "TIM2_CH2"), + STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"), + STM32_FUNCTION(12, "ETH2_MDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(90, "PF10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(3, "SPI3_RDY"), + STM32_FUNCTION(5, "SAI2_MCLK_A"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(7, "UART8_TX"), + STM32_FUNCTION(8, "TIM2_CH3"), + STM32_FUNCTION(11, "ETH2_MII_TXD2 ETH2_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(91, "PF11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "SPDIFRX1_IN0"), + STM32_FUNCTION(4, "SPI6_RDY"), + STM32_FUNCTION(5, "SAI2_SCK_A"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(7, "UART8_RX"), + STM32_FUNCTION(8, "TIM2_CH4"), + STM32_FUNCTION(11, "ETH2_MII_TXD3 ETH2_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(92, "PF12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(9, "TIM5_CH1"), + STM32_FUNCTION(14, "LCD_CLK"), + STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(93, "PF13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(3, "AUDIOCLK"), + STM32_FUNCTION(4, "USART6_TX"), + STM32_FUNCTION(5, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_CKI7"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(8, "FDCAN3_TX"), + STM32_FUNCTION(9, "TIM3_CH3"), + STM32_FUNCTION(14, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(94, "PF14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(4, "USART6_RX"), + STM32_FUNCTION(6, "MDF1_SDI7"), + STM32_FUNCTION(7, "USART3_RTS"), + STM32_FUNCTION(8, "FDCAN3_RX"), + STM32_FUNCTION(9, "TIM3_CH4"), + STM32_FUNCTION(14, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(95, "PF15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(4, "USART6_CTS"), + STM32_FUNCTION(5, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(8, "TIM2_CH2"), + STM32_FUNCTION(9, "TIM3_ETR"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(14, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(96, "PG0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(4, "I3C3_SDA"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(11, "ETH2_MII_RXD0 ETH2_RGMII_RXD0 ETH2_RMII_RXD0"), + STM32_FUNCTION(12, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(14, "LCD_G5"), + STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(97, "PG1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(2, "LPTIM1_IN1"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "I3C3_SCL"), + STM32_FUNCTION(5, "SAI2_SD_A"), + STM32_FUNCTION(6, "UART5_CTS"), + STM32_FUNCTION(7, "USART3_CTS"), + STM32_FUNCTION(9, "TIM5_CH4"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "ETH2_MII_RX_ER"), + STM32_FUNCTION(12, "ETH2_MII_RXD3 ETH2_RGMII_RXD3"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "LCD_VSYNC"), + STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(98, "PG2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(2, "RTC_REFIN"), + STM32_FUNCTION(3, "I2S3_MCK"), + STM32_FUNCTION(4, "I3C3_SDA"), + STM32_FUNCTION(5, "SAI2_FS_A"), + STM32_FUNCTION(7, "USART3_CK"), + STM32_FUNCTION(9, "TIM5_CH3"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(11, "ETH2_MII_TX_CLK"), + STM32_FUNCTION(12, "ETH2_RGMII_CLK125"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(99, "PG3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(2, "LPTIM1_ETR"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(4, "UART8_TX"), + STM32_FUNCTION(5, "SAI2_FS_B"), + STM32_FUNCTION(8, "TIM3_CH3"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(10, "ETH2_CLK"), + STM32_FUNCTION(11, "ETH2_PHY_INTN"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(100, "PG4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SAI3_FS_B"), + STM32_FUNCTION(8, "LPTIM4_IN1"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(11, "ETH2_PPS_OUT"), + STM32_FUNCTION(12, "ETH2_MDC"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(101, "PG5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(2, "HDP3"), + STM32_FUNCTION(4, "USART6_RTS"), + STM32_FUNCTION(8, "TIM2_CH3"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(14, "LCD_R5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(102, "PG6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(1, "TRACED4"), + STM32_FUNCTION(2, "HDP4"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(4, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(8, "TIM2_CH4"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(14, "LCD_R6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(103, "PG7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(1, "TRACED5"), + STM32_FUNCTION(2, "HDP5"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(4, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM5_ETR"), + STM32_FUNCTION(14, "LCD_R7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(104, "PG8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(1, "TRACED6"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "SPI1_RDY"), + STM32_FUNCTION(5, "USART6_CK"), + STM32_FUNCTION(6, "UART5_RTS"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(9, "TIM5_CH3"), + STM32_FUNCTION(14, "LCD_G2"), + STM32_FUNCTION(15, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(105, "PG9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(6, "UART5_TX"), + STM32_FUNCTION(9, "TIM5_CH4"), + STM32_FUNCTION(14, "LCD_G3"), + STM32_FUNCTION(15, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(106, "PG10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(1, "TRACED8"), + STM32_FUNCTION(2, "HDP0"), + STM32_FUNCTION(6, "UART5_RX"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(14, "LCD_G4"), + STM32_FUNCTION(15, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(107, "PG11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(1, "TRACED9"), + STM32_FUNCTION(2, "HDP1"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(14, "LCD_G5"), + STM32_FUNCTION(15, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(108, "PG12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(1, "TRACED10"), + STM32_FUNCTION(2, "HDP2"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(14, "LCD_G6"), + STM32_FUNCTION(15, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(109, "PG13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(1, "TRACED11"), + STM32_FUNCTION(2, "HDP3"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(6, "MDF1_CKI6"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(10, "I2C1_SCL"), + STM32_FUNCTION(11, "I3C1_SCL"), + STM32_FUNCTION(14, "LCD_G7"), + STM32_FUNCTION(15, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(110, "PG14"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(1, "TRACED12"), + STM32_FUNCTION(2, "HDP4"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(6, "MDF1_CKI5"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(14, "LCD_B1"), + STM32_FUNCTION(15, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(111, "PG15"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(1, "TRACED13"), + STM32_FUNCTION(2, "HDP5"), + STM32_FUNCTION(4, "LPTIM1_CH2"), + STM32_FUNCTION(6, "MDF1_SDI5"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(14, "LCD_B2"), + STM32_FUNCTION(15, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(114, "PH2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(2, "LPTIM2_CH1"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(4, "SPDIFRX1_IN3"), + STM32_FUNCTION(5, "SAI1_SCK_B"), + STM32_FUNCTION(6, "I3C3_SDA"), + STM32_FUNCTION(8, "TIM16_CH1"), + STM32_FUNCTION(9, "I2C5_SDA"), + STM32_FUNCTION(10, "I2C3_SDA"), + STM32_FUNCTION(15, "ETH3_RGMII_GTX_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(115, "PH3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(3, "SPI1_NSS I2S1_WS"), + STM32_FUNCTION(7, "UART7_RX"), + STM32_FUNCTION(8, "TIM17_CH1N"), + STM32_FUNCTION(10, "TIM5_CH3"), + STM32_FUNCTION(11, "I2C7_SCL"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(116, "PH4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(7, "UART7_TX"), + STM32_FUNCTION(8, "TIM17_BKIN"), + STM32_FUNCTION(10, "TIM5_CH2"), + STM32_FUNCTION(11, "LCD_R0"), + STM32_FUNCTION(12, "USB3DR_OVRCUR"), + STM32_FUNCTION(13, "USBH_HS_OVRCUR"), + STM32_FUNCTION(14, "ETH1_PTP_AUX_TS"), + STM32_FUNCTION(15, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(117, "PH5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "SAI2_FS_A"), + STM32_FUNCTION(7, "UART8_CTS"), + STM32_FUNCTION(8, "TIM2_CH1"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(11, "LCD_G1"), + STM32_FUNCTION(12, "USB3DR_VBUSEN"), + STM32_FUNCTION(13, "USBH_HS_VBUSEN"), + STM32_FUNCTION(14, "ETH2_PTP_AUX_TS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(118, "PH6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(2, "LPTIM2_IN2"), + STM32_FUNCTION(5, "SAI1_MCLK_B"), + STM32_FUNCTION(6, "I3C3_SCL"), + STM32_FUNCTION(8, "TIM16_CH1N"), + STM32_FUNCTION(9, "I2C5_SCL"), + STM32_FUNCTION(10, "I2C3_SCL"), + STM32_FUNCTION(11, "I2C1_SMBA"), + STM32_FUNCTION(15, "ETH3_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(119, "PH7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(3, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(5, "UART4_TX"), + STM32_FUNCTION(7, "UART7_RTS"), + STM32_FUNCTION(8, "TIM17_CH1"), + STM32_FUNCTION(10, "TIM5_CH4"), + STM32_FUNCTION(11, "I2C7_SDA"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(120, "PH8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(3, "SPI1_MISO I2S1_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN3"), + STM32_FUNCTION(5, "UART4_RX"), + STM32_FUNCTION(7, "UART7_CTS"), + STM32_FUNCTION(10, "TIM5_CH1"), + STM32_FUNCTION(11, "I2C3_SMBA"), + STM32_FUNCTION(12, "I2C5_SMBA"), + STM32_FUNCTION(15, "ETH3_RGMII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(121, "PH9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(4, "SPI6_NSS"), + STM32_FUNCTION(5, "SAI3_MCLK_A"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(8, "TIM15_CH1N"), + STM32_FUNCTION(11, "ETH1_RGMII_CLK125"), + STM32_FUNCTION(12, "ETH1_MII_RX_ER"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(122, "PH10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(5, "SAI3_SCK_A"), + STM32_FUNCTION(8, "TIM15_CH1"), + STM32_FUNCTION(10, "ETH2_MDC"), + STM32_FUNCTION(11, "ETH1_MII_TXD2 ETH1_RGMII_TXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(123, "PH11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(5, "SAI3_FS_A"), + STM32_FUNCTION(8, "TIM15_CH2"), + STM32_FUNCTION(10, "ETH2_MDIO"), + STM32_FUNCTION(11, "ETH1_MII_TXD3 ETH1_RGMII_TXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(124, "PH12"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(4, "SPI6_MISO"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(11, "ETH1_MII_RXD2 ETH1_RGMII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(125, "PH13"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(3, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(4, "SPI6_MOSI"), + STM32_FUNCTION(8, "TIM15_BKIN"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(11, "ETH1_MII_RXD3 ETH1_RGMII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(128, "PI0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(1, "TRACED14"), + STM32_FUNCTION(2, "HDP6"), + STM32_FUNCTION(4, "LPTIM1_IN1"), + STM32_FUNCTION(5, "SAI4_MCLK_B"), + STM32_FUNCTION(7, "USART1_CK"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(14, "LCD_B3"), + STM32_FUNCTION(15, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(129, "PI1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(1, "TRACED15"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(6, "MDF1_SDI6"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(10, "I2C1_SDA"), + STM32_FUNCTION(11, "I3C1_SDA"), + STM32_FUNCTION(14, "LCD_B4"), + STM32_FUNCTION(15, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(130, "PI2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "LPTIM1_ETR"), + STM32_FUNCTION(5, "SAI4_SCK_B"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(14, "LCD_B5"), + STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(131, "PI3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "LPTIM1_IN2"), + STM32_FUNCTION(5, "SAI4_SD_B"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(14, "LCD_B6"), + STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(132, "PI4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "LPTIM1_CH1"), + STM32_FUNCTION(5, "SAI4_FS_B"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(14, "LCD_B7"), + STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(133, "PI5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(4, "SPI1_MOSI I2S1_SDO"), + STM32_FUNCTION(6, "UART5_CTS"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(9, "TIM5_CH2"), + STM32_FUNCTION(14, "LCD_DE"), + STM32_FUNCTION(15, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(134, "PI6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(7, "USART3_TX"), + STM32_FUNCTION(8, "TIM2_ETR"), + STM32_FUNCTION(9, "TIM3_CH1"), + STM32_FUNCTION(14, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(135, "PI7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(7, "USART3_RX"), + STM32_FUNCTION(8, "TIM2_CH1"), + STM32_FUNCTION(9, "TIM3_CH2"), + STM32_FUNCTION(14, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(136, "PI8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(137, "PI9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(2, "SPI7_MOSI"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(5, "FDCAN2_TX"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM16_BKIN"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(13, "DSI_TE"), + STM32_FUNCTION(14, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(138, "PI10"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(2, "SAI1_SCK_A"), + STM32_FUNCTION(3, "SPI1_SCK I2S1_CK"), + STM32_FUNCTION(4, "SPDIFRX1_IN0"), + STM32_FUNCTION(5, "FDCAN2_RX"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(9, "TIM4_CH1"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(13, "FMC_AD12 FMC_D12"), + STM32_FUNCTION(14, "DSI_TE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(139, "PI11"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(6, "UART8_TX"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(10, "TIM4_CH3"), + STM32_FUNCTION(11, "SDMMC3_D3"), + STM32_FUNCTION(12, "FMC_AD15 FMC_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(140, "PI12"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(3, "SPI4_NSS"), + STM32_FUNCTION(8, "FDCAN3_RX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(14, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(141, "PI13"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(3, "SPI4_MOSI"), + STM32_FUNCTION(5, "FDCAN2_RX"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(14, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(142, "PI14"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(3, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(6, "MDF1_SDI1"), + STM32_FUNCTION(8, "TIM20_CH3"), + STM32_FUNCTION(9, "TIM1_CH3N"), + STM32_FUNCTION(11, "FMC_NWAIT"), + STM32_FUNCTION(13, "FMC_AD10 FMC_D10"), + STM32_FUNCTION(14, "DCMI_D4 PSSI_D4 DCMIPP_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(143, "PI15"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(3, "I2S2_MCK"), + STM32_FUNCTION(4, "UART4_RX"), + STM32_FUNCTION(6, "MDF1_CKI2"), + STM32_FUNCTION(8, "TIM20_BKIN2"), + STM32_FUNCTION(9, "TIM1_BKIN2"), + STM32_FUNCTION(10, "SDVSEL1"), + STM32_FUNCTION(11, "SDMMC3_CDIR"), + STM32_FUNCTION(14, "DCMI_D9 PSSI_D9 DCMIPP_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(144, "PJ0"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(3, "SPI5_MOSI"), + STM32_FUNCTION(5, "PCIE_CLKREQN"), + STM32_FUNCTION(6, "SAI4_D2"), + STM32_FUNCTION(7, "USART6_CTS"), + STM32_FUNCTION(10, "USBH_HS_VBUSEN"), + STM32_FUNCTION(12, "ETH2_PTP_AUX_TS"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(14, "ETH3_PPS_OUT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(145, "PJ1"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(9, "TIM8_CH1N"), + STM32_FUNCTION(10, "I2C1_SCL"), + STM32_FUNCTION(11, "I3C1_SCL"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(15, "DCMI_VSYNC PSSI_RDY DCMIPP_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(146, "PJ2"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(5, "SAI2_SD_B"), + STM32_FUNCTION(7, "UART9_RTS"), + STM32_FUNCTION(9, "TIM8_CH4N"), + STM32_FUNCTION(10, "USBH_HS_OVRCUR"), + STM32_FUNCTION(13, "FMC_A14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(147, "PJ3"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(3, "SPI5_NSS"), + STM32_FUNCTION(4, "SAI2_FS_A"), + STM32_FUNCTION(6, "SAI4_D1"), + STM32_FUNCTION(7, "USART6_RTS"), + STM32_FUNCTION(9, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(148, "PJ4"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(4, "SAI2_FS_B"), + STM32_FUNCTION(6, "MDF1_CCK1"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(9, "TIM8_CH4"), + STM32_FUNCTION(10, "I2C2_SMBA"), + STM32_FUNCTION(11, "I2C5_SMBA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(149, "PJ5"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(4, "SAI2_SCK_B"), + STM32_FUNCTION(6, "SAI4_CK1"), + STM32_FUNCTION(7, "USART6_TX"), + STM32_FUNCTION(9, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(150, "PJ6"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ6"), + STM32_FUNCTION(3, "SPI7_MOSI"), + STM32_FUNCTION(5, "SAI4_SD_A"), + STM32_FUNCTION(7, "USART2_CK"), + STM32_FUNCTION(8, "TIM20_CH1N"), + STM32_FUNCTION(9, "TIM1_CH1"), + STM32_FUNCTION(10, "I2C6_SMBA"), + STM32_FUNCTION(14, "DCMI_D7 PSSI_D7 DCMIPP_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(151, "PJ7"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ7"), + STM32_FUNCTION(3, "SPI5_MISO"), + STM32_FUNCTION(5, "SAI2_MCLK_B"), + STM32_FUNCTION(6, "SAI4_D3"), + STM32_FUNCTION(7, "USART6_CK"), + STM32_FUNCTION(9, "TIM8_CH2N"), + STM32_FUNCTION(10, "I2C1_SMBA"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(15, "DCMI_D0 PSSI_D0 DCMIPP_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(152, "PJ8"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ8"), + STM32_FUNCTION(3, "SPI5_SCK"), + STM32_FUNCTION(6, "SAI4_CK2"), + STM32_FUNCTION(7, "USART6_RX"), + STM32_FUNCTION(9, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(15, "PSSI_D14 DCMIPP_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(153, "PJ9"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ9"), + STM32_FUNCTION(3, "SPI4_RDY"), + STM32_FUNCTION(8, "TIM12_CH1"), + STM32_FUNCTION(9, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(15, "DCMI_PIXCLK PSSI_PDCK DCMIPP_PIXCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(154, "PJ10"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ10"), + STM32_FUNCTION(8, "TIM12_CH2"), + STM32_FUNCTION(9, "TIM8_ETR"), + STM32_FUNCTION(10, "I2C1_SDA"), + STM32_FUNCTION(11, "I3C1_SDA"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(15, "DCMI_HSYNC PSSI_DE DCMIPP_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(155, "PJ11"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ11"), + STM32_FUNCTION(3, "SPI5_RDY"), + STM32_FUNCTION(4, "SAI2_SCK_A"), + STM32_FUNCTION(6, "SAI4_D4"), + STM32_FUNCTION(7, "UART9_CTS"), + STM32_FUNCTION(9, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(15, "DCMI_D12 PSSI_D12 DCMIPP_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(156, "PJ12"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(4, "SAI2_SD_A"), + STM32_FUNCTION(7, "UART9_RX"), + STM32_FUNCTION(8, "FDCAN1_TX"), + STM32_FUNCTION(9, "TIM8_BKIN2"), + STM32_FUNCTION(10, "I2C2_SCL"), + STM32_FUNCTION(11, "I3C2_SCL"), + STM32_FUNCTION(13, "FMC_A15"), + STM32_FUNCTION(15, "DCMI_D13 PSSI_D13 DCMIPP_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(157, "PJ13"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(4, "SAI2_MCLK_A"), + STM32_FUNCTION(7, "UART9_TX"), + STM32_FUNCTION(8, "FDCAN1_RX"), + STM32_FUNCTION(9, "TIM10_CH1"), + STM32_FUNCTION(10, "I2C2_SDA"), + STM32_FUNCTION(11, "I3C2_SDA"), + STM32_FUNCTION(15, "PSSI_D15 DCMIPP_D15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(158, "PJ14"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(3, "SPI4_SCK"), + STM32_FUNCTION(8, "FDCAN3_TX"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(14, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(159, "PJ15"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(1, "TRACED7"), + STM32_FUNCTION(2, "HDP7"), + STM32_FUNCTION(3, "SPI4_MISO"), + STM32_FUNCTION(5, "FDCAN2_TX"), + STM32_FUNCTION(9, "TIM11_CH1"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(14, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(160, "PK0"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK0"), + STM32_FUNCTION(3, "SPI2_MISO I2S2_SDI"), + STM32_FUNCTION(4, "SPDIFRX1_IN2"), + STM32_FUNCTION(6, "MDF1_CCK0"), + STM32_FUNCTION(8, "TIM20_ETR"), + STM32_FUNCTION(9, "TIM1_ETR"), + STM32_FUNCTION(11, "SDMMC3_D123DIR"), + STM32_FUNCTION(13, "FMC_AD11 FMC_D11"), + STM32_FUNCTION(14, "DCMI_D11 PSSI_D11 DCMIPP_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(161, "PK1"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK1"), + STM32_FUNCTION(3, "SPI2_MOSI I2S2_SDO"), + STM32_FUNCTION(6, "MDF1_SDI2"), + STM32_FUNCTION(8, "TIM20_BKIN"), + STM32_FUNCTION(9, "TIM1_BKIN"), + STM32_FUNCTION(10, "SDVSEL2"), + STM32_FUNCTION(11, "SDMMC3_D0DIR"), + STM32_FUNCTION(13, "FMC_AD13 FMC_D13"), + STM32_FUNCTION(14, "DCMI_D10 PSSI_D10 DCMIPP_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(162, "PK2"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK2"), + STM32_FUNCTION(3, "SPI7_NSS"), + STM32_FUNCTION(5, "SAI4_SCK_A"), + STM32_FUNCTION(7, "USART1_RTS"), + STM32_FUNCTION(8, "TIM20_CH2"), + STM32_FUNCTION(9, "TIM1_CH2N"), + STM32_FUNCTION(10, "I2C6_SDA"), + STM32_FUNCTION(13, "FMC_NCE3"), + STM32_FUNCTION(14, "DCMI_D6 PSSI_D6 DCMIPP_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(163, "PK3"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(3, "SPI7_RDY"), + STM32_FUNCTION(6, "MDF1_CKI1"), + STM32_FUNCTION(8, "TIM20_CH3N"), + STM32_FUNCTION(9, "TIM1_CH3"), + STM32_FUNCTION(13, "FMC_AD8 FMC_D8"), + STM32_FUNCTION(14, "DCMI_D3 PSSI_D3 DCMIPP_D3"), + STM32_FUNCTION(15, "FMC_NCE4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(164, "PK4"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(3, "SPI7_MISO"), + STM32_FUNCTION(4, "UART4_TX"), + STM32_FUNCTION(5, "SAI4_FS_A"), + STM32_FUNCTION(8, "TIM20_CH1"), + STM32_FUNCTION(9, "TIM1_CH1N"), + STM32_FUNCTION(11, "SDMMC3_CKIN"), + STM32_FUNCTION(13, "FMC_AD9 FMC_D9"), + STM32_FUNCTION(14, "DCMI_D8 PSSI_D8 DCMIPP_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(165, "PK5"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(3, "SPI2_RDY"), + STM32_FUNCTION(6, "MDF1_CKI0"), + STM32_FUNCTION(7, "USART1_TX"), + STM32_FUNCTION(8, "TIM20_CH4N"), + STM32_FUNCTION(9, "TIM1_CH4"), + STM32_FUNCTION(11, "I2C5_SCL"), + STM32_FUNCTION(13, "FMC_AD5 FMC_D5"), + STM32_FUNCTION(14, "DCMI_D1 PSSI_D1 DCMIPP_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(166, "PK6"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(3, "SPI7_SCK"), + STM32_FUNCTION(5, "SAI4_MCLK_A"), + STM32_FUNCTION(7, "USART1_CTS"), + STM32_FUNCTION(8, "TIM20_CH2N"), + STM32_FUNCTION(9, "TIM1_CH2"), + STM32_FUNCTION(10, "I2C6_SCL"), + STM32_FUNCTION(12, "FMC_AD14 FMC_D14"), + STM32_FUNCTION(13, "FMC_AD7 FMC_D7"), + STM32_FUNCTION(14, "DCMI_D5 PSSI_D5 DCMIPP_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(167, "PK7"), + STM32MP_PKG_AI, + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(6, "MDF1_SDI0"), + STM32_FUNCTION(7, "USART1_RX"), + STM32_FUNCTION(8, "TIM20_CH4"), + STM32_FUNCTION(9, "TIM1_CH4N"), + STM32_FUNCTION(11, "I2C5_SDA"), + STM32_FUNCTION(12, "FMC_NCE4"), + STM32_FUNCTION(13, "FMC_AD6 FMC_D6"), + STM32_FUNCTION(14, "DCMI_D2 PSSI_D2 DCMIPP_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static const struct stm32_desc_pin stm32mp257_z_pins[] = { + STM32_PIN_PKG( + PINCTRL_PIN(400, "PZ0"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ0"), + STM32_FUNCTION(3, "LPTIM3_IN1"), + STM32_FUNCTION(4, "SPI8_MOSI"), + STM32_FUNCTION(5, "TIM8_CH1"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM5_OUT"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(401, "PZ1"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ1"), + STM32_FUNCTION(3, "LPTIM3_CH1"), + STM32_FUNCTION(4, "SPI8_MISO"), + STM32_FUNCTION(5, "TIM8_CH2"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM5_ETR"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(10, "I2C8_SMBA"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(402, "PZ2"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ2"), + STM32_FUNCTION(3, "LPTIM3_CH1"), + STM32_FUNCTION(4, "SPI8_SCK"), + STM32_FUNCTION(6, "ADF1_CCK0"), + STM32_FUNCTION(7, "LPUART1_RTS"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(403, "PZ3"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ3"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(3, "LPTIM3_ETR"), + STM32_FUNCTION(4, "SPI8_NSS"), + STM32_FUNCTION(5, "MDF1_SDI5"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_CTS"), + STM32_FUNCTION(8, "LPTIM4_IN1"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(404, "PZ4"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ4"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(3, "MCO2"), + STM32_FUNCTION(4, "SPI8_RDY"), + STM32_FUNCTION(5, "MDF1_CCK1"), + STM32_FUNCTION(6, "ADF1_CCK1"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM4_CH1"), + STM32_FUNCTION(9, "I2C8_SCL"), + STM32_FUNCTION(12, "I3C4_SCL"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(405, "PZ5"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ5"), + STM32_FUNCTION(2, "MCO1"), + STM32_FUNCTION(3, "LPTIM3_ETR"), + STM32_FUNCTION(4, "SPI8_SCK"), + STM32_FUNCTION(6, "ADF1_CCK0"), + STM32_FUNCTION(7, "LPUART1_RTS"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(406, "PZ6"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ6"), + STM32_FUNCTION(1, "DBTRGI"), + STM32_FUNCTION(2, "DBTRGO"), + STM32_FUNCTION(4, "SPI8_NSS"), + STM32_FUNCTION(5, "TIM8_CH3"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_CTS"), + STM32_FUNCTION(8, "LPTIM5_OUT"), + STM32_FUNCTION(11, "LPTIM4_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(407, "PZ7"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ7"), + STM32_FUNCTION(4, "SPI8_MOSI"), + STM32_FUNCTION(5, "MDF1_CCK1"), + STM32_FUNCTION(6, "ADF1_CCK1"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM5_IN1"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(408, "PZ8"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ8"), + STM32_FUNCTION(3, "LPTIM3_IN1"), + STM32_FUNCTION(4, "SPI8_MISO"), + STM32_FUNCTION(5, "MDF1_SDI5"), + STM32_FUNCTION(6, "ADF1_SDI0"), + STM32_FUNCTION(7, "LPUART1_RX"), + STM32_FUNCTION(8, "LPTIM4_CH1"), + STM32_FUNCTION(9, "I2C8_SMBA"), + STM32_FUNCTION(10, "LPTIM5_ETR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN_PKG( + PINCTRL_PIN(409, "PZ9"), + STM32MP_PKG_AI | STM32MP_PKG_AK | STM32MP_PKG_AL, + STM32_FUNCTION(0, "GPIOZ9"), + STM32_FUNCTION(2, "MCO2"), + STM32_FUNCTION(4, "SPI8_RDY"), + STM32_FUNCTION(5, "MDF1_CKI5"), + STM32_FUNCTION(7, "LPUART1_TX"), + STM32_FUNCTION(8, "LPTIM4_ETR"), + STM32_FUNCTION(9, "I2C8_SDA"), + STM32_FUNCTION(11, "LPTIM3_CH2"), + STM32_FUNCTION(12, "I3C4_SDA"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32mp257_match_data = { + .pins = stm32mp257_pins, + .npins = ARRAY_SIZE(stm32mp257_pins), +}; + +static struct stm32_pinctrl_match_data stm32mp257_z_match_data = { + .pins = stm32mp257_z_pins, + .npins = ARRAY_SIZE(stm32mp257_z_pins), +}; + +static const struct of_device_id stm32mp257_pctrl_match[] = { + { + .compatible = "st,stm32mp257-pinctrl", + .data = &stm32mp257_match_data, + }, + { + .compatible = "st,stm32mp257-z-pinctrl", + .data = &stm32mp257_z_match_data, + }, + { } +}; + +static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume) +}; + +static struct platform_driver stm32mp257_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32mp257-pinctrl", + .of_match_table = stm32mp257_pctrl_match, + .pm = &stm32_pinctrl_dev_pm_ops, + }, +}; + +static int __init stm32mp257_pinctrl_init(void) +{ + return platform_driver_register(&stm32mp257_pinctrl_driver); +} +arch_initcall(stm32mp257_pinctrl_init); From c3053382574a5a829c93fb5ab0bb52d20456e745 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 5 Jan 2021 13:37:13 +0100 Subject: [PATCH 37/44] dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon Add the new syscon compatible for STM32MP25 syscfg = "st,stm32mp25-syscfg". Reorder enum following ASCII oredering. Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ad8e51aa01b0c..b63ff591ef8f7 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -15,12 +15,13 @@ properties: oneOf: - items: - enum: - - st,stm32mp157-syscfg - - st,stm32mp151-pwr-mcu - - st,stm32-syscfg - st,stm32-power-config + - st,stm32-syscfg - st,stm32-tamp - st,stm32f4-gcan + - st,stm32mp151-pwr-mcu + - st,stm32mp157-syscfg + - st,stm32mp25-syscfg - const: syscon - items: - const: st,stm32-tamp From 9e4e24414cc6b45bd887d746a59691e295431ddf Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 24 May 2023 14:37:27 +0200 Subject: [PATCH 38/44] arm64: introduce STM32 family on Armv8 architecture Add a dedicated ARCH_STM32 for STM32 SoCs config. First STM32 Armv8 SoC family is the STM32MP25 which is composed of STM32MP251, STM32MP253, STM32MP255, STM32MP257 SoCs. Signed-off-by: Alexandre Torgue --- arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d6..b1818d100d88c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -277,6 +277,20 @@ config ARCH_INTEL_SOCFPGA Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, Agilex and eASIC N5X. +config ARCH_STM32 + bool "STMicroelectronics STM32 SoC Family" + select GPIOLIB + select PINCTRL + select PINCTRL_STM32MP257 + select ARM_SMC_MBOX + select ARM_SCMI_PROTOCOL + select COMMON_CLK_SCMI + help + This enables support for ARMv8 based STMicroelectronics + STM32 family, including: + - STM32MP25: + - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. + config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" select IRQ_FASTEOI_HIERARCHY_HANDLERS From 5d30d03aaf78586c37100006ba271d045f730bb5 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 7 Oct 2020 15:29:52 +0200 Subject: [PATCH 39/44] arm64: dts: st: introduce stm32mp25 SoCs family STM32MP25 family is composed of 4 SoCs defined as following: -STM32MP251: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ... -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and LVDS display. -STM32MP255: STM32MP253 + GPU/AI and video encode/decode. -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports). A second diversity layer exists for security features/ A35 frequency: -STM32MP25xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 279 ++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp253.dtsi | 23 ++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 9 + arch/arm64/boot/dts/st/stm32mp257.dtsi | 9 + arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 8 + arch/arm64/boot/dts/st/stm32mp25xf.dtsi | 8 + 6 files changed, 336 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp251.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp253.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp255.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp257.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp25xf.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi new file mode 100644 index 0000000000000..5268a43218415 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi new file mode 100644 index 0000000000000..af48e82efe8a9 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi new file mode 100644 index 0000000000000..e6fa596211f5c --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257.dtsi b/arch/arm64/boot/dts/st/stm32mp257.dtsi new file mode 100644 index 0000000000000..5c5000d3d9dbc --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi new file mode 100644 index 0000000000000..5e83a6926485f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xf.dtsi b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi new file mode 100644 index 0000000000000..5e83a6926485f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; From 3b170e1653c05b067ea6ef616ece961b07714f48 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 7 Jan 2021 14:15:12 +0100 Subject: [PATCH 40/44] arm64: dts: st: introduce stm32mp25 pinctrl files Three packages exist for stm32mp25 dies. As ball-out is different between them, this patch covers those differences by introducing dedicated pinctrl dtsi files. Each dtsi pinctrl package file describes the package ball-out through gpio-ranges. Available packages are: STM32MP25xAI: 18*18/FCBGA 172 ios STM32MP25xAK: 14*14/FCBGA 144 ios STM32MP25xAL: 10*10/TFBGA 144 ios It includes also the common file used for pin groups definition. Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 7 ++ .../boot/dts/st/stm32mp25xxai-pinctrl.dtsi | 83 +++++++++++++++++++ .../boot/dts/st/stm32mp25xxak-pinctrl.dtsi | 71 ++++++++++++++++ .../boot/dts/st/stm32mp25xxal-pinctrl.dtsi | 71 ++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi new file mode 100644 index 0000000000000..5bd27767fbf59 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + diff --git a/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 0000000000000..abdbc7aebc7f1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 0000000000000..2e0d4d349d143 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 0000000000000..2406e972554c1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; From 6defdc268916a6f92a24d3495b22cd9c573e4357 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 24 May 2023 16:39:51 +0200 Subject: [PATCH 41/44] dt-bindings: stm32: document stm32mp257f-ev1 board Add new entry for stm32mp257f-ev1 board. Signed-off-by: Alexandre Torgue Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4af5b8f4f8032..4466b455bffad 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -161,6 +161,12 @@ properties: - const: phytec,phycore-stm32mp157c-som - const: st,stm32mp157 + - description: ST STM32MP257 based Boards + items: + - enum: + - st,stm32mp257f-ev1 + - const: st,stm32mp257 + additionalProperties: true ... From 1c89075497bb6347fcda99442f3505043b4d2fdf Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 18 Nov 2021 12:26:49 +0100 Subject: [PATCH 42/44] arm64: dts: st: add stm32mp257f-ev1 board support Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/st/Makefile | 2 + arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 31 ++++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 50 +++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/st/Makefile create mode 100644 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 7b107fa7414bf..30dd6347a929e 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,6 +27,7 @@ subdir-y += renesas subdir-y += rockchip subdir-y += socionext subdir-y += sprd +subdir-y += st subdir-y += synaptics subdir-y += tesla subdir-y += ti diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile new file mode 100644 index 0000000000000..881fe1296c581 --- /dev/null +++ b/arch/arm64/boot/dts/st/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 5bd27767fbf59..d34a1d5e79c06 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -5,3 +5,34 @@ */ #include +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = ; /* USART2_TX */ + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts new file mode 100644 index 0000000000000..39b4726cc0986 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; From 064433f84e6b69055379aa11a4084627537ee64e Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 24 May 2023 17:27:13 +0200 Subject: [PATCH 43/44] arm64: defconfig: enable ARCH_STM32 and STM32 serial driver Allow a basic boot on STM32MP257 SoC. Signed-off-by: Alexandre Torgue --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a24609e14d50e..2e0b4ffcb2ced 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -58,6 +58,7 @@ CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_STM32=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_TESLA_FSD=y @@ -461,6 +462,8 @@ CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_STM32=y +CONFIG_SERIAL_STM32_CONSOLE=y CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_OWL=y CONFIG_SERIAL_DEV_BUS=y From c9cb7e72e293141d0d6c1d74c26788d3a0605172 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 25 May 2023 17:28:19 +0200 Subject: [PATCH 44/44] MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE STM32 SoCs based on Armv8 have been added to the STM32 family. Those new SoCs are maintained as legacy STM32 MPU. Signed-off-by: Alexandre Torgue --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e5..06759396e2201 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2849,6 +2849,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-nex F: arch/arm/boot/dts/stm32* F: arch/arm/mach-stm32/ F: drivers/clocksource/armv7m_systick.c +F: arch/arm64/boot/dts/st/ N: stm32 N: stm