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Merge tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux…
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…/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Main pin control pull request for the v3.13 cycle.

  The changes hitting arch/blackfin are ACKed by the Blackfin
  maintainer, and the device tree bindings are ACKed to the extent
  possible by someone from the device tree maintainers group.

   - Blackfin ADI pin control driver, we move yet another architecture
     under this subsystem umbrella.

   - Incremental updates to the Renesas Super-H PFC pin control driver.
     New subdriver for the r8a7791 SoC.

   - Non-linear GPIO ranges from the gpiolib side of things, this
     enabled simplified device tree bindings by referring entire groups
     of pins on some pin controller to act as back-end for a certain
     GPIO-chip driver.

   - Add the Abilis TB10x pin control driver used on the ARC
     architecture.  Also the corresponding GPIO driver is merged through
     this tree, so the ARC has full support for pins and GPIOs after
     this.

   - Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin controller
     instances.  The i.MX1 and i.MX27 is an entirely new family
     (silicon) of controllers whereas i.MX50 is a variant of the
     previous supported controller.

   - Then the usual slew of fixes, cleanups and incremental updates"

The ARC DT changes are apparently still pending, that hopefully gets
sorted out in a timely manner.

* tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
  pinctrl: imx50: add pinctrl support code for the IMX50 SoC
  pinctrl: at91: copy define to driver
  pinctrl: remove minor dead code
  pinctrl: imx: fix using pin->input_val wrongly
  pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe()
  gpio: tb10x: fix return value check in tb10x_gpio_probe()
  gpio: tb10x: use module_platform_driver to simplify the code
  pinctrl: imx27: imx27 pincontrol driver
  pinctrl: imx1 core driver
  pinctrl: sh-pfc: r8a7791 PFC support
  sh-pfc: r8a7778: Add CAN pin groups
  gpio: add TB10x GPIO driver
  pinctrl: at91: correct a few typos
  pinctrl: mvebu: remove redundant of_match_ptr
  pinctrl: tb10x: use module_platform_driver to simplify the code
  pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe()
  pinctrl: add documentation for pinctrl_get_group_pins()
  pinctrl: rockchip: emulate both edge triggered interrupts
  pinctrl: rockchip: add rk3188 specifics
  pinctrl: rockchip: remove redundant check
  ...
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Linus Torvalds committed Nov 12, 2013
2 parents eeab517 + 9da8312 commit 8a5dc58
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36 changes: 36 additions & 0 deletions Documentation/devicetree/bindings/gpio/abilis,tb10x-gpio.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
* Abilis TB10x GPIO controller

Required Properties:
- compatible: Should be "abilis,tb10x-gpio"
- reg: Address and length of the register set for the device
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted).
- abilis,ngpio: the number of GPIO pins this driver controls.

Optional Properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
- interrupts: Defines the interrupt line connecting this GPIO controller to
its parent interrupt controller.
- interrupt-parent: Defines the parent interrupt controller.

GPIO ranges are specified as described in
Documentation/devicetree/bindings/gpio/gpio.txt

Example:

gpioa: gpio@FF140000 {
compatible = "abilis,tb10x-gpio";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&tb10x_ictl>;
interrupts = <27 2>;
reg = <0xFF140000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
abilis,ngpio = <3>;
gpio-ranges = <&iomux 0 0 0>;
gpio-ranges-group-names = "gpioa_pins";
};
40 changes: 38 additions & 2 deletions Documentation/devicetree/bindings/gpio/gpio.txt
Original file line number Diff line number Diff line change
Expand Up @@ -87,8 +87,10 @@ controllers. The gpio-ranges property described below represents this, and
contains information structures as follows:

gpio-range-list ::= <single-gpio-range> [gpio-range-list]
single-gpio-range ::=
single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
numeric-gpio-range ::=
<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
gpio-phandle : phandle to pin controller node.
gpio-base : Base GPIO ID in the GPIO controller
pinctrl-base : Base pinctrl pin ID in the pin controller
Expand All @@ -97,14 +99,27 @@ contains information structures as follows:
The "pin controller node" mentioned above must conform to the bindings
described in ../pinctrl/pinctrl-bindings.txt.

In case named gpio ranges are used (ranges with both <pinctrl-base> and
<count> set to 0), the property gpio-ranges-group-names contains one string
for every single-gpio-range in gpio-ranges:
gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
gpiorange-name : Name of the pingroup associated to the GPIO range in
the respective pin controller.

Elements of gpiorange-names-list corresponding to numeric ranges contain
the empty string. Elements of gpiorange-names-list corresponding to named
ranges contain the name of a pin group defined in the respective pin
controller. The number of pins/GPIOs in the range is the number of pins in
that pin group.

Previous versions of this binding required all pin controller nodes that
were referenced by any gpio-ranges property to contain a property named
#gpio-range-cells with value <3>. This requirement is now deprecated.
However, that property may still exist in older device trees for
compatibility reasons, and would still be required even in new device
trees that need to be compatible with older software.

Example:
Example 1:

qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
Expand All @@ -117,3 +132,24 @@ Example:
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
pins 50..59.

Example 2:

gpio_pio_i: gpio-controller@14B0 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1480 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 0 20 10>,
<&pinctrl2 10 0 0>,
<&pinctrl1 15 0 10>,
<&pinctrl2 25 0 0>;
gpio-ranges-group-names = "",
"foo",
"",
"bar";
};

Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
are named "foo" and "bar".
80 changes: 80 additions & 0 deletions Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,80 @@
Abilis Systems TB10x pin controller
===================================

Required properties
-------------------

- compatible: should be "abilis,tb10x-iomux";
- reg: should contain the physical address and size of the pin controller's
register range.


Function definitions
--------------------

Functions are defined (and referenced) by sub-nodes of the pin controller.
Every sub-node defines exactly one function (implying a set of pins).
Every function is associated to one named pin group inside the pin controller
driver and these names are used to associate pin group predefinitions to pin
controller sub-nodes.

Required function definition subnode properties:
- abilis,function: should be set to the name of the function's pin group.

The following pin groups are available:
- GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion
- Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
- Parallel TS input ports: mip1, mip3, mip5, mip7
- Serial TS output ports: mos0, mos1, mos2, mos3
- Parallel TS output port: mop
- CI+ port: ciplus
- CableCard (Mcard) port: mcard
- Smart card ports: stc0, stc1
- UART ports: uart0, uart1
- SPI ports: spi1, spi3
- JTAG: jtag

All other ports of the chip are not multiplexed and thus not managed by this
driver.


GPIO ranges definition
----------------------

The named pin groups of GPIO ports can be used to define GPIO ranges as
explained in Documentation/devicetree/bindings/gpio/gpio.txt.


Example
-------

iomux: iomux@FF10601c {
compatible = "abilis,tb10x-iomux";
reg = <0xFF10601c 0x4>;
pctl_gpio_a: pctl-gpio-a {
abilis,function = "gpioa";
};
pctl_uart0: pctl-uart0 {
abilis,function = "uart0";
};
};
uart@FF100000 {
compatible = "snps,dw-apb-uart";
reg = <0xFF100000 0x100>;
clock-frequency = <166666666>;
interrupts = <25 1>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pctl_uart0>;
};
gpioa: gpio@FF140000 {
compatible = "abilis,tb10x-gpio";
reg = <0xFF140000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpio = <3>;
gpio-ranges = <&iomux 0 0>;
gpio-ranges-group-names = "gpioa";
};
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, multi drive, etc.

Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl"
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.

Expand Down
37 changes: 18 additions & 19 deletions Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
Original file line number Diff line number Diff line change
Expand Up @@ -22,11 +22,12 @@ Required properties for iomux controller:
Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.

Required properties for pin configuration node:
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, which consists of a tuple of
<mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting
value like pull-up on this pin.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. And that's why fsl,pins entry
looks like <PIN_FUNC_ID CONFIG> in the example below.

Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
Expand Down Expand Up @@ -72,24 +73,22 @@ iomuxc@020e0000 {
/* shared pinctrl settings */
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
};
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
....
};
Refer to the IOMUXC controller chapter in imx6q datasheet,
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
80Ohm driver strength and Fast Slew Rate.
User should refer to each SoC spec to set the correct value.

TODO: when dtc macro support is available, we can change above raw data
to dt macro which can get better readability in dts file.
99 changes: 99 additions & 0 deletions Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,99 @@
* Freescale IMX27 IOMUX Controller

Required properties:
- compatible: "fsl,imx27-iomuxc"

The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.

Required properties for pin configuration node:
- fsl,pins: three integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.

PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
number on the specific port (between 0 and 31).

MUX_ID is
function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)

function value is used to select the pin function.
Possible values:
0 - Primary function
1 - Alternate function
2 - GPIO
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)

direction defines the data direction of the pin.
Possible values:
0 - Input
1 - Output
Register: DDIR

gpio_oconf configures the gpio submodule output signal. This does not
have any effect unless GPIO function is selected. A/B/C_IN are output
signals of function blocks A,B and C. Specific function blocks are
described in the reference manual.
Possible values:
0 - A_IN
1 - B_IN
2 - C_IN
3 - Data Register
Registers: OCR1, OCR2

gpio_iconfa/b configures the gpio submodule input to functionblocks A and
B. GPIO function should be selected if this is configured.
Possible values:
0 - GPIO_IN
1 - Interrupt Status Register
2 - Pulldown
3 - Pullup
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2

CONFIG can be 0 or 1, meaning Pullup disable/enable.



Example:

iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;

uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>;
};

...
};
};


For convenience there are macros defined in imx27-pinfunc.h which provide PIN
and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
are defined in the i.MX27 reference manual.

The above example using macros:

iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;

uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};

...
};
};
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ pinctrl-bindings.txt:

Required: pins
Options: function, bias-disable, bias-pull-up, bias-pull-down,
bias-pin-default, drive-open-drain.
drive-open-drain.

Note that many of these properties are only valid for certain specific pins.
See the Palmas device datasheet for complete details regarding which pins
Expand Down
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