From 02183a5250193aae6913ed3ee720be021ae92b03 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 15 Jul 2016 00:00:05 +0300 Subject: [PATCH 01/26] ARM: dts: r8a7792: add PFC support Define the generic R8A7792 part of the PFC device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 3fd61d7ab9066..0b746ddd5cd6e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -108,6 +108,11 @@ #power-domain-cells = <1>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7792"; + reg = <0 0xe6060000 0 0x144>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; From 2cd452d19e6e79ea58c8022c43248b64d579db60 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 15 Jul 2016 00:00:56 +0300 Subject: [PATCH 02/26] ARM: dts: blanche: add SCIF0/3 pins Add the (previously omitted) SCIF0/3 pin data to the Blanche board's device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index e7b40f0e7da60..9b550bde939af 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -57,10 +57,28 @@ clock-frequency = <20000000>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif3_pins: scif3 { + groups = "scif3_data"; + function = "scif3"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; &scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + status = "okay"; }; From 1d93a8b5a234282724f6f4a3113e1d32bea0ec71 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 14:02:01 -0700 Subject: [PATCH 03/26] ARM: dts: blanche: add Ethernet pins Add the (previously omitted) pin data for the SMSC LAN89218 Ethernet chip to the Blanche board's device tree: the chip's IRQ output is connected to the SoC's IRQ0 pin and its nCS input is connected to the SoC's EX_CS0# pin. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 9b550bde939af..4777a609ff81f 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -50,6 +50,9 @@ reg-io-width = <4>; vddvario-supply = <&d3_3v>; vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; }; }; @@ -67,6 +70,17 @@ groups = "scif3_data"; function = "scif3"; }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; }; &scif0 { From 4e2b4f6626541dd791d468c9ccd2d0cc72cc0989 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 6 Jul 2016 01:01:22 +0300 Subject: [PATCH 04/26] ARM: dts: r8a7792: add GPIO clocks Describe the GPIO clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 0b746ddd5cd6e..da3eb295c6f1a 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -370,6 +370,27 @@ clock-output-names = "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0"; }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 + R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 + R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 + R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 + R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 + R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 + >; + clock-output-names = + "gpio7", "gpio6", "gpio5", "gpio4", + "gpio3", "gpio2", "gpio1", "gpio0", + "gpio11", "gpio10", "gpio9", "gpio8"; + }; }; /* External root clock */ From 63359c2ddc86bded339f38bde504994f123ebd63 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 6 Jul 2016 01:02:20 +0300 Subject: [PATCH 05/26] ARM: dts: r8a7792: add GPIO support Describe all 12 GPIO controllers in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 168 +++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index da3eb295c6f1a..d5ab9474297e3 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -113,6 +113,174 @@ reg = <0 0xe6060000 0 0x144>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio6: gpio@e6055100 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055100 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio7: gpio@e6055200 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055200 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio8: gpio@e6055300 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055300 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio9: gpio@e6055400 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio10: gpio@e6055500 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055500 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio11: gpio@e6055600 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055600 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 352 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; From 08cafff67e8881e1622068924aaab3c3aa052b0b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 5 Jul 2016 00:22:38 +0300 Subject: [PATCH 06/26] ARM: dts: r8a7792: add EtherAVB clocks Add the EtherAVB clock and its parent, HP clock to the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index d5ab9474297e3..f97b034da35fd 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -471,6 +471,13 @@ clock-div = <6>; clock-mult = <1>; }; + hp_clk: hp { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -538,6 +545,15 @@ clock-output-names = "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0"; }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&hp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "etheravb"; + }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; From b12dcdcc474977095ce72152b285be7f94d0efd3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 5 Jul 2016 00:23:30 +0300 Subject: [PATCH 07/26] ARM: dts: r8a7792: add EtherAVB support Define the generic R8A7792 part of the EtherAVB device node. Based on the commit 89aac8af1a60 ("ARM: dts: r8a7794: add EtherAVB support"). Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index f97b034da35fd..37c9d95688cfa 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -444,6 +444,18 @@ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7792", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", From 47db051c22a03d41eac0d8193f3fe37b4f9768e9 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 23:19:44 +0300 Subject: [PATCH 08/26] ARM: dts: r8a7792: add CAN clocks The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and the external clock fed on the CAN_CLK pin. Describe those clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 37c9d95688cfa..af8020bfc030f 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -511,6 +511,13 @@ clock-div = <8>; clock-mult = <1>; }; + rcan_clk: rcan { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <49>; + clock-mult = <1>; + }; /* Gate clocks */ mstp1_clks: mstp1_clks@e6150134 { @@ -572,7 +579,8 @@ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>; + <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, + <&cp_clk>, <&cp_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 @@ -580,12 +588,14 @@ R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 + R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 >; clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "gpio9", "gpio8"; + "gpio11", "gpio10", "can1", "can0", + "gpio9", "gpio8"; }; }; @@ -604,4 +614,12 @@ /* This value must be overridden by the board. */ clock-frequency = <0>; }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; From f947c02a0f86dffa5258ef347c6b6980953a9679 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 23:20:35 +0300 Subject: [PATCH 09/26] ARM: dts: r8a7792: add CAN support Define the generic R8A7792 parts of the CAN0/1 device nodes. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index af8020bfc030f..1b96bf6393fbf 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -456,6 +456,30 @@ status = "disabled"; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_CAN0>, + <&rcan_clk>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_CAN1>, + <&rcan_clk>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", From 38584104eafb6ed40ca06c8421dcc369c9015c1d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 23:21:15 +0300 Subject: [PATCH 10/26] ARM: dts: blanche: add CAN0 support Define the Blanche board dependent part of the CAN0 device node along with the CAN_CLK crystal. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 4777a609ff81f..eeffba870211a 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -60,6 +60,10 @@ clock-frequency = <20000000>; }; +&can_clk { + clock-frequency = <48000000>; +}; + &pfc { scif0_pins: scif0 { groups = "scif0_data"; @@ -81,6 +85,11 @@ function = "lbsc"; }; }; + + can0_pins: can0 { + groups = "can0_data", "can_clk"; + function = "can0"; + }; }; &scif0 { @@ -96,3 +105,10 @@ status = "okay"; }; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; From 83701e00ded47e7f6390c6a123209426565046b7 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 21 Jul 2016 08:44:08 +0900 Subject: [PATCH 11/26] ARM: dts: r8a7794: Correct SDHI register size r8a7794 SDHI ch0 has SD_DMACR which is located in 0x324. This patch updates register size Based on work for the r8a7790 by Kuninori Morimoto. Cc: Kuninori Morimoto Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/r8a7794.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 685f986cf9627..55737bca4e63f 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -697,7 +697,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, From fe683922cb436097ac5b1f65148fa0db3a6735a3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:10:31 +0300 Subject: [PATCH 12/26] ARM: dts: r8a7792: add SD clocks Describe the SDHI0 clock and its parent, SD clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 1b96bf6393fbf..4148c5867c07b 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -535,6 +535,13 @@ clock-div = <8>; clock-mult = <1>; }; + sd_clk: sd { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; rcan_clk: rcan { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; @@ -564,6 +571,15 @@ >; clock-output-names = "sys-dmac1", "sys-dmac0"; }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&sd_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "sdhi0"; + }; mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; From ce01b14ecf19a18cd95e698f915f5ea582086c21 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:11:26 +0300 Subject: [PATCH 13/26] ARM: dts: r8a7792: add SDHI support Define the generic R8A7792 part of the SDHI0 device node. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 4148c5867c07b..228860d9464ac 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -435,6 +435,18 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7792"; + reg = <0 0xee100000 0 0x328>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7792", "renesas,rcar-gen2-jpu"; From eedee25c2181ffd5463a994d456349dd39dc1b54 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:48:33 +0300 Subject: [PATCH 14/26] ARM: dts: r8a7792: add I2C clocks Describe the I2C[0-5] clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 228860d9464ac..353bc303b1651 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -632,7 +632,8 @@ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, - <&cp_clk>, <&cp_clk>; + <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 @@ -642,12 +643,16 @@ R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 + R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 + R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 + R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 >; clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", "gpio11", "gpio10", "can1", "can0", - "gpio9", "gpio8"; + "gpio9", "gpio8", "i2c5", "i2c4", + "i2c3", "i2c2", "i2c1", "i2c0"; }; }; From 78082700c8885a2b370c23ed9caec781fdf72139 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:49:12 +0300 Subject: [PATCH 15/26] ARM: dts: r8a7792: add I2C support Define the generic R8A7792 parts of the I2C[0-5] device nodes. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 82 ++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 353bc303b1651..89f248c5cd9e0 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -18,6 +18,15 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; +}; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -468,6 +477,79 @@ status = "disabled"; }; + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7792", "renesas,rcar-gen2-can"; From 62855bcf15796de1231c93652d385a8b11be75c4 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 22:16:38 +0300 Subject: [PATCH 16/26] ARM: dts: r8a7792: add VIN clocks Describe the VIN[0-5] clocks and their parent, ZG clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 89f248c5cd9e0..dbe2f28fee992 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -643,6 +643,13 @@ clock-div = <49>; clock-mult = <1>; }; + zg_clk: zg { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <5>; + clock-mult = <1>; + }; /* Gate clocks */ mstp1_clks: mstp1_clks@e6150134 { @@ -702,10 +709,17 @@ compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + <&zg_clk>, <&zg_clk>, <&hp_clk>; #clock-cells = <1>; - clock-indices = ; - clock-output-names = "etheravb"; + clock-indices = < + R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 + R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 + R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 + R8A7792_CLK_ETHERAVB + >; + clock-output-names = "vin5", "vin4", "vin3", "vin2", + "vin1", "vin0", "etheravb"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7792-mstp-clocks", From a2d30b9c555f02c6a2aa389fbd41a103503242dd Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 22:17:42 +0300 Subject: [PATCH 17/26] ARM: dts: r8a7792: add VIN support Define the generic R8A7792 parts of the VIN[0-5] device nodes. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index dbe2f28fee992..e1f85a9904d0d 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -25,6 +25,12 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; + vin4 = &vin4; + vin5 = &vin5; }; cpus { @@ -574,6 +580,66 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", From 0b1f0e374404f70b77c0f79c6f16fdcf5484552b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 23:59:18 +0300 Subject: [PATCH 18/26] ARM: dts: r8a7794: add audio clocks Describe the external audio clocks (signals AUDIO_CLK[ABC]) required by the sound driver. Boards that provide audio clocks need to override the clock frequencies. This patch is based on the commit 0d3dbde84a45 ("ARM: shmobile: r8a7791: add audio clock on DTSI"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 55737bca4e63f..5d1fded796336 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -952,6 +952,27 @@ clock-frequency = <0>; }; + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7794-cpg-clocks", From 2a29f9d6fea82485941449c2328af5b2a4ea636f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 23:59:59 +0300 Subject: [PATCH 19/26] ARM: dts: r8a7794: add MSTP5 clocks Add some MSTP5 clocks to the R8A7794 device tree. Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 9 +++++++++ include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 5d1fded796336..1c2d3846d70ea 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1204,6 +1204,15 @@ clock-indices = ; clock-output-names = "irqc"; }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&hp_clk>, <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "audmac0", "pwm"; + }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index a3491ba2f6ecb..f8279eca033e1 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -67,6 +67,7 @@ #define R8A7794_CLK_IRQC 7 /* MSTP5 */ +#define R8A7794_CLK_AUDIO_DMAC0 2 #define R8A7794_CLK_PWM 23 /* MSTP7 */ From 975fb77f874be95e50e653e90bcbcf09c08e66c2 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 14:01:01 -0700 Subject: [PATCH 20/26] ARM: dts: r8a7794: add MSTP10 clocks Add MSTP10 clocks to the R8A7794 device tree. This patch is based on the commit ee9141522dcf ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 52 +++++++++++++++++++++++ include/dt-bindings/clock/r8a7794-clock.h | 24 +++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 1c2d3846d70ea..cba41c199fd83 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1267,6 +1267,58 @@ "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7794-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", + "ssi6", "ssi5", "ssi4", "ssi3", + "ssi2", "ssi1", "ssi0", + "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src6", "scu-src5", "scu-src4", + "scu-src3", "scu-src2", "scu-src1"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index f8279eca033e1..9d02f5317c7c3 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -108,6 +108,30 @@ #define R8A7794_CLK_I2C1 30 #define R8A7794_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7794_CLK_SSI_ALL 5 +#define R8A7794_CLK_SSI9 6 +#define R8A7794_CLK_SSI8 7 +#define R8A7794_CLK_SSI7 8 +#define R8A7794_CLK_SSI6 9 +#define R8A7794_CLK_SSI5 10 +#define R8A7794_CLK_SSI4 11 +#define R8A7794_CLK_SSI3 12 +#define R8A7794_CLK_SSI2 13 +#define R8A7794_CLK_SSI1 14 +#define R8A7794_CLK_SSI0 15 +#define R8A7794_CLK_SCU_ALL 17 +#define R8A7794_CLK_SCU_DVC1 18 +#define R8A7794_CLK_SCU_DVC0 19 +#define R8A7794_CLK_SCU_CTU1_MIX1 20 +#define R8A7794_CLK_SCU_CTU0_MIX0 21 +#define R8A7794_CLK_SCU_SRC6 25 +#define R8A7794_CLK_SCU_SRC5 26 +#define R8A7794_CLK_SCU_SRC4 27 +#define R8A7794_CLK_SCU_SRC3 28 +#define R8A7794_CLK_SCU_SRC2 29 +#define R8A7794_CLK_SCU_SRC1 30 + /* MSTP11 */ #define R8A7794_CLK_SCIFA3 6 #define R8A7794_CLK_SCIFA4 7 From 298e4ee3d213a0764e8d4baa5336d4d1649a5bc5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 28 Jul 2016 00:02:18 +0300 Subject: [PATCH 21/26] ARM: dts: r8a7794: add Audio-DMAC support Describe Audio-DMAC in the R8A7794 device tree. This patch is loosely based on the commit 8994fff67761 ("ARM: shmobile: r8a7791: Add Audio DMAC devices to DT"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index cba41c199fd83..668e1383dd098 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -296,6 +296,34 @@ dma-channels = <15>; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", + "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,rcar-gen2-scifa", "renesas,scifa"; From 320d6c5a08a4abd3990ee4744033ade6ed53d5fb Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 28 Jul 2016 00:03:10 +0300 Subject: [PATCH 22/26] ARM: dts: r8a7794: add sound support Define the generic R8A7794 part of the sound device node. This sound device is a complex one and comprises the Audio Clock Generator (ADG), Sampling Rate Converter Unit (SCU), Serial Sound Interface [Unit] (SSI[U]), and Audio DMAC-Peripheral-Peripheral. It is up to the board file to enable the device. This patch is based on the R8A7791 sound work by Kuninori Morimoto. Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 181 +++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 668e1383dd098..6216a170a3df9 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1416,4 +1416,185 @@ #iommu-cells = <1>; status = "disabled"; }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7794", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI9>, + <&mstp10_clks R8A7794_CLK_SSI8>, + <&mstp10_clks R8A7794_CLK_SSI7>, + <&mstp10_clks R8A7794_CLK_SSI6>, + <&mstp10_clks R8A7794_CLK_SSI5>, + <&mstp10_clks R8A7794_CLK_SSI4>, + <&mstp10_clks R8A7794_CLK_SSI3>, + <&mstp10_clks R8A7794_CLK_SSI2>, + <&mstp10_clks R8A7794_CLK_SSI1>, + <&mstp10_clks R8A7794_CLK_SSI0>, + <&mstp10_clks R8A7794_CLK_SCU_SRC6>, + <&mstp10_clks R8A7794_CLK_SCU_SRC5>, + <&mstp10_clks R8A7794_CLK_SCU_SRC4>, + <&mstp10_clks R8A7794_CLK_SCU_SRC3>, + <&mstp10_clks R8A7794_CLK_SCU_SRC2>, + <&mstp10_clks R8A7794_CLK_SCU_SRC1>, + <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, + <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, + <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7794_CLK_SCU_DVC0>, + <&mstp10_clks R8A7794_CLK_SCU_DVC1>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&m2_clk>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", "src.2", + "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&cpg_clocks>; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + + rcar_sound,src { + src@0 { + status = "disabled"; + }; + src1: src@1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi@0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; }; From feb13b95c3fc461bb01ef32cdb818f99d6a859db Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 28 Jul 2016 00:05:58 +0300 Subject: [PATCH 23/26] ARM: dts: silk: add sound support Define the SILK board dependent part of the R8A7794 sound device node. Add device node for Asahi Kasei AK4643 stereo codec to the I2C1 bus. Add the "simple-audio-card" device node to interconnect the SoC sound device and the codec. This patch is based on the commit 493b4da7c10c ("ARM: dts: porter: add sound support"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-silk.dts | 70 ++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index cf24f45fff228..cf880ac06f4b7 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -10,6 +10,17 @@ * kind, whether express or implied. */ +/* + * SSI-AK4643 + * + * SW1: 2-1: AK4643 + * 2-3: ADV7511 + * + * This command is required before playback/capture: + * + * amixer set "LINEOUT Mixer DACL" on + */ + /dts-v1/; #include "r8a7794.dtsi" #include @@ -119,6 +130,29 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + x9_clk: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&soundcodec>; + simple-audio-card,frame-master = <&soundcodec>; + + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + soundcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&x9_clk>; + }; + }; }; &extal_clk { @@ -193,6 +227,16 @@ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; function = "du1"; }; + + ssi_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + audio_clk_pins: audio_clk { + groups = "audio_clkc"; + function = "audio_clk"; + }; }; &scif2 { @@ -230,6 +274,12 @@ status = "okay"; clock-frequency = <400000>; + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; @@ -392,3 +442,23 @@ }; }; }; + +&rcar_sound { + pinctrl-0 = <&ssi_pins &audio_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>; + capture = <&ssi1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; From d6f5fe84b5f99ab3fad6911b825098ebdeb4a921 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 6 Aug 2016 00:52:39 +0300 Subject: [PATCH 24/26] ARM: dts: r8a7792: fix misindented line Commit 2a0900655d5e (ARM: dts: r8a7792: add I2C support) had a wrongly indented line at the end of the "aliases" subnode -- fix it. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index e1f85a9904d0d..eaa0c48c61849 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -31,7 +31,7 @@ vin3 = &vin3; vin4 = &vin4; vin5 = &vin5; -}; + }; cpus { #address-cells = <1>; From 3b0211af06298682d5faaa4c4cedf666fb1281c3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 5 Aug 2016 21:25:47 +0300 Subject: [PATCH 25/26] ARM: dts: r8a7792: add DU clocks Describe the DU0/1 clocks and their parent, ZX clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index eaa0c48c61849..7e0c57ff9892e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -660,6 +660,13 @@ clock-div = <2>; clock-mult = <1>; }; + zx_clk: zx { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -761,15 +768,17 @@ "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>; + <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 + R8A7792_CLK_DU1 R8A7792_CLK_DU0 >; clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0"; + "scif2", "scif1", "scif0", + "du1", "du0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7792-mstp-clocks", From 8bec0842ba2bb1b3bd954a1ef50f426b8f09c84f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 5 Aug 2016 21:26:25 +0300 Subject: [PATCH 26/26] ARM: dts: r8a7792: add DU support Define the generic R8A7792 part of the DU device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 7e0c57ff9892e..9763289db5ceb 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -556,6 +556,34 @@ status = "disabled"; }; + du: display@feb00000 { + compatible = "renesas,du-r8a7792"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = , + ; + clocks = <&mstp7_clks R8A7792_CLK_DU0>, + <&mstp7_clks R8A7792_CLK_DU1>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7792", "renesas,rcar-gen2-can";