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drm/amd/powerplay: delete SMUM_SET_FIELD
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repeated defining in hwmgr.h

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Rex Zhu authored and Alex Deucher committed Sep 26, 2017
1 parent f0f6e37 commit 9517586
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Showing 2 changed files with 6 additions and 11 deletions.
5 changes: 0 additions & 5 deletions drivers/gpu/drm/amd/powerplay/inc/smumgr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -170,11 +170,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
#define SMUM_READ_FIELD(device, reg, field) \
SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)

#define SMUM_SET_FIELD(value, reg, field, field_val) \
(((value) & ~SMUM_FIELD_MASK(reg, field)) | \
(SMUM_FIELD_MASK(reg, field) & ((field_val) << \
SMUM_FIELD_SHIFT(reg, field))))

#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field)
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12 changes: 6 additions & 6 deletions drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -191,17 +191,17 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
/* Disable MEC parsing/prefetching */
tmp = cgs_read_register(hwmgr->device,
mmCP_MEC_CNTL);
tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);

tmp = cgs_read_register(hwmgr->device,
mmCP_CPC_IC_BASE_CNTL);

tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);

reg_data = smu_lower_32_bits(info.mc_addr) &
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