From 09277e4fc9a62992839bf59684ef86910e1f4557 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Thu, 10 Oct 2024 14:19:43 +0800 Subject: [PATCH 1/2] dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property Per the RMII specification, the REF_CLK is sourced from MAC to PHY or from an external source. But for TJA11xx PHYs, they support to output a 50MHz RMII reference clock on REF_CLK pin. Previously the "nxp,rmii-refclk-in" was added to indicate that in RMII mode, if this property present, REF_CLK is input to the PHY, otherwise it is output. This seems inappropriate now. Because according to the RMII specification, the REF_CLK is originally input, so there is no need to add an additional "nxp,rmii-refclk-in" property to declare that REF_CLK is input. Unfortunately, because the "nxp,rmii-refclk-in" property has been added for a while, and we cannot confirm which DTS use the TJA1100 and TJA1101 PHYs, changing it to switch polarity will cause an ABI break. But fortunately, this property is only valid for TJA1100 and TJA1101. For TJA1103/TJA1104/TJA1120/TJA1121 PHYs, this property is invalid because they use the nxp-c45-tja11xx driver, which is a different driver from TJA1100/TJA1101. Therefore, for PHYs using nxp-c45-tja11xx driver, add "nxp,rmii-refclk-out" property to support outputting RMII reference clock on REF_CLK pin. Signed-off-by: Wei Fang Reviewed-by: Rob Herring (Arm) Signed-off-by: Paolo Abeni --- .../devicetree/bindings/net/nxp,tja11xx.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml index a754a61adc2df..5f9f7efff5383 100644 --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml @@ -62,6 +62,22 @@ allOf: reference clock output when RMII mode enabled. Only supported on TJA1100 and TJA1101. + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id001b.b010 + - ethernet-phy-id001b.b013 + - ethernet-phy-id001b.b030 + - ethernet-phy-id001b.b031 + + then: + properties: + nxp,rmii-refclk-out: + type: boolean + description: Enable 50MHz RMII reference clock output on REF_CLK pin. + patternProperties: "^ethernet-phy@[0-9a-f]+$": type: object From 6d8d89873ae075bf73f17af2bad109da90fd017f Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Thu, 10 Oct 2024 14:19:44 +0800 Subject: [PATCH 2/2] net: phy: c45-tja11xx: add support for outputting RMII reference clock For TJA11xx PHYs, they have the capability to output 50MHz reference clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in the PHY data sheet. Signed-off-by: Wei Fang Signed-off-by: Paolo Abeni --- drivers/net/phy/nxp-c45-tja11xx.c | 30 +++++++++++++++++++++++++++++- drivers/net/phy/nxp-c45-tja11xx.h | 1 + 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index 5af5ade4fc641..7e328c2a29a49 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -185,6 +186,8 @@ #define NXP_C45_SKB_CB(skb) ((struct nxp_c45_skb_cb *)(skb)->cb) +#define TJA11XX_REVERSE_MODE BIT(0) + struct nxp_c45_phy; struct nxp_c45_skb_cb { @@ -1510,6 +1513,8 @@ static int nxp_c45_get_delays(struct phy_device *phydev) static int nxp_c45_set_phy_mode(struct phy_device *phydev) { + struct nxp_c45_phy *priv = phydev->priv; + u16 basic_config; int ret; ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); @@ -1561,8 +1566,15 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev) phydev_err(phydev, "rmii mode not supported\n"); return -EINVAL; } + + basic_config = MII_BASIC_CONFIG_RMII; + + /* This is not PHY_INTERFACE_MODE_REVRMII */ + if (priv->flags & TJA11XX_REVERSE_MODE) + basic_config |= MII_BASIC_CONFIG_REV; + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, - MII_BASIC_CONFIG_RMII); + basic_config); break; case PHY_INTERFACE_MODE_SGMII: if (!(ret & SGMII_ABILITY)) { @@ -1623,6 +1635,20 @@ static int nxp_c45_get_features(struct phy_device *phydev) return genphy_c45_pma_read_abilities(phydev); } +static int nxp_c45_parse_dt(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + struct nxp_c45_phy *priv = phydev->priv; + + if (!IS_ENABLED(CONFIG_OF_MDIO)) + return 0; + + if (of_property_read_bool(node, "nxp,rmii-refclk-out")) + priv->flags |= TJA11XX_REVERSE_MODE; + + return 0; +} + static int nxp_c45_probe(struct phy_device *phydev) { struct nxp_c45_phy *priv; @@ -1642,6 +1668,8 @@ static int nxp_c45_probe(struct phy_device *phydev) phydev->priv = priv; + nxp_c45_parse_dt(phydev); + mutex_init(&priv->ptp_lock); phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, diff --git a/drivers/net/phy/nxp-c45-tja11xx.h b/drivers/net/phy/nxp-c45-tja11xx.h index f364fca68f0be..8b5fc383752bc 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.h +++ b/drivers/net/phy/nxp-c45-tja11xx.h @@ -28,6 +28,7 @@ struct nxp_c45_phy { int extts_index; bool extts; struct nxp_c45_macsec *macsec; + u32 flags; }; #if IS_ENABLED(CONFIG_MACSEC)