From a1328374d81b20700909f3dfcd337b13702568d8 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 14 Jan 2025 19:19:48 +0100 Subject: [PATCH] clk: stm32f4: use FIELD helpers to access the PLLCFGR fields Use GENMASK() along with FIELD_GET() and FIELD_PREP() helpers to access the PLLCFGR fields instead of manually masking and shifting. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/r/20250114182021.670435-4-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-stm32f4.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 07c13ebe327d5..db1c56c8d54fe 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -5,6 +5,7 @@ * Inspired by clk-asm9260.c . */ +#include #include #include #include @@ -39,6 +40,8 @@ #define STM32F4_RCC_DCKCFGR 0x8c #define STM32F7_RCC_DCKCFGR2 0x90 +#define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6) + #define NONE -1 #define NO_IDX NONE #define NO_MUX NONE @@ -632,9 +635,11 @@ static unsigned long stm32f4_pll_recalc(struct clk_hw *hw, { struct clk_gate *gate = to_clk_gate(hw); struct stm32f4_pll *pll = to_stm32f4_pll(gate); + unsigned long val; unsigned long n; - n = (readl(base + pll->offset) >> 6) & 0x1ff; + val = readl(base + pll->offset); + n = FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); return parent_rate * n; } @@ -673,9 +678,10 @@ static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, n = rate / parent_rate; - val = readl(base + pll->offset) & ~(0x1ff << 6); + val = readl(base + pll->offset) & ~STM32F4_RCC_PLLCFGR_N_MASK; + val |= FIELD_PREP(STM32F4_RCC_PLLCFGR_N_MASK, n); - writel(val | ((n & 0x1ff) << 6), base + pll->offset); + writel(val, base + pll->offset); if (pll_state) stm32f4_pll_enable(hw);