Skip to content

Commit

Permalink
rtw89: phy: handle txpwr lmt/lmt_ru of 6G band
Browse files Browse the repository at this point in the history 
Add declarations of 6G stuff and extend rtw89_channel_to_idx() to
map 6G's channels to 6G channel indexes. While 6G, correspondingly
read 6G's entry for tx power limit and limit_ru.

After this, we should pay attention to chip_info::support_bands.
If a chip declares 6G support, it must configure txpwr_lmt_6g and
txpwr_lmt_ru_6g in case accessing NULL pointer while setting tx power
limit/limit_ru on 6G band.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220218034017.9160-2-pkshih@realtek.com
  • Loading branch information
Zong-Zhe Yang authored and Kalle Valo committed Feb 22, 2022
1 parent e035257 commit ac74f01
Show file tree
Hide file tree
Showing 2 changed files with 68 additions and 3 deletions.
25 changes: 25 additions & 0 deletions drivers/net/wireless/realtek/rtw89/core.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -371,6 +371,25 @@ enum rtw89_hw_rate {
*/
#define RTW89_5G_CH_NUM 53

/* 6G channels,
* 1, 3, 5, 7, 9, 11, 13, 15,
* 17, 19, 21, 23, 25, 27, 29, 33,
* 35, 37, 39, 41, 43, 45, 47, 49,
* 51, 53, 55, 57, 59, 61, 65, 67,
* 69, 71, 73, 75, 77, 79, 81, 83,
* 85, 87, 89, 91, 93, 97, 99, 101,
* 103, 105, 107, 109, 111, 113, 115, 117,
* 119, 121, 123, 125, 129, 131, 133, 135,
* 137, 139, 141, 143, 145, 147, 149, 151,
* 153, 155, 157, 161, 163, 165, 167, 169,
* 171, 173, 175, 177, 179, 181, 183, 185,
* 187, 189, 193, 195, 197, 199, 201, 203,
* 205, 207, 209, 211, 213, 215, 217, 219,
* 221, 225, 227, 229, 231, 233, 235, 237,
* 239, 241, 243, 245, 247, 249, 251, 253,
*/
#define RTW89_6G_CH_NUM 120

enum rtw89_rate_section {
RTW89_RS_CCK,
RTW89_RS_OFDM,
Expand Down Expand Up @@ -554,6 +573,7 @@ enum rtw89_ps_mode {

#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1)
#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1)

enum rtw89_ru_bandwidth {
Expand Down Expand Up @@ -2246,10 +2266,15 @@ struct rtw89_chip_info {
const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
[RTW89_REGD_NUM][RTW89_5G_CH_NUM];
const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
[RTW89_REGD_NUM][RTW89_6G_CH_NUM];
const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]
[RTW89_REGD_NUM][RTW89_2G_CH_NUM];
const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]
[RTW89_REGD_NUM][RTW89_5G_CH_NUM];
const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM]
[RTW89_REGD_NUM][RTW89_6G_CH_NUM];

u8 txpwr_factor_rf;
u8 txpwr_factor_mac;
Expand Down
46 changes: 43 additions & 3 deletions drivers/net/wireless/realtek/rtw89/phy.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1115,8 +1115,36 @@ s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
}
EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);

static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel)
static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
{
switch (channel_6g) {
case 1 ... 29:
return (channel_6g - 1) / 2;
case 33 ... 61:
return (channel_6g - 3) / 2;
case 65 ... 93:
return (channel_6g - 5) / 2;
case 97 ... 125:
return (channel_6g - 7) / 2;
case 129 ... 157:
return (channel_6g - 9) / 2;
case 161 ... 189:
return (channel_6g - 11) / 2;
case 193 ... 221:
return (channel_6g - 13) / 2;
case 225 ... 253:
return (channel_6g - 15) / 2;
default:
rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
return 0;
}
}

static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
{
if (band == RTW89_BAND_6G)
return rtw89_channel_6g_to_idx(rtwdev, channel);

switch (channel) {
case 1 ... 14:
return channel - 1;
Expand All @@ -1136,8 +1164,8 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch);
u8 band = rtwdev->hal.current_band_type;
u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
u8 regd = rtw89_regd_get(rtwdev, band);
s8 lmt = 0, sar;

Expand All @@ -1154,6 +1182,12 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf]
[RTW89_WW][ch_idx];
break;
case RTW89_BAND_6G:
lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx];
if (!lmt)
lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf]
[RTW89_WW][ch_idx];
break;
default:
rtw89_warn(rtwdev, "unknown band type: %d\n", band);
return 0;
Expand Down Expand Up @@ -1269,8 +1303,8 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,
u8 ru, u8 ntx, u8 ch)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch);
u8 band = rtwdev->hal.current_band_type;
u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
u8 regd = rtw89_regd_get(rtwdev, band);
s8 lmt_ru = 0, sar;

Expand All @@ -1287,6 +1321,12 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,
lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx]
[RTW89_WW][ch_idx];
break;
case RTW89_BAND_6G:
lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx];
if (!lmt_ru)
lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx]
[RTW89_WW][ch_idx];
break;
default:
rtw89_warn(rtwdev, "unknown band type: %d\n", band);
return 0;
Expand Down

0 comments on commit ac74f01

Please sign in to comment.