From 7f061c19f6521ef2b3e6f784ae344ebb562a5343 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 10:13:58 +0100 Subject: [PATCH 1/4] dt-bindings: arm-smmu: Add compatible for SM8550 SoC Add the SoC specific compatible for SM8550 implementing arm,mmu-500. Signed-off-by: Abel Vesa Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230207-topic-sm8550-upstream-smmu-bindings-v3-1-cb15a7123cfe@linaro.org Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 807cb511fe186..ea81e9b1860cf 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -53,6 +53,7 @@ properties: - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 - const: qcom,smmu-500 - const: arm,mmu-500 @@ -389,6 +390,7 @@ allOf: - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 then: properties: clock-names: false From 5c3686616b1840b3143b227eb58fb1c1621d204e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 17:44:16 +0100 Subject: [PATCH 2/4] dt-bindings: arm-smmu: Use qcom,smmu compatible for MMU500 adreno SMMUs qcom,smmu-500 was introduced to prevent people from adding new compatibles for what seems to roughly be the same hardware. Use it for qcom,adreno-smmu-compatible targets as well. While at it, fix the "arm,smmu-500" -> "arm,mmu-500" typo in the comment. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230313-topic-gpu_smmu_bindings-v3-1-66ab655fbfd5@linaro.org Signed-off-by: Will Deacon --- .../devicetree/bindings/iommu/arm,smmu.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ea81e9b1860cf..b3a8f58646481 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -76,9 +76,19 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - const: arm,mmu-500 - - - description: Qcom Adreno GPUs implementing "arm,smmu-500" + - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" + items: + - enum: + - qcom,sc7280-smmu-500 + - qcom,sm8150-smmu-500 + - qcom,sm8250-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) + deprecated: true items: + # Do not add additional SoC to this list. Instead use previous list. - enum: - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 From 16d1646871fbe800c9751f0816a970f9126a6586 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 17:44:17 +0100 Subject: [PATCH 3/4] dt-bindings: arm-smmu: Add SM8350 Adreno SMMU Document the Adreno SMMU present on SM8350. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230313-topic-gpu_smmu_bindings-v3-2-66ab655fbfd5@linaro.org Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index b3a8f58646481..f45e4296a5eaf 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -82,6 +82,7 @@ properties: - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 + - qcom,sm8350-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 From 3ad6585509dc8157e598dbd06b71efed2e45fee8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:52:08 +0100 Subject: [PATCH 4/4] dt-bindings: arm-smmu: Document SM61[12]5 GPU SMMU Both of these SoCs have a Qualcomm MMU500 implementation of SMMU in front of their GPUs that expect 3 clocks. Both of them also have an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500 from the "no clocks" list (intentionally 'breaking' the schema checks of APPS SMMU, as now it *can* accept clocks - with the current structure of this file it would have taken a wastefully-long time to sort this out properly..) and add necessary yaml to describe the clocks required by the GPU SMMUs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230315-topic-kamorta_adrsmmu-v1-1-d1c0dea90bd9@linaro.org Signed-off-by: Will Deacon --- .../devicetree/bindings/iommu/arm,smmu.yaml | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index f45e4296a5eaf..ba677d401e240 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -80,6 +80,8 @@ properties: items: - enum: - qcom,sc7280-smmu-500 + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -376,6 +378,30 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + items: + - enum: + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: + properties: + clock-names: + items: + - const: mem + - const: hlos + - const: iface + + clocks: + items: + - description: GPU memory bus clock + - description: Voter clock required for HLOS SMMU access + - description: Interface clock required for register access + # Disallow clocks for all other platforms with specific compatibles - if: properties: @@ -395,8 +421,6 @@ allOf: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - - qcom,sm6115-smmu-500 - - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500