From cc1966a7e0844922c463e06a61d4ef60aa2644b9 Mon Sep 17 00:00:00 2001
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: Wed, 5 May 2021 14:17:36 +0200
Subject: [PATCH] staging: mt7621-dts: properly organize pcie node
Device tree pcie node for this SoC is using different
styles in its different properties. Hence properly
unify them to be able to write a a proper yaml schema
documentation.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210505121736.6459-11-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index fadc76fdcaf1e..5759ba8742ca4 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -484,10 +484,10 @@
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e140000 0x100 /* host-pci bridge registers */
- 0x1e142000 0x100 /* pcie port 0 RC control registers */
- 0x1e143000 0x100 /* pcie port 1 RC control registers */
- 0x1e144000 0x100>; /* pcie port 2 RC control registers */
+ reg = <0x1e140000 0x100>, /* host-pci bridge registers */
+ <0x1e142000 0x100>, /* pcie port 0 RC control registers */
+ <0x1e143000 0x100>, /* pcie port 1 RC control registers */
+ <0x1e144000 0x100>; /* pcie port 2 RC control registers */
#address-cells = <3>;
#size-cells = <2>;
@@ -497,10 +497,8 @@
device_type = "pci";
bus-range = <0 255>;
- ranges = <
- 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
- 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
- >;
+ ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
+ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
#interrupt-cells = <1>;
interrupt-map-mask = <0xF800 0 0 0>;
@@ -510,7 +508,7 @@
status = "disabled";
- resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
+ resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
reset-names = "pcie0", "pcie1", "pcie2";
clocks = <&sysc MT7621_CLK_PCIE0>,
<&sysc MT7621_CLK_PCIE1>,