From cf1ba3cb245020459f2ca446b7a7b199839f5d83 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 6 Mar 2025 12:40:01 +0300 Subject: [PATCH] spi: spi-qpic-snand: Fix ECC_CFG_ECC_DISABLE shift in qcom_spi_read_last_cw() The ECC_CFG_ECC_DISABLE define is BIT(0). It's supposed to be used directly instead of used as a shifter. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") Signed-off-by: Dan Carpenter Link: https://patch.msgid.link/2f4b0a0b-2c03-41c0-8a4a-3d789a83832d@stanley.mountain Signed-off-by: Mark Brown --- drivers/spi/spi-qpic-snand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index 8c413a6a5152..ffb2b6ec685c 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -514,7 +514,7 @@ static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc, cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) | 0 << CW_PER_PAGE; cfg1 = ecc_cfg->cfg1_raw; - ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; + ecc_bch_cfg = ECC_CFG_ECC_DISABLE; snandc->regs->cmd = snandc->qspi->cmd; snandc->regs->cfg0 = cpu_to_le32(cfg0);