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drm/amd/powerplay: show uvd/vce power gate enablement for tonga.
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Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Rex Zhu authored and Alex Deucher committed Mar 17, 2016
1 parent 66f4854 commit d27d494
Showing 1 changed file with 3 additions and 1 deletion.
4 changes: 3 additions & 1 deletion drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
Original file line number Diff line number Diff line change
Expand Up @@ -5170,14 +5170,16 @@ tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);


offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
activity_percent += 0x80;
activity_percent >>= 8;

seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);

seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");

seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
}

static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
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