From d2995cb58390f874a9bd9f594d2a054d1d953645 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 20 Apr 2017 15:51:35 -0400 Subject: [PATCH] drm/amdgpu: Add GART size scaling for GFX9 Scale gart size with the system memory size, same as for older chip families. Change-Id: I070aa20cd88d73d7a75808f828a66bc147ebe271 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 37 ++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index df69aae99df48..2c68c129b2cfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -459,9 +459,40 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) /* unless the user had overridden it, set the gart * size equal to the 1024 or vram, whichever is larger. */ - if (amdgpu_gart_size == -1) - adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); - else + if (amdgpu_gart_size == -1) { + uint64_t gart_size_aligned; + struct sysinfo si; + + /* Maximum GTT size is limited by the GART table size + * in visible VRAM and the address space. Use at most + * half of each. + */ + uint64_t max_gtt_size = min( + adev->mc.visible_vram_size / 8 * PAGE_SIZE / 2, + 1ULL << 39); + + si_meminfo(&si); + /* Set the GART to map the largest size between either + * VRAM capacity or double the available physical RAM + */ + adev->mc.gtt_size = min( + max( + ((uint64_t)si.totalram * si.mem_unit * 2), + adev->mc.mc_vram_size + ), + max_gtt_size + ); + + /* GART sizes computed from physical RAM capacity + * may not always be perfect powers of two. + * Round up starting from the minimum size of 1GB. + */ + gart_size_aligned = 1024ULL << 20; + while (adev->mc.gtt_size > gart_size_aligned) + gart_size_aligned <<= 1; + + adev->mc.gtt_size = gart_size_aligned; + } else adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; gmc_v9_0_vram_gtt_location(adev, &adev->mc);