From bc2e65bfc5af404d44442fca6d8ae69657df1e11 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 6 Jun 2024 19:51:45 +0300 Subject: [PATCH 01/58] MIPS: Alchemy: Switch to use kmemdup_array() Let the kememdup_array() take care about multiplication and possible overflows. Signed-off-by: Andy Shevchenko Signed-off-by: Thomas Bogendoerfer --- arch/mips/alchemy/common/platform.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index d4ab34b3b404e..da74cae6b43a6 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -409,8 +409,8 @@ static void __init alchemy_setup_macs(int ctype) if (alchemy_get_macs(ctype) < 1) return; - macres = kmemdup(au1xxx_eth0_resources[ctype], - sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); + macres = kmemdup_array(au1xxx_eth0_resources[ctype], MAC_RES_COUNT, + sizeof(*macres), GFP_KERNEL); if (!macres) { printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n"); return; @@ -430,8 +430,8 @@ static void __init alchemy_setup_macs(int ctype) if (alchemy_get_macs(ctype) < 2) return; - macres = kmemdup(au1xxx_eth1_resources[ctype], - sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); + macres = kmemdup_array(au1xxx_eth1_resources[ctype], MAC_RES_COUNT, + sizeof(*macres), GFP_KERNEL); if (!macres) { printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n"); return; From 73d4bb58a3f6671255c9cb3960f2202da38bbc14 Mon Sep 17 00:00:00 2001 From: Celeste Liu Date: Thu, 30 May 2024 19:19:51 +0800 Subject: [PATCH 02/58] mips: defconfig: drop RT_GROUP_SCHED=y from generic/db1xxx/eyeq5 For cgroup v1, if turned on, and there's any cgroup in the "cpu" hierarchy it needs an RT budget assigned, otherwise the processes in it will not be able to get RT at all. The problem with RT group scheduling is that it requires the budget assigned but there's no way we could assign a default budget, since the values to assign are both upper and lower time limits, are absolute, and need to be sum up to < 1 for each individal cgroup. That means we cannot really come up with values that would work by default in the general case.[1] For cgroup v2, it's almost unusable as well. If it turned on, the cpu controller can only be enabled when all RT processes are in the root cgroup. But it will lose the benefits of cgroup v2 if all RT process were placed in the same cgroup. Red Hat, Gentoo, Arch Linux and Debian all disable it. systemd also doesn't support it.[2] [1]: https://bugzilla.redhat.com/show_bug.cgi?id=1229700 [2]: https://github.com/systemd/systemd/issues/13781#issuecomment-549164383 Signed-off-by: Celeste Liu Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/db1xxx_defconfig | 1 - arch/mips/configs/eyeq5_defconfig | 1 - arch/mips/configs/generic_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/mips/configs/db1xxx_defconfig b/arch/mips/configs/db1xxx_defconfig index b2d9253ff786f..6eff21ff15d54 100644 --- a/arch/mips/configs/db1xxx_defconfig +++ b/arch/mips/configs/db1xxx_defconfig @@ -12,7 +12,6 @@ CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y diff --git a/arch/mips/configs/eyeq5_defconfig b/arch/mips/configs/eyeq5_defconfig index c35c29a4d4795..3794707c95222 100644 --- a/arch/mips/configs/eyeq5_defconfig +++ b/arch/mips/configs/eyeq5_defconfig @@ -8,7 +8,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y diff --git a/arch/mips/configs/generic_defconfig b/arch/mips/configs/generic_defconfig index 071e2205c7ede..fa916407bdd44 100644 --- a/arch/mips/configs/generic_defconfig +++ b/arch/mips/configs/generic_defconfig @@ -5,7 +5,6 @@ CONFIG_IKCONFIG_PROC=y CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y From db1848a97d5c70ed39481e62c5657ed113cb6bf7 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 13 May 2024 20:34:15 +0200 Subject: [PATCH 03/58] dt-bindings: mips: Add bindings for a new Mobileye SoC EyeQ6H Add the yaml bindings for a new Mobileye SoC: EyeQ6H. Acked-by: Conor Dooley Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/mobileye.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml index 831975f6b479f..d60744550e466 100644 --- a/Documentation/devicetree/bindings/mips/mobileye.yaml +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml @@ -26,6 +26,11 @@ properties: - enum: - mobileye,eyeq5-epm5 - const: mobileye,eyeq5 + - description: Boards with Mobileye EyeQ6H SoC + items: + - enum: + - mobileye,eyeq6h-epm6 + - const: mobileye,eyeq6h additionalProperties: true From 12c03bd444c26786995db694b39c55c09a39ae6f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 13 May 2024 20:34:16 +0200 Subject: [PATCH 04/58] MIPS: mobileye: Add EyeQ6H device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EyeQ6H (or “High”) is an other SoC from Mobileye still based on the MIPS I6500 architecture as the EyeQ5. The 2 clusters of this SoC contains 4 cores which are capable of running 4 threads. Besides this, it features multiple controllers such as the classic UART, high speed I2C, SPI, as well as CAN-FD, PCIe Gen4, Octal/Quad SPI Flash interface, Gigabit Ethernet, MIPI CSI-2, MIPI DSI, and eMMC 5.1. It also includes a Hardware Security Module, Functional Safety Hardware, and video encoders and more. This commit provides the initial device tree files with support for UART, GPIO and pinctrl, as well as fixed clocked. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts | 22 +++++ .../dts/mobileye/eyeq6h-fixed-clocks.dtsi | 52 ++++++++++ arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi | 88 +++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 98 +++++++++++++++++++ 4 files changed, 260 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts create mode 100644 arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq6h.dtsi diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts b/arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts new file mode 100644 index 0000000000000..ebc0d363fbf82 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h-epm6.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2024 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq6h.dtsi" + +/ { + compatible = "mobileye,eyeq6-epm6", "mobileye,eyeq6"; + model = "Mobile EyeQ6H MP6 Evaluation board"; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x1 0x00000000 0x1 0x00000000>; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi new file mode 100644 index 0000000000000..5fa99e06fde7e --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +#include + +/ { + xtal: clock-30000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + }; + + pll_west: clock-2000000000-west { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_cpu: clock-2000000000-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + /* pll-cpu derivatives */ + occ_cpu: clock-2000000000-occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + + /* pll-west derivatives */ + occ_periph_w: clock-200000000 { + compatible = "fixed-factor-clock"; + clocks = <&pll_west>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + uart_clk: clock-200000000-uart { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph_w>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi new file mode 100644 index 0000000000000..a3d1b36848938 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h-pins.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2024 Mobileye Vision Technologies Ltd. + */ + +/* + * MUX register structure + * bits | field | comment + * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func + * [4] | SW_LOOPBACK| + * [5] | SW_OUT_HZ | + * [7] | DBG_IN | + * [11:8] | DS | drive strength + * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU + * [14] | OD | Open drain + * [15] | ST_CFG | Hysteretic input enable (Schmitt trigger) + */ + +&pinctrl_west { + // TODO: use pinctrl-single,bias-pullup + // TODO: use pinctrl-single,bias-pulldown + // TODO: use pinctrl-single,drive-strength + // TODO: use pinctrl-single,input-schmitt + + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + 0x000 0x200 // I2C0_SCL pin + 0x004 0x200 // I2C0_SDA pin + >; + }; + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + 0x008 0x200 // I2C1_SCL pin + 0x00c 0x200 // I2C1_SDA pin + >; + }; + eth0_pins: eth0-pins { + pinctrl-single,pins = < + 0x080 1 // GPIO_C4__SMA0_MDC pin + 0x084 1 // GPIO_C5__SMA0_MDIO pin + >; + }; + uart0_pins: uart0-pins { + pinctrl-single,pins = <0x0a8 1>; // UART0 pin group + }; + uart1_pins: uart1-pins { + pinctrl-single,pins = <0x0a0 1>; // UART1 pin group + }; + spi0_pins: spi0-pins { + pinctrl-single,pins = <0x0ac 1>; // SPI0 pin group + }; + spi1_pins: spi1-pins { + pinctrl-single,pins = <0x0a4 1>; // SPI1 pin group + }; +}; + +&pinctrl_east { + i2c2_pins: i2c2-pins { + pinctrl-single,pins = < + 0x000 0x200 // i2c2_SCL pin + 0x004 0x200 // i2c2_SDA pin + >; + }; + i2c3_pins: i2c3-pins { + pinctrl-single,pins = < + 0x008 0x200 // i2c3_SCL pin + 0x00c 0x200 // i2c3_SDA pin + >; + }; + eth1_pins: eth1-pins { + pinctrl-single,pins = < + 0x080 1 // GPIO_D4__SMA1_MDC pin + 0x084 1 // GPIO_D5__SMA1_MDIO pin + >; + }; + uart2_sel_pins: uart2-pins { + pinctrl-single,pins = <0x0a4 1>; // UART2 pin group + }; + uart3_pins: uart3-pins { + pinctrl-single,pins = <0x09c 1>; // UART3 pin group + }; + spi2_pins: spi2-pins { + pinctrl-single,pins = <0x0a8 1>; // SPI2 pin group + }; + spi3_pins: spi3-pins { + pinctrl-single,pins = <0x0a0 1>; // SPI3 pin group + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi new file mode 100644 index 0000000000000..1db3c3cda2e39 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright 2024 Mobileye Vision Technologies Ltd. + */ + +#include + +#include "eyeq6h-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&occ_cpu>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@d3331000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xd3331000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&occ_periph_w>, <&occ_periph_w>; + clock-names = "uartclk", "apb_pclk"; + }; + + pinctrl_west: pinctrl@d3337000 { + compatible = "pinctrl-single"; + reg = <0x0 0xd3337000 0x0 0xb0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffff>; + }; + + pinctrl_east: pinctrl@d3357000 { + compatible = "pinctrl-single"; + reg = <0x0 0xd3357000 0x0 0xb0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffff>; + }; + + pinctrl_south: pinctrl@d8014000 { + compatible = "pinctrl-single"; + reg = <0x0 0xd8014000 0x0 0xf8>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffff>; + }; + + gic: interrupt-controller@f0920000 { + compatible = "mti,gic"; + reg = <0x0 0xf0920000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&occ_cpu>; + }; + }; + }; +}; + +#include "eyeq6h-pins.dtsi" From fbe0fae601b780622fcb7034a479fa161645b9f4 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 13 May 2024 20:34:17 +0200 Subject: [PATCH 05/58] MIPS: mobileye: Add EyeQ6H support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EyeQ6H (or “High”) is an other SoC from Mobileye still based on the MIPS I6500 architecture as the EyeQ5. The 2 clusters of this SoC contains 4 cores which are capable of running 4 threads. Besides this, it features multiple controllers such as the classic UART, high speed I2C, SPI, as well as CAN-FD, PCIe Gen4, Octal/Quad SPI Flash interface, Gigabit Ethernet, MIPI CSI-2, MIPI DSI, and eMMC 5.1. It also includes a Hardware Security Module, Functional Safety Hardware, and video encoders and more. This commit provides the infrastructure to build a kernel running on EyeQ6H SoC. For now the support is limited and only one CPU core is running. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kbuild.platforms | 2 +- arch/mips/Kconfig | 7 +- arch/mips/boot/dts/Makefile | 2 +- arch/mips/boot/dts/mobileye/Makefile | 1 + arch/mips/configs/eyeq5_defconfig | 1 + arch/mips/configs/eyeq6_defconfig | 111 +++++++++++++++++++++++++++ arch/mips/mobileye/Kconfig | 26 +++++++ arch/mips/mobileye/Platform | 1 + 8 files changed, 146 insertions(+), 5 deletions(-) create mode 100644 arch/mips/configs/eyeq6_defconfig create mode 100644 arch/mips/mobileye/Kconfig diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5c145b67d3bf4..bca37ddf974b8 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -8,6 +8,7 @@ platform-$(CONFIG_BCM47XX) += bcm47xx/ platform-$(CONFIG_BCM63XX) += bcm63xx/ platform-$(CONFIG_BMIPS_GENERIC) += bmips/ platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/ +platform-$(CONFIG_EYEQ) += mobileye/ platform-$(CONFIG_MIPS_COBALT) += cobalt/ platform-$(CONFIG_MACH_DECSTATION) += dec/ platform-$(CONFIG_MIPS_GENERIC) += generic/ @@ -17,7 +18,6 @@ platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ -platform-$(CONFIG_MACH_EYEQ5) += mobileye/ platform-$(CONFIG_MACH_NINTENDO64) += n64/ platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_RALINK) += ralink/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f1aa1bf11166b..ab7bd7315334e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -575,8 +575,8 @@ config MACH_PIC32 Microchip PIC32 is a family of general-purpose 32 bit MIPS core microcontrollers. -config MACH_EYEQ5 - bool "Mobileye EyeQ5 SoC" +config EYEQ + bool "Mobileye EyeQ SoC" select MACH_GENERIC_CORE select ARM_AMBA select PHYSICAL_START_BOOL @@ -615,7 +615,7 @@ config MACH_EYEQ5 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN select USE_OF help - Select this to build a kernel supporting EyeQ5 SoC from Mobileye. + Select this to build a kernel supporting EyeQ SoC from Mobileye. bool @@ -1021,6 +1021,7 @@ source "arch/mips/generic/Kconfig" source "arch/mips/ingenic/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lantiq/Kconfig" +source "arch/mips/mobileye/Kconfig" source "arch/mips/pic32/Kconfig" source "arch/mips/ralink/Kconfig" source "arch/mips/sgi-ip27/Kconfig" diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index efff87cb33a9e..e2476b12bb0c8 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-$(CONFIG_BMIPS_GENERIC) += brcm subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon +subdir-$(CONFIG_EYEQ) += mobileye subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img subdir-$(CONFIG_MACH_INGENIC) += ingenic @@ -8,7 +9,6 @@ subdir-$(CONFIG_LANTIQ) += lantiq subdir-$(CONFIG_MACH_LOONGSON64) += loongson subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti -subdir-$(CONFIG_MACH_EYEQ5) += mobileye subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile index 01c01c3aad81d..7cc89968aaacd 100644 --- a/arch/mips/boot/dts/mobileye/Makefile +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -2,3 +2,4 @@ # Copyright 2023 Mobileye Vision Technologies Ltd. dtb-$(CONFIG_MACH_EYEQ5) += eyeq5-epm5.dtb +dtb-$(CONFIG_MACH_EYEQ6H) += eyeq6h-epm6.dtb diff --git a/arch/mips/configs/eyeq5_defconfig b/arch/mips/configs/eyeq5_defconfig index 3794707c95222..ae9a09b16e40b 100644 --- a/arch/mips/configs/eyeq5_defconfig +++ b/arch/mips/configs/eyeq5_defconfig @@ -18,6 +18,7 @@ CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y +CONFIG_EYEQ=y CONFIG_MACH_EYEQ5=y CONFIG_FIT_IMAGE_FDT_EPM5=y CONFIG_PAGE_SIZE_16KB=y diff --git a/arch/mips/configs/eyeq6_defconfig b/arch/mips/configs/eyeq6_defconfig new file mode 100644 index 0000000000000..6597d5e88b335 --- /dev/null +++ b/arch/mips/configs/eyeq6_defconfig @@ -0,0 +1,111 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_TASKSTATS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_EYEQ=y +CONFIG_MACH_EYEQ6H=y +CONFIG_MIPS_CPS=y +CONFIG_CPU_HAS_MSA=y +CONFIG_NR_CPUS=16 +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_JUMP_LABEL=y +CONFIG_PAGE_SIZE_16KB=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_TRIM_UNUSED_KSYMS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_USERFAULTFD=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NETFILTER=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_ENDPOINT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_SCSI=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_IPVLAN=y +CONFIG_MACB=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_CAN_M_CAN=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_MFD_SYSCON=y +CONFIG_HID_A4TECH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_NVMEM is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CRYPTO_CRC32_MIPS=y +CONFIG_FRAME_WARN=1024 +CONFIG_DEBUG_FS=y +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="earlycon" diff --git a/arch/mips/mobileye/Kconfig b/arch/mips/mobileye/Kconfig new file mode 100644 index 0000000000000..f9abb2d6e1787 --- /dev/null +++ b/arch/mips/mobileye/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0 +if EYEQ + +choice + prompt "Mobileye EyeQ SoC selection" + default MACH_EYEQ5 + help + Select Mobileye EyeQ MIPS SoC type. + + config MACH_EYEQ5 + bool "Mobileye EyeQ5 SoC" + + config MACH_EYEQ6H + bool "Mobileye EyeQ6H SoC" +endchoice + +config FIT_IMAGE_FDT_EPM5 + bool "Include FDT for Mobileye EyeQ5 development platforms" + depends on MACH_EYEQ5 + default n + help + Enable this to include the FDT for the EyeQ5 development platforms + from Mobileye in the FIT kernel image. + This requires u-boot on the platform. + +endif diff --git a/arch/mips/mobileye/Platform b/arch/mips/mobileye/Platform index c69f811dd13af..69f775bbbb1e1 100644 --- a/arch/mips/mobileye/Platform +++ b/arch/mips/mobileye/Platform @@ -9,6 +9,7 @@ # load-$(CONFIG_MACH_EYEQ5) = 0xa800000808000000 +load-$(CONFIG_MACH_EYEQ6H) = 0xa800000100800000 all-$(CONFIG_MACH_EYEQ5) += vmlinux.gz.itb its-y := vmlinux.its.S From e6dc7bc55a83c39bc81a1f6faff8631e05f7ff75 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 3 Apr 2024 12:56:25 +0200 Subject: [PATCH 06/58] mips: configs: ci20: Enable DRM_DW_HDMI Commit 4fc8cb47fcfd ("drm/display: Move HDMI helpers into display-helper module") turned the DRM_DW_HDMI dependency of DRM_INGENIC_DW_HDMI into a depends on which ended up disabling the drivers in the defconfig. Make sure it's still enabled. Fixes: 4fc8cb47fcfd ("drm/display: Move HDMI helpers into display-helper module") Reported-by: Mark Brown Reported-by: Alexander Stein Signed-off-by: Maxime Ripard Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/ci20_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 7827b2b392f67..90536cab417ee 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -122,6 +122,7 @@ CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m CONFIG_DRM=m CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_DW_HDMI=m CONFIG_DRM_INGENIC=m CONFIG_DRM_INGENIC_DW_HDMI=m CONFIG_FB=y From 16c6d88f14a8ddaec9f093e7eb94f57c45826a82 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 16:21:59 +0100 Subject: [PATCH 07/58] MIPS: asm/pm.h: Use platform agnostic macros Use platform agnostic macros so it can be compiled on all MIPS platforms. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pm.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/pm.h b/arch/mips/include/asm/pm.h index 10bb7b6407383..7ecd4dfe38461 100644 --- a/arch/mips/include/asm/pm.h +++ b/arch/mips/include/asm/pm.h @@ -17,7 +17,7 @@ /* Save CPU state to stack for suspend to RAM */ .macro SUSPEND_SAVE_REGS - subu sp, PT_SIZE + PTR_SUBU sp, PT_SIZE /* Call preserved GPRs */ LONG_S $16, PT_R16(sp) LONG_S $17, PT_R17(sp) @@ -56,13 +56,13 @@ LONG_L $31, PT_R31(sp) /* Pop and return */ jr ra - addiu sp, PT_SIZE + PTR_ADDIU sp, PT_SIZE .set pop .endm /* Get address of static suspend state into t1 */ .macro LA_STATIC_SUSPEND - la t1, mips_static_suspend_state + PTR_LA t1, mips_static_suspend_state .endm /* Save important CPU state for early restoration to global data */ @@ -72,11 +72,11 @@ * Segment configuration is saved in global data where it can be easily * reloaded without depending on the segment configuration. */ - mfc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ + mfc0 k0, CP0_SEGCTL0 LONG_S k0, SSS_SEGCTL0(t1) - mfc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ + mfc0 k0, CP0_SEGCTL1 LONG_S k0, SSS_SEGCTL1(t1) - mfc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ + mfc0 k0, CP0_SEGCTL2 LONG_S k0, SSS_SEGCTL2(t1) #endif /* save stack pointer (pointing to GPRs) */ @@ -92,11 +92,11 @@ * segments. */ LONG_L k0, SSS_SEGCTL0(t1) - mtc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ + mtc0 k0, CP0_SEGCTL0 LONG_L k0, SSS_SEGCTL1(t1) - mtc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ + mtc0 k0, CP0_SEGCTL1 LONG_L k0, SSS_SEGCTL2(t1) - mtc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ + mtc0 k0, CP0_SEGCTL2 tlbw_use_hazard #endif /* restore stack pointer (pointing to GPRs) */ @@ -105,10 +105,10 @@ /* flush caches to make sure context has reached memory */ .macro SUSPEND_CACHE_FLUSH - .extern __wback_cache_all + .extern __flush_cache_all .set push .set noreorder - la t1, __wback_cache_all + PTR_LA t1, __flush_cache_all LONG_L t0, 0(t1) jalr t0 nop From 2226d454db931455018521db13ab763d276952a7 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 16:22:00 +0100 Subject: [PATCH 08/58] MIPS: select CPU_PM with SUSPEND Functionalities provided by CPU_PM are essential for suspend to work on all platforms. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ab7bd7315334e..1236ea1220612 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -30,7 +30,7 @@ config MIPS select BUILDTIME_TABLE_SORT select CLONE_BACKWARDS select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1) - select CPU_PM if CPU_IDLE + select CPU_PM if CPU_IDLE || SUSPEND select GENERIC_ATOMIC64 if !64BIT select GENERIC_CMOS_UPDATE select GENERIC_CPU_AUTOPROBE From 68557c59a550c6afff714e54709e9c5511f39135 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 16:22:01 +0100 Subject: [PATCH 09/58] MIPS: Loongson64: Implement PM suspend for LEFI firmware Implement PM suspend for LEFI firmware. Entering STR (Suspend to RAM) is as simple as save our context then go to a firmware vector. Wake is a little bit treaky as we need to setup some CP0 status first, which can be done with smp_slave_setup. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/Makefile | 2 +- arch/mips/loongson64/pm.c | 88 +++++++--------------------------- arch/mips/loongson64/sleeper.S | 17 +++++++ 3 files changed, 36 insertions(+), 71 deletions(-) create mode 100644 arch/mips/loongson64/sleeper.S diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index e806280bbb850..cbba30dfddf5d 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o dma.o \ obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_NUMA) += numa.o obj-$(CONFIG_RS780_HPET) += hpet.o -obj-$(CONFIG_SUSPEND) += pm.o +obj-$(CONFIG_SUSPEND) += pm.o sleeper.o obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o obj-$(CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION) += cpucfg-emul.o obj-$(CONFIG_SYSFS) += boardinfo.o diff --git a/arch/mips/loongson64/pm.c b/arch/mips/loongson64/pm.c index 7c8556f097812..5f0604af8f136 100644 --- a/arch/mips/loongson64/pm.c +++ b/arch/mips/loongson64/pm.c @@ -6,98 +6,46 @@ * Author: Wu Zhangjin */ #include -#include #include -#include #include #include -static unsigned int __maybe_unused cached_master_mask; /* i8259A */ -static unsigned int __maybe_unused cached_slave_mask; -static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */ +asmlinkage void loongson_lefi_sleep(unsigned long sleep_addr); -void arch_suspend_disable_irqs(void) +static int lefi_pm_enter(suspend_state_t state) { - /* disable all mips events */ - local_irq_disable(); - -#ifdef CONFIG_I8259 - /* disable all events of i8259A */ - cached_slave_mask = inb(PIC_SLAVE_IMR); - cached_master_mask = inb(PIC_MASTER_IMR); - - outb(0xff, PIC_SLAVE_IMR); - inb(PIC_SLAVE_IMR); - outb(0xff, PIC_MASTER_IMR); - inb(PIC_MASTER_IMR); -#endif - /* disable all events of bonito */ - cached_bonito_irq_mask = LOONGSON_INTEN; - LOONGSON_INTENCLR = 0xffff; - (void)LOONGSON_INTENCLR; -} - -void arch_suspend_enable_irqs(void) -{ - /* enable all mips events */ - local_irq_enable(); -#ifdef CONFIG_I8259 - /* only enable the cached events of i8259A */ - outb(cached_slave_mask, PIC_SLAVE_IMR); - outb(cached_master_mask, PIC_MASTER_IMR); -#endif - /* enable all cached events of bonito */ - LOONGSON_INTENSET = cached_bonito_irq_mask; - (void)LOONGSON_INTENSET; -} - -/* - * Setup the board-specific events for waking up loongson from wait mode - */ -void __weak setup_wakeup_events(void) -{ -} - -void __weak mach_suspend(void) -{ -} - -void __weak mach_resume(void) -{ -} - -static int loongson_pm_enter(suspend_state_t state) -{ - mach_suspend(); - - mach_resume(); - - return 0; + switch (state) { + case PM_SUSPEND_MEM: + pm_set_suspend_via_firmware(); + loongson_lefi_sleep(loongson_sysconf.suspend_addr); + pm_set_resume_via_firmware(); + return 0; + default: + return -EINVAL; + } } -static int loongson_pm_valid_state(suspend_state_t state) +static int lefi_pm_valid_state(suspend_state_t state) { switch (state) { - case PM_SUSPEND_ON: - case PM_SUSPEND_STANDBY: case PM_SUSPEND_MEM: - return 1; - + return !!loongson_sysconf.suspend_addr; default: return 0; } } -static const struct platform_suspend_ops loongson_pm_ops = { - .valid = loongson_pm_valid_state, - .enter = loongson_pm_enter, +static const struct platform_suspend_ops lefi_pm_ops = { + .valid = lefi_pm_valid_state, + .enter = lefi_pm_enter, }; static int __init loongson_pm_init(void) { - suspend_set_ops(&loongson_pm_ops); + if (loongson_sysconf.fw_interface == LOONGSON_LEFI) + suspend_set_ops(&lefi_pm_ops); return 0; } diff --git a/arch/mips/loongson64/sleeper.S b/arch/mips/loongson64/sleeper.S new file mode 100644 index 0000000000000..04874b9bf430b --- /dev/null +++ b/arch/mips/loongson64/sleeper.S @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024, Jiaxun Yang + * Loongson EFI firmware sleeper routine + */ + +#include +#include + +#include + +LEAF(loongson_lefi_sleep) + SUSPEND_SAVE + jalr a0 + smp_slave_setup + RESUME_RESTORE_REGS_RETURN +END(loongson_lefi_sleep) From 4ba491dd3b0e8ac6e6f46b9a91f490b6dad21aa0 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 19:51:19 +0100 Subject: [PATCH 10/58] MIPS: kvm: Declare prototype for kvm_init_loongson_ipi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Declear prototype for kvm_init_loongson_ipi in interrupt.h. Fix warning: arch/mips/kvm/loongson_ipi.c:190:6: warning: no previous prototype for ‘kvm_init_loongson_ipi’ [-Wmissing-prototypes] 190 | void kvm_init_loongson_ipi(struct kvm *kvm) | ^~~~~~~~~~~~~~~~~~~~~ Fixes: f21db3090de2 ("KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support") Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/kvm/interrupt.h | 4 ++++ arch/mips/kvm/loongson_ipi.c | 2 ++ arch/mips/kvm/mips.c | 2 -- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/kvm/interrupt.h b/arch/mips/kvm/interrupt.h index e529ea2bb34b9..07bc0160bc943 100644 --- a/arch/mips/kvm/interrupt.h +++ b/arch/mips/kvm/interrupt.h @@ -37,3 +37,7 @@ u32 kvm_irq_to_priority(u32 irq); int kvm_mips_pending_timer(struct kvm_vcpu *vcpu); void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause); + +#ifdef CONFIG_CPU_LOONGSON64 +extern void kvm_init_loongson_ipi(struct kvm *kvm); +#endif diff --git a/arch/mips/kvm/loongson_ipi.c b/arch/mips/kvm/loongson_ipi.c index 5d53f32d837c1..6ac83a31148cb 100644 --- a/arch/mips/kvm/loongson_ipi.c +++ b/arch/mips/kvm/loongson_ipi.c @@ -10,6 +10,8 @@ #include +#include "interrupt.h" + #define IPI_BASE 0x3ff01000ULL #define CORE0_STATUS_OFF 0x000 diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c index 231ac052b506b..56fedfbe9455e 100644 --- a/arch/mips/kvm/mips.c +++ b/arch/mips/kvm/mips.c @@ -135,8 +135,6 @@ void kvm_arch_hardware_disable(void) kvm_mips_callbacks->hardware_disable(); } -extern void kvm_init_loongson_ipi(struct kvm *kvm); - int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) { switch (type) { From 40a48dd3bb85bcd795d37ef8129af7eca978d669 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 19:51:20 +0100 Subject: [PATCH 11/58] MIPS: Loongson64: Include bootinfo.h in dma.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dma.c defined function plat_swiotlb_setup, which is declared in bootinfo.h. Fixes warning: arch/mips/loongson64/dma.c:25:13: warning: no previous prototype for ‘plat_swiotlb_setup’ [-Wmissing-prototypes] 25 | void __init plat_swiotlb_setup(void) | ^~~~~~~~~~~~~~~~~~ Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/loongson64/dma.c b/arch/mips/loongson64/dma.c index 8220a1bc0db64..52801442ea86c 100644 --- a/arch/mips/loongson64/dma.c +++ b/arch/mips/loongson64/dma.c @@ -2,6 +2,7 @@ #include #include #include +#include #include dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) From 98a9e2ac3755a353eefea8c52e23d5b0c50f3899 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 19:51:21 +0100 Subject: [PATCH 12/58] MIPS: Loongson64: DTS: Fix msi node for ls7a Add it to silent warning: arch/mips/boot/dts/loongson/ls7a-pch.dtsi:68.16-416.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts:32.31-40.4: Warning (interrupt_provider): /bus@10000000/msi-controller@2ff00000: Missing '#interrupt-cells' in interrupt provider arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider' Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts index c945f8565d543..fb180cb2b8e2c 100644 --- a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts +++ b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts @@ -33,6 +33,7 @@ compatible = "loongson,pch-msi-1.0"; reg = <0 0x2ff00000 0 0x8>; interrupt-controller; + #interrupt-cells = <1>; msi-controller; loongson,msi-base-vec = <64>; loongson,msi-num-vecs = <192>; From d89a415ff8d5e0aad4963f2d8ebb0f9e8110b7fa Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 7 May 2024 19:51:22 +0100 Subject: [PATCH 13/58] MIPS: Loongson64: DTS: Fix PCIe port nodes for ls7a Add various required properties to silent warnings: arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi:116.16-297.5: Warning (interrupt_provider): /bus@10000000/pci@1a000000: '#interrupt-cells' found, but node is not an interrupt provider arch/mips/boot/dts/loongson/loongson64_2core_2k1000.dtb: Warning (interrupt_map): Failed prerequisite 'interrupt_provider' Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- .../boot/dts/loongson/loongson64-2k1000.dtsi | 37 +++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index ee3e2153dd13f..b5593f7cc383b 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -118,7 +118,6 @@ device_type = "pci"; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <2>; reg = <0 0x1a000000 0 0x02000000>, <0xfe 0x00000000 0 0x20000000>; @@ -204,93 +203,117 @@ interrupt-parent = <&liointc0>; }; - pci_bridge@9,0 { + pcie@9,0 { compatible = "pci0014,7a19.0", "pci0014,7a19", "pciclass060400", "pciclass0604"; reg = <0x4800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; #interrupt-cells = <1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>; + ranges; external-facing; }; - pci_bridge@a,0 { + pcie@a,0 { compatible = "pci0014,7a09.0", "pci0014,7a09", "pciclass060400", "pciclass0604"; reg = <0x5000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; #interrupt-cells = <1>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>; + ranges; external-facing; }; - pci_bridge@b,0 { + pcie@b,0 { compatible = "pci0014,7a09.0", "pci0014,7a09", "pciclass060400", "pciclass0604"; reg = <0x5800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; #interrupt-cells = <1>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>; + ranges; external-facing; }; - pci_bridge@c,0 { + pcie@c,0 { compatible = "pci0014,7a09.0", "pci0014,7a09", "pciclass060400", "pciclass0604"; reg = <0x6000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; #interrupt-cells = <1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>; + ranges; external-facing; }; - pci_bridge@d,0 { + pcie@d,0 { compatible = "pci0014,7a19.0", "pci0014,7a19", "pciclass060400", "pciclass0604"; reg = <0x6800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; #interrupt-cells = <1>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>; + ranges; external-facing; }; - pci_bridge@e,0 { + pcie@e,0 { compatible = "pci0014,7a09.0", "pci0014,7a09", "pciclass060400", "pciclass0604"; reg = <0x7000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; #interrupt-cells = <1>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>; + ranges; external-facing; }; From 0db3bc9ce03ef3dfa8af58e258737ceab217eae6 Mon Sep 17 00:00:00 2001 From: Genjian Zhang Date: Thu, 16 May 2024 19:59:05 +0800 Subject: [PATCH 14/58] MIPS: sgi-ip22: Add prototypes for several functions to header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the following build warning: arch/mips/sgi-ip22/ip22-time.c:119:18: error: no previous prototype for ‘indy_8254timer_irq’ [-Werror=missing-prototypes] arch/mips/sgi-ip22/ip22-berr.c:89:6: error: no previous prototype for ‘ip22_be_interrupt’ [-Werror=missing-prototypes] arch/mips/sgi-ip22/ip22-berr.c:113:13: error: no previous prototype for ‘ip22_be_init’ [-Werror=missing-prototypes] Reported-by: k2ci Signed-off-by: Genjian Zhang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/sgi/ip22.h | 3 +++ arch/mips/sgi-ip22/ip22-int.c | 2 -- arch/mips/sgi-ip22/ip22-setup.c | 2 -- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h index 87ec9eaa04e3c..57942afb5c86b 100644 --- a/arch/mips/include/asm/sgi/ip22.h +++ b/arch/mips/include/asm/sgi/ip22.h @@ -76,5 +76,8 @@ extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg); extern unsigned short ip22_nvram_read(int reg); +extern void ip22_be_interrupt(int irq); +extern void ip22_be_init(void) __init; +extern void indy_8254timer_irq(void); #endif diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 96798a4ab2def..11f8adc98cb59 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -165,8 +165,6 @@ static void __irq_entry indy_buserror_irq(void) #define SGI_INTERRUPTS SGINT_LOCAL3 #endif -extern void indy_8254timer_irq(void); - /* * IRQs on the INDY look basically (barring software IRQs which we don't use * at all) like: diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index b69daa02401b9..e06a818fe7928 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -26,8 +26,6 @@ #include #include -extern void ip22_be_init(void) __init; - void __init plat_mem_setup(void) { char *ctype; From 3ee1167a16dfae1f656d52133a72be992cb85047 Mon Sep 17 00:00:00 2001 From: Genjian Zhang Date: Thu, 16 May 2024 19:59:06 +0800 Subject: [PATCH 15/58] MIPS: ip22-gio: Make ip22_gio_set_64bit() and ip22_gio_init() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These functions are used in only one file. Made them static to fix the following build error: arch/mips/sgi-ip22/ip22-gio.c:249:6: error: no previous prototype for ‘ip22_gio_set_64bit’ [-Werror=missing-prototypes] arch/mips/sgi-ip22/ip22-gio.c:398:12: error: no previous prototype for ‘ip22_gio_init’ [-Werror=missing-prototypes] Reported-by: k2ci Signed-off-by: Genjian Zhang Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip22/ip22-gio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c index a3cdcb2899410..2738325e98dd0 100644 --- a/arch/mips/sgi-ip22/ip22-gio.c +++ b/arch/mips/sgi-ip22/ip22-gio.c @@ -246,7 +246,7 @@ void gio_set_master(struct gio_device *dev) } EXPORT_SYMBOL_GPL(gio_set_master); -void ip22_gio_set_64bit(int slotno) +static void ip22_gio_set_64bit(int slotno) { u32 tmp = sgimc->giopar; @@ -395,7 +395,7 @@ static struct resource gio_bus_resource = { .flags = IORESOURCE_MEM, }; -int __init ip22_gio_init(void) +static int __init ip22_gio_init(void) { unsigned int pbdma __maybe_unused; int ret; From 8de4ed75bd14ed197119ac509c6902a8561e0c1c Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sun, 16 Jun 2024 18:54:24 +0100 Subject: [PATCH 16/58] MIPS: ip30: ip30-console: Add missing include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include linux/processor.h to fix build error: arch/mips/sgi-ip30/ip30-console.c: In function ‘prom_putchar’: arch/mips/sgi-ip30/ip30-console.c:21:17: error: implicit declaration of function ‘cpu_relax’ [-Werror=implicit-function-declaration] 21 | cpu_relax(); Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip30/ip30-console.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/sgi-ip30/ip30-console.c b/arch/mips/sgi-ip30/ip30-console.c index 7c6dcf6e73f70..a5f10097b9859 100644 --- a/arch/mips/sgi-ip30/ip30-console.c +++ b/arch/mips/sgi-ip30/ip30-console.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include From f5e9d56199f715357a28f057312b116d97f32f90 Mon Sep 17 00:00:00 2001 From: Jeff Johnson Date: Tue, 18 Jun 2024 18:01:29 -0700 Subject: [PATCH 17/58] crypto: mips/poly1305 - add missing MODULE_DESCRIPTION() macro With ARCH=mips, make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in arch/mips/crypto/poly1305-mips.o Add the missing invocation of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson Signed-off-by: Thomas Bogendoerfer --- arch/mips/crypto/poly1305-glue.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/crypto/poly1305-glue.c b/arch/mips/crypto/poly1305-glue.c index bc6110fb98e0a..867728ee535af 100644 --- a/arch/mips/crypto/poly1305-glue.c +++ b/arch/mips/crypto/poly1305-glue.c @@ -186,6 +186,7 @@ static void __exit mips_poly1305_mod_exit(void) module_init(mips_poly1305_mod_init); module_exit(mips_poly1305_mod_exit); +MODULE_DESCRIPTION("Poly1305 transform (MIPS accelerated"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS_CRYPTO("poly1305"); MODULE_ALIAS_CRYPTO("poly1305-mips"); From b81656c37acf1e682dde02f3e07987784b0f3634 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:09 +0100 Subject: [PATCH 18/58] MIPS: Loongson64: Remove memory node for builtin-dtb Builtin DTBS should never contain memory node as memory is going to be managed by LEFI interface. Remove memory node to prevent confliction. Fixes: b1a792601f26 ("MIPS: Loongson64: DeviceTree for Loongson-2K1000") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index b5593f7cc383b..f5a74338bf059 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -23,14 +23,6 @@ }; }; - memory@200000 { - compatible = "memory"; - device_type = "memory"; - reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */ - <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */ - <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */ - }; - cpu_clk: cpu_clk { #clock-cells = <0>; compatible = "fixed-clock"; From dbb69b9d6234aad23b3ecd33e5bc8a8ae1485b7d Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:10 +0100 Subject: [PATCH 19/58] MIPS: dts: loongson: Fix liointc IRQ polarity All internal liointc interrupts are high level triggered. Fixes: b1a792601f26 ("MIPS: Loongson64: DeviceTree for Loongson-2K1000") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- .../boot/dts/loongson/loongson64-2k1000.dtsi | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index f5a74338bf059..3f5255584c308 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -93,7 +93,7 @@ compatible = "loongson,ls2k1000-rtc"; reg = <0 0x1fe07800 0 0x78>; interrupt-parent = <&liointc0>; - interrupts = <60 IRQ_TYPE_LEVEL_LOW>; + interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; }; uart0: serial@1fe00000 { @@ -101,7 +101,7 @@ reg = <0 0x1fe00000 0 0x8>; clock-frequency = <125000000>; interrupt-parent = <&liointc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; no-loopback-test; }; @@ -124,8 +124,8 @@ "pciclass0c03"; reg = <0x1800 0x0 0x0 0x0 0x0>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>, - <13 IRQ_TYPE_LEVEL_LOW>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&liointc0>; phy-mode = "rgmii"; @@ -147,8 +147,8 @@ "loongson, pci-gmac"; reg = <0x1900 0x0 0x0 0x0 0x0>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>, - <15 IRQ_TYPE_LEVEL_LOW>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&liointc0>; phy-mode = "rgmii"; @@ -169,7 +169,7 @@ "pciclass0c03"; reg = <0x2100 0x0 0x0 0x0 0x0>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; }; @@ -180,7 +180,7 @@ "pciclass0c03"; reg = <0x2200 0x0 0x0 0x0 0x0>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; }; @@ -191,7 +191,7 @@ "pciclass0106"; reg = <0x4000 0x0 0x0 0x0 0x0>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc0>; }; @@ -206,10 +206,10 @@ #size-cells = <2>; device_type = "pci"; #interrupt-cells = <1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>; + interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>; ranges; external-facing; }; @@ -225,10 +225,10 @@ #size-cells = <2>; device_type = "pci"; #interrupt-cells = <1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>; + interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>; ranges; external-facing; }; @@ -244,10 +244,10 @@ #size-cells = <2>; device_type = "pci"; #interrupt-cells = <1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>; + interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>; ranges; external-facing; }; @@ -263,10 +263,10 @@ #size-cells = <2>; device_type = "pci"; #interrupt-cells = <1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>; ranges; external-facing; }; @@ -282,10 +282,10 @@ #size-cells = <2>; device_type = "pci"; #interrupt-cells = <1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>; + interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>; ranges; external-facing; }; @@ -301,10 +301,10 @@ #size-cells = <2>; device_type = "pci"; #interrupt-cells = <1>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&liointc1>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>; + interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>; ranges; external-facing; }; From f70fd92df7529e7283e02a6c3a2510075f13ba30 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:11 +0100 Subject: [PATCH 20/58] MIPS: dts: loongson: Fix ls2k1000-rtc interrupt The correct interrupt line for RTC is line 8 on liointc1. Fixes: e47084e116fc ("MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index 3f5255584c308..c3a57a0befa7c 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -92,8 +92,8 @@ rtc0: rtc@1fe07800 { compatible = "loongson,ls2k1000-rtc"; reg = <0 0x1fe07800 0 0x78>; - interrupt-parent = <&liointc0>; - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&liointc1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; }; uart0: serial@1fe00000 { From 813c18d1ca1987afaf47e035152e1baa1375b1b2 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:12 +0100 Subject: [PATCH 21/58] MIPS: dts: loongson: Fix GMAC phy node phy-mode should be rgmii-id to match hardware configuration. Also there should be a phy-handle to reference phy node. Fixes: f8a11425075f ("MIPS: Loongson64: Add GMAC support for Loongson-2K1000") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index c3a57a0befa7c..b2f66f6bb2fea 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -128,7 +128,8 @@ <13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&liointc0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; mdio { #address-cells = <1>; #size-cells = <0>; @@ -151,7 +152,8 @@ <15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&liointc0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; mdio { #address-cells = <1>; #size-cells = <0>; From da3f62466e5afc752f8b72146bbc4700dbba5a9f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:13 +0100 Subject: [PATCH 22/58] MIPS: dts: loongson: Add ISA node ISA node is required by Loongson64 platforms to initialize PIO support. Kernel will hang at boot without ISA node. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi index b2f66f6bb2fea..cc7747c5f21f3 100644 --- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi +++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi @@ -44,6 +44,13 @@ 0 0x40000000 0 0x40000000 0 0x40000000 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; + isa@18000000 { + compatible = "isa"; + #size-cells = <1>; + #address-cells = <2>; + ranges = <1 0x0 0x0 0x18000000 0x4000>; + }; + pm: reset-controller@1fe07000 { compatible = "loongson,ls2k-pm"; reg = <0 0x1fe07000 0 0x422>; From c04366b1207a036b7de02dfcc1ac7138d3343c9b Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:14 +0100 Subject: [PATCH 23/58] MIPS: Loongson64: Test register availability before use Some global register address variable may be missing on specific CPU type, test them before use them. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 5a990cdef91a6..66d049cdcf145 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -466,12 +466,25 @@ static void loongson3_smp_finish(void) static void __init loongson3_smp_setup(void) { int i = 0, num = 0; /* i: physical id, num: logical id */ + int max_cpus = 0; init_cpu_possible(cpu_none_mask); + for (i = 0; i < ARRAY_SIZE(smp_group); i++) { + if (!smp_group[i]) + break; + max_cpus += loongson_sysconf.cores_per_node; + } + + if (max_cpus < loongson_sysconf.nr_cpus) { + pr_err("SMP Groups are less than the number of CPUs\n"); + loongson_sysconf.nr_cpus = max_cpus ? max_cpus : 1; + } + /* For unified kernel, NR_CPUS is the maximum possible value, * loongson_sysconf.nr_cpus is the really present value */ + i = 0; while (i < loongson_sysconf.nr_cpus) { if (loongson_sysconf.reserved_cpus_mask & (1< Date: Fri, 14 Jun 2024 16:40:15 +0100 Subject: [PATCH 24/58] platform: mips: cpu_hwmon: Disable driver on unsupported hardware cpu_hwmon is unsupported on CPUs without loongson_chiptemp register and csr. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- drivers/platform/mips/cpu_hwmon.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c index d8c5f9195f85f..2ac2f31090f96 100644 --- a/drivers/platform/mips/cpu_hwmon.c +++ b/drivers/platform/mips/cpu_hwmon.c @@ -139,6 +139,9 @@ static int __init loongson_hwmon_init(void) csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; + if (!csr_temp_enable && !loongson_chiptemp[0]) + return -ENODEV; + nr_packages = loongson_sysconf.nr_cpus / loongson_sysconf.cores_per_package; From 4e7ca0b57f3bc09ba3e4ab86bf6b7c35134bfd04 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:16 +0100 Subject: [PATCH 25/58] MIPS: Loongson64: reset: Prioritise firmware service We should always use firmware's poweroff & reboot service if it's available as firmware may need to perform more task than platform's syscon etc. However _machine_restart & poweroff hooks are registered at low priority, which means platform reboot driver can override them. Register firmware based reboot/poweroff implementation with register_sys_off_handler with appropriate priority so that they will be prioritised. Remove _machine_halt hook as it's deemed to be unnecessary. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/reset.c | 38 +++++++++++++++--------------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/arch/mips/loongson64/reset.c b/arch/mips/loongson64/reset.c index e01c8d4a805a9..3e20ade0503ad 100644 --- a/arch/mips/loongson64/reset.c +++ b/arch/mips/loongson64/reset.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -21,36 +22,21 @@ #include #include -static void loongson_restart(char *command) +static int firmware_restart(struct sys_off_data *unusedd) { void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr; fw_restart(); - while (1) { - if (cpu_wait) - cpu_wait(); - } + return NOTIFY_DONE; } -static void loongson_poweroff(void) +static int firmware_poweroff(struct sys_off_data *unused) { void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr; fw_poweroff(); - while (1) { - if (cpu_wait) - cpu_wait(); - } -} - -static void loongson_halt(void) -{ - pr_notice("\n\n** You can safely turn off the power now **\n\n"); - while (1) { - if (cpu_wait) - cpu_wait(); - } + return NOTIFY_DONE; } #ifdef CONFIG_KEXEC_CORE @@ -154,9 +140,17 @@ static void loongson_crash_shutdown(struct pt_regs *regs) static int __init mips_reboot_setup(void) { - _machine_restart = loongson_restart; - _machine_halt = loongson_halt; - pm_power_off = loongson_poweroff; + if (loongson_sysconf.restart_addr) { + register_sys_off_handler(SYS_OFF_MODE_RESTART, + SYS_OFF_PRIO_FIRMWARE, + firmware_restart, NULL); + } + + if (loongson_sysconf.poweroff_addr) { + register_sys_off_handler(SYS_OFF_MODE_POWER_OFF, + SYS_OFF_PRIO_FIRMWARE, + firmware_poweroff, NULL); + } #ifdef CONFIG_KEXEC_CORE kexec_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL); From 335819fd5bac67d05ab2d8d7438ac5c475ac03c6 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:17 +0100 Subject: [PATCH 26/58] MIPS: Loongson64: sleeper: Pass ra and sp as arguments Some firmware implementations require restoring ra and sp to be passed as arguments. Passing them as necessary. Fixes: 68557c59a550 ("MIPS: Loongson64: Implement PM suspend for LEFI firmware") Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/sleeper.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson64/sleeper.S b/arch/mips/loongson64/sleeper.S index 04874b9bf430b..cf16877409e2f 100644 --- a/arch/mips/loongson64/sleeper.S +++ b/arch/mips/loongson64/sleeper.S @@ -11,7 +11,11 @@ LEAF(loongson_lefi_sleep) SUSPEND_SAVE - jalr a0 - smp_slave_setup + move t9, a0 + PTR_LA a0, wake + move a1, sp + jalr t9 +wake: + smp_slave_setup RESUME_RESTORE_REGS_RETURN END(loongson_lefi_sleep) From 77543269ff23c75bebfb8e6e9a1177b350908ea7 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 14 Jun 2024 16:40:18 +0100 Subject: [PATCH 27/58] MIPS: Loongson64: env: Hook up Loongsson-2K Somehow those enablement bits were left over when we were adding initial Loongson-2K support. Set up basic information and select proper builtin DTB for Loongson-2K. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-loongson64/boot_param.h | 2 ++ arch/mips/loongson64/env.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h index e007edd6b60a7..9218b3ae33832 100644 --- a/arch/mips/include/asm/mach-loongson64/boot_param.h +++ b/arch/mips/include/asm/mach-loongson64/boot_param.h @@ -42,12 +42,14 @@ enum loongson_cpu_type { Legacy_1B = 0x5, Legacy_2G = 0x6, Legacy_2H = 0x7, + Legacy_2K = 0x8, Loongson_1A = 0x100, Loongson_1B = 0x101, Loongson_2E = 0x200, Loongson_2F = 0x201, Loongson_2G = 0x202, Loongson_2H = 0x203, + Loongson_2K = 0x204, Loongson_3A = 0x300, Loongson_3B = 0x301 }; diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index ef3750a6ffacf..09ff052698614 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -88,6 +88,12 @@ void __init prom_lefi_init_env(void) cpu_clock_freq = ecpu->cpu_clock_freq; loongson_sysconf.cputype = ecpu->cputype; switch (ecpu->cputype) { + case Legacy_2K: + case Loongson_2K: + smp_group[0] = 0x900000001fe11000; + loongson_sysconf.cores_per_node = 2; + loongson_sysconf.cores_per_package = 2; + break; case Legacy_3A: case Loongson_3A: loongson_sysconf.cores_per_node = 4; @@ -221,6 +227,8 @@ void __init prom_lefi_init_env(void) default: break; } + } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) { + loongson_fdt_blob = __dtb_loongson64_2core_2k1000_begin; } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) { if (loongson_sysconf.bridgetype == LS7A) loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin; From a5c05453a13ab324ad8719e8a23dfb6af01f3652 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 20 Jun 2024 17:26:42 +0200 Subject: [PATCH 28/58] mips: bmips: rework and cache CBR addr handling Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in setup.c for each arch to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Acked-by: Florian Fainelli Signed-off-by: Christian Marangi Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/prom.c | 3 +++ arch/mips/bcm47xx/setup.c | 4 ++++ arch/mips/bcm63xx/prom.c | 3 +++ arch/mips/bcm63xx/setup.c | 4 ++++ arch/mips/bmips/dma.c | 2 +- arch/mips/bmips/setup.c | 7 ++++++- arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 4 ++-- 8 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 58fb7c2dc3b8a..66e3ee2b04e6b 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,8 @@ static __init void prom_init_mem(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); prom_init_mem(); setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); } diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 94bf839576c15..2f1ee0560aba5 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -45,6 +46,9 @@ #include #include +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + union bcm47xx_bus bcm47xx_bus; EXPORT_SYMBOL(bcm47xx_bus); diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index c3a2ea62c5c30..f21dd168171a5 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -22,6 +22,9 @@ void __init prom_init(void) { u32 reg, mask; + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); + bcm63xx_cpu_init(); /* stop any running watchdog */ diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index c13ddb544a23b..16ea8945ae3a7 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,9 @@ #include #include +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + void bcm63xx_machine_halt(void) { pr_info("System halted\n"); diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 3779e7855bd75..2bc9c0d4402fd 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; void arch_sync_dma_for_cpu_all(void) { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; u32 cfg; if (boot_cpu_type() != CPU_BMIPS3300 && diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 66a8ba19c2872..6dd166c3d6438 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,6 +34,9 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; @@ -111,7 +114,7 @@ static void bcm6358_quirks(void) * because the bootloader is not initializing it properly. */ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || - !!BMIPS_GET_CBR(); + !!bmips_cbr_addr; } static void bcm6368_quirks(void) @@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); bmips_init_cfe(); bmips_cpu_setup(); register_bmips_smp_ops(); diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 581a6a3c66e40..3a1cdfddb987e 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; +extern void __iomem *bmips_cbr_addr; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b3dbf9ecb0d63..a4f84667a9019 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, u32 val) info.val = val; bmips_set_reset_vec_remote(&info); } else { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; if (cpu == 0) __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); @@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { - void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); + void __iomem __maybe_unused *cbr = bmips_cbr_addr; u32 __maybe_unused cfg; switch (current_cpu_type()) { From 3de96d810ffd712b7ad2bd764c1390fac2436551 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 20 Jun 2024 17:26:43 +0200 Subject: [PATCH 29/58] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where CBR(Core Base Register) address might be badly or never initialized by the Bootloader or reading it from co-processor registers, if the system boots from secondary CPU, results in invalid address. The CBR address is always the same on the SoC. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi Acked-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Acked-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer --- .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca28881..0cc634482a6a8 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,16 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where CBR(Core Base Register) + address might be badly or never initialized by the Bootloader + or reading it from co-processor registers, if the system boots + from secondary CPU, results in invalid address. + The CBR address is always the same on the SoC hence it + can be provided in DT to handle these broken case. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +74,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: From b95b30e50aed225d26e20737873ae2404941901c Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 20 Jun 2024 17:26:44 +0200 Subject: [PATCH 30/58] mips: bmips: setup: make CBR address configurable Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by: Christian Marangi Acked-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/setup.c | 6 +++++- arch/mips/bcm63xx/setup.c | 6 +++++- arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++-- 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 2f1ee0560aba5..247be207f293c 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -46,7 +46,11 @@ #include #include -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; union bcm47xx_bus bcm47xx_bus; diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index 16ea8945ae3a7..81529084bc75d 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -23,7 +23,11 @@ #include #include -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; void bcm63xx_machine_halt(void) diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 6dd166c3d6438..2572fd49a6e94 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,7 +34,11 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; extern bool bmips_rac_flush_disable; @@ -208,13 +212,35 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { struct device_node *np; + u32 addr; unflatten_and_copy_device_tree(); /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ np = of_find_node_by_name(NULL, "cpus"); - if (np && of_get_available_child_count(np) <= 1) + if (!np) + return; + + if (of_get_available_child_count(np) <= 1) bmips_smp_enabled = 0; + + /* Check if DT provide a CBR address */ + if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) + goto exit; + + /* Make sure CBR address is outside DRAM window */ + if (addr >= (u32)memblock_start_of_DRAM() && + addr < (u32)memblock_end_of_DRAM()) { + WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", + addr); + goto exit; + } + + bmips_cbr_addr = (void __iomem *)addr; + /* Since CBR is provided by DT, enable RAC flush */ + bmips_rac_flush_disable = false; + +exit: of_node_put(np); } From 04f38d1a4db017f17e82442727b91ce03dd72759 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= Date: Thu, 20 Jun 2024 17:26:45 +0200 Subject: [PATCH 31/58] mips: bmips: enable RAC on BMIPS4350 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by: Daniel González Cabanelas Signed-off-by: Álvaro Fernández Rojas [ rework code and reduce code duplication ] Acked-by: Florian Fainelli Signed-off-by: Christian Marangi Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/smp-bmips.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index a4f84667a9019..35b8d810833cc 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -592,6 +592,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { void __iomem __maybe_unused *cbr = bmips_cbr_addr; + u32 __maybe_unused rac_addr; u32 __maybe_unused cfg; switch (current_cpu_type()) { @@ -620,6 +621,23 @@ void bmips_cpu_setup(void) __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); break; + case CPU_BMIPS4350: + rac_addr = BMIPS_RAC_CONFIG_1; + + if (!(read_c0_brcm_cmt_local() & (1 << 31))) + rac_addr = BMIPS_RAC_CONFIG; + + /* Enable data RAC */ + cfg = __raw_readl(cbr + rac_addr); + __raw_writel(cfg | 0xf, cbr + rac_addr); + __raw_readl(cbr + rac_addr); + + /* Flush stale data out of the readahead cache */ + cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); + __raw_readl(cbr + BMIPS_RAC_CONFIG); + break; + case CPU_BMIPS4380: /* CBG workaround for early BMIPS4380 CPUs */ switch (read_c0_prid()) { From c171186c177970d3ec22dd814f2693f1f7fc1e7d Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:28 +0100 Subject: [PATCH 32/58] MIPS: csrc-r4k: Refine rating computation Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/csrc-r4k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index edc4afc080faa..f02ae333f4f95 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) return -ENXIO; /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + clocksource_mips.rating = 200; + clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99); /* * R2 onwards makes the count accessible to user mode so it can be used From 7190401fc56fb5f02ee3d04476778ab000bbaf32 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:29 +0100 Subject: [PATCH 33/58] MIPS: csrc-r4k: Apply verification clocksource flags CP0 counter suffers from various problems like SMP sync, behaviour on wait. Set CLOCK_SOURCE_MUST_VERIFY and CLOCK_SOURCE_VERIFY_PERCPU, as what x86 did to TSC, to let kernel test it before use. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/csrc-r4k.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index f02ae333f4f95..055747a7417d6 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -21,7 +21,9 @@ static struct clocksource clocksource_mips = { .name = "MIPS", .read = c0_hpt_read, .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_MUST_VERIFY | + CLOCK_SOURCE_VERIFY_PERCPU, }; static u64 __maybe_unused notrace r4k_read_sched_clock(void) From 426fa8e4fe7bb914b5977cbce453a9926bf5b2e6 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:30 +0100 Subject: [PATCH 34/58] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT csrc-r4k suffers from SMP synchronization overhead. Select HAVE_UNSTABLE_SCHED_CLOCK to workaround drift between the CPUs on the system. HAVE_UNSTABLE_SCHED_CLOCK requires cmpxchg64, so enable it for 64 bits only. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1236ea1220612..c14192514e9db 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1084,6 +1084,7 @@ config CSRC_IOASIC config CSRC_R4K select CLOCKSOURCE_WATCHDOG if CPU_FREQ + select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT bool config CSRC_SB1250 From 7464c0762e96904b6bf686a4dc8b3255adf1c890 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:31 +0100 Subject: [PATCH 35/58] MIPS: csrc-r4k: Don't register as sched_clock if unfit When we have more than one CPU in system, counter synchronisation overhead can lead to a scenario that sched_clock goes backward when being read from different CPUs. This is accommodated by CONFIG_HAVE_UNSTABLE_SCHED_CLOCK, but it's unavailable on 32bit kernel. We don't want to risk sched_clock correctness, so if we have multiple CPU in system and CONFIG_HAVE_UNSTABLE_SCHED_CLOCK is not set, we just don't use counter as sched_clock source. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/csrc-r4k.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 055747a7417d6..bdb1fa8931f4a 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -68,6 +68,18 @@ static bool rdhwr_count_usable(void) return false; } +static inline __init bool count_can_be_sched_clock(void) +{ + if (IS_ENABLED(CONFIG_CPU_FREQ)) + return false; + + if (num_possible_cpus() > 1 && + !IS_ENABLED(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK)) + return false; + + return true; +} + #ifdef CONFIG_CPU_FREQ static bool __read_mostly r4k_clock_unstable; @@ -125,9 +137,8 @@ int __init init_r4k_clocksource(void) clocksource_register_hz(&clocksource_mips, mips_hpt_frequency); -#ifndef CONFIG_CPU_FREQ - sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency); -#endif + if (count_can_be_sched_clock()) + sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency); return 0; } From 580724fce27f2b71b3e4d58bbe6d83b671929b33 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:54:32 +0100 Subject: [PATCH 36/58] MIPS: sync-r4k: Rework based on x86 tsc_sync The original sync-r4k did a good job on reducing jitter by determine the "next time value", but it has a limitation that when synchronization being performed too many times due to high core count or CPU hotplug, the timewrap on CPU0 will become unaccpetable. Rework the mechanism based on latest x86 tsc_sync. (It seems like the original implementation is based on tsc_sync at that time, so it's just a refresh.) To improve overall performance. Tesed on Loongson64, Boston, QEMU. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/r4k-timer.h | 5 - arch/mips/kernel/smp.c | 2 - arch/mips/kernel/sync-r4k.c | 281 +++++++++++++++++++++--------- 3 files changed, 202 insertions(+), 86 deletions(-) diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h index 6e7361629348a..432e61dd5204c 100644 --- a/arch/mips/include/asm/r4k-timer.h +++ b/arch/mips/include/asm/r4k-timer.h @@ -12,15 +12,10 @@ #ifdef CONFIG_SYNC_R4K -extern void synchronise_count_master(int cpu); extern void synchronise_count_slave(int cpu); #else -static inline void synchronise_count_master(int cpu) -{ -} - static inline void synchronise_count_slave(int cpu) { } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 0b53d35a116e7..0362fc5df7b0f 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -462,8 +462,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) return -EIO; } - synchronise_count_master(cpu); - /* Wait for CPU to finish startup & mark itself online before return */ wait_for_completion(&cpu_running); return 0; diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index abdd7aaa3311c..39156592582ea 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/arch/mips/kernel/sync-r4k.c @@ -2,121 +2,244 @@ /* * Count register synchronisation. * - * All CPUs will have their count registers synchronised to the CPU0 next time - * value. This can cause a small timewarp for CPU0. All other CPU's should - * not have done anything significant (but they may have had interrupts - * enabled briefly - prom_smp_finish() should not be responsible for enabling - * interrupts...) + * Derived from arch/x86/kernel/tsc_sync.c + * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar */ #include #include #include +#include +#include +#include +#include #include -#include -#include #include +#include -static unsigned int initcount = 0; -static atomic_t count_count_start = ATOMIC_INIT(0); -static atomic_t count_count_stop = ATOMIC_INIT(0); - -#define COUNTON 100 -#define NR_LOOPS 3 - -void synchronise_count_master(int cpu) -{ - int i; - unsigned long flags; - - pr_info("Synchronize counters for CPU %u: ", cpu); +#define COUNTON 100 +#define NR_LOOPS 3 +#define LOOP_TIMEOUT 20 - local_irq_save(flags); +/* + * Entry/exit counters that make sure that both CPUs + * run the measurement code at once: + */ +static atomic_t start_count; +static atomic_t stop_count; +static atomic_t test_runs; - /* - * We loop a few times to get a primed instruction cache, - * then the last pass is more or less synchronised and - * the master and slaves each set their cycle counters to a known - * value all at once. This reduces the chance of having random offsets - * between the processors, and guarantees that the maximum - * delay between the cycle counters is never bigger than - * the latency of information-passing (cachelines) between - * two CPUs. - */ +/* + * We use a raw spinlock in this exceptional case, because + * we want to have the fastest, inlined, non-debug version + * of a critical section, to be able to prove counter time-warps: + */ +static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED; - for (i = 0; i < NR_LOOPS; i++) { - /* slaves loop on '!= 2' */ - while (atomic_read(&count_count_start) != 1) - mb(); - atomic_set(&count_count_stop, 0); - smp_wmb(); +static uint32_t last_counter; +static uint32_t max_warp; +static int nr_warps; +static int random_warps; - /* Let the slave writes its count register */ - atomic_inc(&count_count_start); +/* + * Counter warp measurement loop running on both CPUs. + */ +static uint32_t check_counter_warp(void) +{ + uint32_t start, now, prev, end, cur_max_warp = 0; + int i, cur_warps = 0; - /* Count will be initialised to current timer */ - if (i == 1) - initcount = read_c0_count(); + start = read_c0_count(); + end = start + (uint32_t) mips_hpt_frequency / 1000 * LOOP_TIMEOUT; + for (i = 0; ; i++) { /* - * Everyone initialises count in the last loop: + * We take the global lock, measure counter, save the + * previous counter that was measured (possibly on + * another CPU) and update the previous counter timestamp. */ - if (i == NR_LOOPS-1) - write_c0_count(initcount); + arch_spin_lock(&sync_lock); + prev = last_counter; + now = read_c0_count(); + last_counter = now; + arch_spin_unlock(&sync_lock); /* - * Wait for slave to leave the synchronization point: + * Be nice every now and then (and also check whether + * measurement is done [we also insert a 10 million + * loops safety exit, so we dont lock up in case the + * counter is totally broken]): */ - while (atomic_read(&count_count_stop) != 1) - mb(); - atomic_set(&count_count_start, 0); - smp_wmb(); - atomic_inc(&count_count_stop); + if (unlikely(!(i & 7))) { + if (now > end || i > 10000000) + break; + cpu_relax(); + touch_nmi_watchdog(); + } + /* + * Outside the critical section we can now see whether + * we saw a time-warp of the counter going backwards: + */ + if (unlikely(prev > now)) { + arch_spin_lock(&sync_lock); + max_warp = max(max_warp, prev - now); + cur_max_warp = max_warp; + /* + * Check whether this bounces back and forth. Only + * one CPU should observe time going backwards. + */ + if (cur_warps != nr_warps) + random_warps++; + nr_warps++; + cur_warps = nr_warps; + arch_spin_unlock(&sync_lock); + } + } + WARN(!(now-start), + "Warning: zero counter calibration delta: %d [max: %d]\n", + now-start, end-start); + return cur_max_warp; +} + +/* + * The freshly booted CPU initiates this via an async SMP function call. + */ +static void check_counter_sync_source(void *__cpu) +{ + unsigned int cpu = (unsigned long)__cpu; + int cpus = 2; + + atomic_set(&test_runs, NR_LOOPS); +retry: + /* Wait for the target to start. */ + while (atomic_read(&start_count) != cpus - 1) + cpu_relax(); + + /* + * Trigger the target to continue into the measurement too: + */ + atomic_inc(&start_count); + + check_counter_warp(); + + while (atomic_read(&stop_count) != cpus-1) + cpu_relax(); + + /* + * If the test was successful set the number of runs to zero and + * stop. If not, decrement the number of runs an check if we can + * retry. In case of random warps no retry is attempted. + */ + if (!nr_warps) { + atomic_set(&test_runs, 0); + + pr_info("Counter synchronization [CPU#%d -> CPU#%u]: passed\n", + smp_processor_id(), cpu); + } else if (atomic_dec_and_test(&test_runs) || random_warps) { + /* Force it to 0 if random warps brought us here */ + atomic_set(&test_runs, 0); + + pr_info("Counter synchronization [CPU#%d -> CPU#%u]:\n", + smp_processor_id(), cpu); + pr_info("Measured %d cycles counter warp between CPUs", max_warp); + if (random_warps) + pr_warn("Counter warped randomly between CPUs\n"); } - /* Arrange for an interrupt in a short while */ - write_c0_compare(read_c0_count() + COUNTON); - local_irq_restore(flags); + /* + * Reset it - just in case we boot another CPU later: + */ + atomic_set(&start_count, 0); + random_warps = 0; + nr_warps = 0; + max_warp = 0; + last_counter = 0; + + /* + * Let the target continue with the bootup: + */ + atomic_inc(&stop_count); /* - * i386 code reported the skew here, but the - * count registers were almost certainly out of sync - * so no point in alarming people + * Retry, if there is a chance to do so. */ - pr_cont("done.\n"); + if (atomic_read(&test_runs) > 0) + goto retry; } +/* + * Freshly booted CPUs call into this: + */ void synchronise_count_slave(int cpu) { - int i; - unsigned long flags; + uint32_t cur_max_warp, gbl_max_warp, count; + int cpus = 2; - local_irq_save(flags); + if (!cpu_has_counter || !mips_hpt_frequency) + return; + /* Kick the control CPU into the counter synchronization function */ + smp_call_function_single(cpumask_first(cpu_online_mask), + check_counter_sync_source, + (unsigned long *)(unsigned long)cpu, 0); +retry: /* - * Not every cpu is online at the time this gets called, - * so we first wait for the master to say everyone is ready + * Register this CPU's participation and wait for the + * source CPU to start the measurement: */ + atomic_inc(&start_count); + while (atomic_read(&start_count) != cpus) + cpu_relax(); - for (i = 0; i < NR_LOOPS; i++) { - atomic_inc(&count_count_start); - while (atomic_read(&count_count_start) != 2) - mb(); + cur_max_warp = check_counter_warp(); - /* - * Everyone initialises count in the last loop: - */ - if (i == NR_LOOPS-1) - write_c0_count(initcount); + /* + * Store the maximum observed warp value for a potential retry: + */ + gbl_max_warp = max_warp; + + /* + * Ok, we are done: + */ + atomic_inc(&stop_count); + + /* + * Wait for the source CPU to print stuff: + */ + while (atomic_read(&stop_count) != cpus) + cpu_relax(); - atomic_inc(&count_count_stop); - while (atomic_read(&count_count_stop) != 2) - mb(); + /* + * Reset it for the next sync test: + */ + atomic_set(&stop_count, 0); + + /* + * Check the number of remaining test runs. If not zero, the test + * failed and a retry with adjusted counter is possible. If zero the + * test was either successful or failed terminally. + */ + if (!atomic_read(&test_runs)) { + /* Arrange for an interrupt in a short while */ + write_c0_compare(read_c0_count() + COUNTON); + return; } - /* Arrange for an interrupt in a short while */ - write_c0_compare(read_c0_count() + COUNTON); - local_irq_restore(flags); + /* + * If the warp value of this CPU is 0, then the other CPU + * observed time going backwards so this counter was ahead and + * needs to move backwards. + */ + if (!cur_max_warp) + cur_max_warp = -gbl_max_warp; + + count = read_c0_count(); + count += cur_max_warp; + write_c0_count(count); + + pr_debug("Counter compensate: CPU%u observed %d warp\n", cpu, cur_max_warp); + + goto retry; + } -#undef NR_LOOPS From 02c76df921ae76634933107e082e1c1d00b21120 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Mon, 1 Jul 2024 16:48:42 -0700 Subject: [PATCH 37/58] MIPS: Alchemy: switch to use software nodes for GPIOs Switch to use software nodes/properties to describe GPIOs for the ADS7846 touchscreen and the SPI controller (away from using GPIO lookup tables). This allows removing use of ADS7846 platform data, which will be going away. Signed-off-by: Dmitry Torokhov Reviewed-by: Linus Walleij Signed-off-by: Thomas Bogendoerfer --- arch/mips/alchemy/devboards/db1000.c | 80 +++++++++++++++------------- 1 file changed, 42 insertions(+), 38 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 7b9f91db227f2..6984cd5169b5f 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -10,15 +10,16 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include -#include #include #include #include @@ -374,22 +375,20 @@ static struct platform_device db1100_mmc1_dev = { /******************************************************************************/ -static struct ads7846_platform_data db1100_touch_pd = { - .model = 7846, - .vref_mv = 3300, +static const struct software_node db1100_alchemy2_gpiochip = { + .name = "alchemy-gpio2", }; -static struct spi_gpio_platform_data db1100_spictl_pd = { - .num_chipselect = 1, +static const struct property_entry db1100_ads7846_properties[] = { + PROPERTY_ENTRY_U16("ti,vref_min", 3300), + PROPERTY_ENTRY_GPIO("pendown-gpios", + &db1100_alchemy2_gpiochip, 21, GPIO_ACTIVE_LOW), + { } }; -static struct gpiod_lookup_table db1100_touch_gpio_table = { - .dev_id = "spi0.0", - .table = { - GPIO_LOOKUP("alchemy-gpio2", 21, - "pendown", GPIO_ACTIVE_LOW), - { } - }, +static const struct software_node db1100_ads7846_swnode = { + .name = "ads7846", + .properties = db1100_ads7846_properties, }; static struct spi_board_info db1100_spi_info[] __initdata = { @@ -400,37 +399,37 @@ static struct spi_board_info db1100_spi_info[] __initdata = { .chip_select = 0, .mode = 0, .irq = AU1100_GPIO21_INT, - .platform_data = &db1100_touch_pd, + .swnode = &db1100_ads7846_swnode, }, }; -static struct platform_device db1100_spi_dev = { - .name = "spi_gpio", - .id = 0, - .dev = { - .platform_data = &db1100_spictl_pd, - .dma_mask = &au1xxx_all_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, +static const struct spi_gpio_platform_data db1100_spictl_pd __initconst = { + .num_chipselect = 1, }; /* * Alchemy GPIO 2 has its base at 200 so the GPIO lines * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip. */ -static struct gpiod_lookup_table db1100_spi_gpiod_table = { - .dev_id = "spi_gpio", - .table = { - GPIO_LOOKUP("alchemy-gpio2", 9, - "sck", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("alchemy-gpio2", 8, - "mosi", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("alchemy-gpio2", 7, - "miso", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("alchemy-gpio2", 10, - "cs", GPIO_ACTIVE_HIGH), - { }, - }, +static const struct property_entry db1100_spi_dev_properties[] __initconst = { + PROPERTY_ENTRY_GPIO("miso-gpios", + &db1100_alchemy2_gpiochip, 7, GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("mosi-gpios", + &db1100_alchemy2_gpiochip, 8, GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("sck-gpios", + &db1100_alchemy2_gpiochip, 9, GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("cs-gpios", + &db1100_alchemy2_gpiochip, 10, GPIO_ACTIVE_HIGH), + { } +}; + +static const struct platform_device_info db1100_spi_dev_info __initconst = { + .name = "spi_gpio", + .id = 0, + .data = &db1100_spictl_pd, + .size_data = sizeof(db1100_spictl_pd), + .dma_mask = DMA_BIT_MASK(32), + .properties = db1100_spi_dev_properties, }; static struct platform_device *db1x00_devs[] = { @@ -452,8 +451,10 @@ int __init db1000_dev_setup(void) { int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; + int err; unsigned long pfc; struct clk *c, *p; + struct platform_device *spi_dev; if (board == BCSR_WHOAMI_DB1500) { c0 = AU1500_GPIO2_INT; @@ -480,7 +481,7 @@ int __init db1000_dev_setup(void) pfc |= (1 << 0); /* SSI0 pins as GPIOs */ alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); - gpiod_add_lookup_table(&db1100_touch_gpio_table); + software_node_register(&db1100_alchemy2_gpiochip); spi_register_board_info(db1100_spi_info, ARRAY_SIZE(db1100_spi_info)); @@ -497,8 +498,11 @@ int __init db1000_dev_setup(void) clk_put(p); platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); - gpiod_add_lookup_table(&db1100_spi_gpiod_table); - platform_device_register(&db1100_spi_dev); + + spi_dev = platform_device_register_full(&db1100_spi_dev_info); + err = PTR_ERR_OR_ZERO(spi_dev); + if (err) + pr_err("failed to register SPI controller: %d\n", err); } else if (board == BCSR_WHOAMI_DB1000) { c0 = AU1000_GPIO2_INT; c1 = AU1000_GPIO5_INT; From bde4b22dc526dea5c1170f2645f268c1d78c924e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Lebrun?= Date: Fri, 28 Jun 2024 18:11:50 +0200 Subject: [PATCH 38/58] dt-bindings: soc: mobileye: add EyeQ OLB system controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add documentation to describe the "Other Logic Block" system-controller. It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have a single instance, whereas EyeQ6H has seven named instances. Features provided are: - Clocks, children to main crystal. Some PLLs and divider clocks. - Resets. Some instances DO NOT have reset. - Pinctrl. Only EyeQ5 has such feature. Those are NOT the only features exposed in OLB system-controllers! Many individual registers, related to IP block integration, can be found. Additional features will be exposed over time. We simplify devicetree phandles to OLB in two ways: - Compatibles exposing a single clock do not ask for a index argument. This means we use EyeQ6H OLB south (it has four clocks): clocks = <&olb_south EQ6HC_SOUTH_PLL_PER>; But use EyeQ6H OLB east (it has one clock): clocks = <&olb_east>; - Compatibles exposing a single reset domain do not ask for a domain index, only a reset index. This means we use EyeQ5 OLB (it has three domains): resets = <&olb 0 10>; But use EyeQ6H west reset (it has one domain): resets = <&olb_west 3>; About pinctrl subnodes: all pins have two functionality, either GPIO or something-else. The latter is pin dependent, we express constraints using many if-then. Reviewed-by: Rob Herring (Arm) Signed-off-by: Théo Lebrun Signed-off-by: Thomas Bogendoerfer --- .../soc/mobileye/mobileye,eyeq5-olb.yaml | 374 ++++++++++++++++++ 1 file changed, 374 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml new file mode 100644 index 0000000000000..f7e606d45ebcf --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -0,0 +1,374 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ SoC system controller + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +description: + OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks, + resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single + instance. EyeQ6H hosts seven instances. + +properties: + compatible: + items: + - enum: + - mobileye,eyeq5-olb + - mobileye,eyeq6l-olb + - mobileye,eyeq6h-acc-olb + - mobileye,eyeq6h-central-olb + - mobileye,eyeq6h-east-olb + - mobileye,eyeq6h-west-olb + - mobileye,eyeq6h-south-olb + - mobileye,eyeq6h-ddr0-olb + - mobileye,eyeq6h-ddr1-olb + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + First cell is domain and optional if compatible has a single reset domain. + Second cell is reset index inside that domain. + enum: [ 1, 2 ] + + '#clock-cells': + description: + Cell is clock index. Optional if compatible has a single clock. + enum: [ 0, 1 ] + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + const: ref + +patternProperties: + '-pins?$': + type: object + description: Pin muxing configuration. + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + properties: + pins: true + function: + enum: [gpio, + # Bank A + timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0, + spi1, refclk0, + # Bank B + timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0] + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + required: + - pins + - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + pins: + items: # PA0 - PA28, PB0 - PB22 + pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$' + - if: + properties: + function: + const: timer0 + then: + properties: + pins: + items: + enum: [PA0, PA1] + - if: + properties: + function: + const: timer1 + then: + properties: + pins: + items: + enum: [PA2, PA3] + - if: + properties: + function: + const: timer2 + then: + properties: + pins: + items: + enum: [PA4, PA5] + - if: + properties: + function: + const: timer5 + then: + properties: + pins: + items: + enum: [PA6, PA7, PA8, PA9] + - if: + properties: + function: + const: uart0 + then: + properties: + pins: + items: + enum: [PA10, PA11] + - if: + properties: + function: + const: uart1 + then: + properties: + pins: + items: + enum: [PA12, PA13] + - if: + properties: + function: + const: can0 + then: + properties: + pins: + items: + enum: [PA14, PA15] + - if: + properties: + function: + const: can1 + then: + properties: + pins: + items: + enum: [PA16, PA17] + - if: + properties: + function: + const: spi0 + then: + properties: + pins: + items: + enum: [PA18, PA19, PA20, PA21, PA22] + - if: + properties: + function: + const: spi1 + then: + properties: + pins: + items: + enum: [PA23, PA24, PA25, PA26, PA27] + - if: + properties: + function: + const: refclk0 + then: + properties: + pins: + items: + enum: [PA28] + - if: + properties: + function: + const: timer3 + then: + properties: + pins: + items: + enum: [PB0, PB1] + - if: + properties: + function: + const: timer4 + then: + properties: + pins: + items: + enum: [PB2, PB3] + - if: + properties: + function: + const: timer6 + then: + properties: + pins: + items: + enum: [PB4, PB5, PB6, PB7] + - if: + properties: + function: + const: uart2 + then: + properties: + pins: + items: + enum: [PB8, PB9] + - if: + properties: + function: + const: can2 + then: + properties: + pins: + items: + enum: [PB10, PB11] + - if: + properties: + function: + const: spi2 + then: + properties: + pins: + items: + enum: [PB12, PB13, PB14, PB15, PB16] + - if: + properties: + function: + const: spi3 + then: + properties: + pins: + items: + enum: [PB17, PB18, PB19, PB20, PB21] + - if: + properties: + function: + const: mclk0 + then: + properties: + pins: + items: + enum: [PB22] + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +allOf: + # Compatibles exposing a single reset domain. + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq6h-acc-olb + - mobileye,eyeq6h-east-olb + - mobileye,eyeq6h-west-olb + then: + properties: + '#reset-cells': + const: 1 + required: + - '#reset-cells' + + # Compatibles exposing two reset domains. + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq5-olb + - mobileye,eyeq6l-olb + then: + properties: + '#reset-cells': + const: 2 + required: + - '#reset-cells' + + # Compatibles not exposing resets. + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq6h-central-olb + - mobileye,eyeq6h-south-olb + - mobileye,eyeq6h-ddr0-olb + - mobileye,eyeq6h-ddr1-olb + then: + properties: + '#reset-cells': false + + # Compatibles exposing a single clock. + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq6h-central-olb + - mobileye,eyeq6h-east-olb + - mobileye,eyeq6h-west-olb + - mobileye,eyeq6h-ddr0-olb + - mobileye,eyeq6h-ddr1-olb + then: + properties: + '#clock-cells': + const: 0 + else: + properties: + '#clock-cells': + const: 1 + + # Only EyeQ5 has pinctrl in OLB. + - if: + not: + properties: + compatible: + contains: + const: mobileye,eyeq5-olb + then: + patternProperties: + '-pins?$': false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon"; + reg = <0 0xe00000 0x0 0x400>; + #reset-cells = <2>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + }; + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-controller@d2003000 { + compatible = "mobileye,eyeq6h-acc-olb", "syscon"; + reg = <0x0 0xd2003000 0x0 0x1000>; + #reset-cells = <1>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + }; From 9b7e81a9bf2c65af2f78c51da61d9e0647f36fd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Lebrun?= Date: Fri, 28 Jun 2024 18:11:51 +0200 Subject: [PATCH 39/58] MIPS: mobileye: eyeq5: add OLB system-controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The OLB ("Other Logic Block") is a system-controller region hosting clock, reset and pin controllers. It contains registers such as I2C speed mode that need to be accessible by other nodes. Remove fixed-clocks previously used; replace references. Add parent crystal clock, fixed at 30MHz. Add pin nodes for all functions. Add mobileye,eyeq5-olb compatible node, hosting clk, reset and pinctrl. Add reset and pinctrl references to UART nodes. Signed-off-by: Théo Lebrun Signed-off-by: Thomas Bogendoerfer --- ...q5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +++----- arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi | 125 ++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 22 ++- 3 files changed, 162 insertions(+), 39 deletions(-) rename arch/mips/boot/dts/mobileye/{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} (88%) create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi similarity index 88% rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi index 78f5533a95c67..17a342cc744e5 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi @@ -3,42 +3,20 @@ * Copyright 2023 Mobileye Vision Technologies Ltd. */ +#include + / { /* Fixed clock */ - pll_cpu: pll-cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1500000000>; - }; - - pll_vdi: pll-vdi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1280000000>; - }; - - pll_per: pll-per { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - pll_ddr0: pll-ddr0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1857210000>; - }; - - pll_ddr1: pll-ddr1 { + xtal: xtal { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1857210000>; + clock-frequency = <30000000>; }; /* PLL_CPU derivatives */ occ_cpu: occ-cpu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&olb EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; @@ -101,7 +79,7 @@ }; occ_isram: occ-isram { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&olb EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -115,7 +93,7 @@ }; occ_dbu: occ-dbu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&olb EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -130,7 +108,7 @@ /* PLL_VDI derivatives */ occ_vdi: occ-vdi { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&olb EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -144,7 +122,7 @@ }; occ_can_ser: occ-can-ser { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&olb EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -158,7 +136,7 @@ }; i2c_ser_clk: i2c-ser-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&olb EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -166,7 +144,7 @@ /* PLL_PER derivatives */ occ_periph: occ-periph { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&olb EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -225,7 +203,7 @@ }; emmc_sys_clk: emmc-sys-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&olb EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -233,7 +211,7 @@ }; ccf_ctrl_clk: ccf-ctrl-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&olb EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; @@ -241,7 +219,7 @@ }; occ_mjpeg_core: occ-mjpeg-core { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&olb EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -265,7 +243,7 @@ }; fcmu_a_clk: fcmu-a-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&olb EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -273,7 +251,7 @@ }; occ_pci_sys: occ-pci-sys { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&olb EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; diff --git a/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi new file mode 100644 index 0000000000000..0b3671013ab40 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +/* + * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one + * pin configuration node per function. + */ + +&olb { + timer0_pins: timer0-pins { + function = "timer0"; + pins = "PA0", "PA1"; + }; + timer1_pins: timer1-pins { + function = "timer1"; + pins = "PA2", "PA3"; + }; + timer2_pins: timer2-pins { + function = "timer2"; + pins = "PA4", "PA5"; + }; + pps0_pins: pps0-pin { + function = "timer2"; + pins = "PA4"; + }; + pps1_pins: pps1-pin { + function = "timer2"; + pins = "PA5"; + }; + timer5_ext_pins: timer5-ext-pins { + function = "timer5"; + pins = "PA6", "PA7", "PA8", "PA9"; + }; + timer5_ext_input_pins: timer5-ext-input-pins { + function = "timer5"; + pins = "PA6", "PA7"; + }; + timer5_ext_incap_a_pins: timer5-ext-incap-a-pin { + function = "timer5"; + pins = "PA6"; + }; + timer5_ext_incap_b_pins: timer5-ext-incap-b-pin { + function = "timer5"; + pins = "PA7"; + }; + can0_pins: can0-pins { + function = "can0"; + pins = "PA14", "PA15"; + }; + can1_pins: can1-pins { + function = "can1"; + pins = "PA16", "PA17"; + }; + uart0_pins: uart0-pins { + function = "uart0"; + pins = "PA10", "PA11"; + }; + uart1_pins: uart1-pins { + function = "uart1"; + pins = "PA12", "PA13"; + }; + spi0_pins: spi0-pins { + function = "spi0"; + pins = "PA18", "PA19", "PA20", "PA21", "PA22"; + }; + spi1_pins: spi1-pins { + function = "spi1"; + pins = "PA23", "PA24", "PA25", "PA26", "PA27"; + }; + spi1_slave_pins: spi1-slave-pins { + function = "spi1"; + pins = "PA24", "PA25", "PA26"; + }; + refclk0_pins: refclk0-pin { + function = "refclk0"; + pins = "PA28"; + }; + timer3_pins: timer3-pins { + function = "timer3"; + pins = "PB0", "PB1"; + }; + timer4_pins: timer4-pins { + function = "timer4"; + pins = "PB2", "PB3"; + }; + timer6_ext_pins: timer6-ext-pins { + function = "timer6"; + pins = "PB4", "PB5", "PB6", "PB7"; + }; + timer6_ext_input_pins: timer6-ext-input-pins { + function = "timer6"; + pins = "PB4", "PB5"; + }; + timer6_ext_incap_a_pins: timer6-ext-incap-a-pin { + function = "timer6"; + pins = "PB4"; + }; + timer6_ext_incap_b_pins: timer6-ext-incap-b-pin { + function = "timer6"; + pins = "PB5"; + }; + can2_pins: can2-pins { + function = "can2"; + pins = "PB10", "PB11"; + }; + uart2_pins: uart2-pins { + function = "uart2"; + pins = "PB8", "PB9"; + }; + spi2_pins: spi2-pins { + function = "spi2"; + pins = "PB12", "PB13", "PB14", "PB15", "PB16"; + }; + spi3_pins: spi3-pins { + function = "spi3"; + pins = "PB17", "PB18", "PB19", "PB20", "PB21"; + }; + spi3_slave_pins: spi3-slave-pins { + function = "spi3"; + pins = "PB18", "PB19", "PB20"; + }; + mclk0_pins: mclk0-pin { + function = "mclk0"; + pins = "PB22"; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 6cc5980e2fa17..0708771c193d0 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq5-fixed-clocks.dtsi" +#include "eyeq5-clocks.dtsi" / { #address-cells = <2>; @@ -78,6 +78,9 @@ interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&olb 0 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; }; uart1: serial@900000 { @@ -88,6 +91,9 @@ interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&olb 0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; uart2: serial@a00000 { @@ -98,6 +104,18 @@ interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&olb 0 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + }; + + olb: system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon"; + reg = <0 0xe00000 0x0 0x400>; + #reset-cells = <2>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; }; gic: interrupt-controller@140000 { @@ -122,3 +140,5 @@ }; }; }; + +#include "eyeq5-pins.dtsi" From 6fe920b4fc18bed2f1946dab9b4d6784958cafc4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Lebrun?= Date: Fri, 28 Jun 2024 18:11:52 +0200 Subject: [PATCH 40/58] MAINTAINERS: Mobileye: add OLB drivers and dt-bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Register OLB-related files part of the "MOBILEYE MIPS SOCS" MAINTAINERS section. Those include: - drivers (clk-eyeq, reset-eyeq, pinctrl-eyeq5), - dt-bindings (mobileye,eyeq5-olb.yaml file), - bindings includes file . Signed-off-by: Théo Lebrun Signed-off-by: Thomas Bogendoerfer --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aacccb376c28a..e224f91f65a21 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15195,9 +15195,14 @@ M: Théo Lebrun L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S +F: drivers/clk/clk-eyeq.c +F: drivers/pinctrl/pinctrl-eyeq5.c +F: drivers/reset/reset-eyeq.c +F: include/dt-bindings/clock/mobileye,eyeq5-clk.h MODULE SUPPORT M: Luis Chamberlain From 89c7f5078935872cf47a713a645affb5037be694 Mon Sep 17 00:00:00 2001 From: Dominique Martinet Date: Fri, 5 Jul 2024 16:48:30 +0900 Subject: [PATCH 41/58] MIPS: Octeron: remove source file executable bit This does not matter the least, but there is no other .[ch] file in the repo that is executable, so clean this up. Fixes: 29b83a64df3b ("MIPS: Octeon: Add PCIe link status check") Signed-off-by: Dominique Martinet Signed-off-by: Thomas Bogendoerfer --- arch/mips/pci/pcie-octeon.c | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/mips/pci/pcie-octeon.c diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c old mode 100755 new mode 100644 From 36675ac2a759c6dc99e3155fd6b9ebcc75ef8a45 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 11 May 2024 12:43:28 +0200 Subject: [PATCH 42/58] MIPS: CPS: Add a couple of multi-cluster utility functions This patch introduces a couple of utility functions which help later patches with introducing support for multi-cluster systems. - mips_cps_multicluster_cpus() allows its caller to determine whether the system includes CPUs spread across multiple clusters. This is useful because in some cases behaviour can be more optimal taking this knowledge into account. The means by which we check this is dependent upon the way we probe CPUs & assign their numbers, so keeping this knowledge confined here in arch/mips/ seems appropriate. - mips_cps_first_online_in_cluster() allows its caller to determine whether it is running upon the first CPU online within its cluster. This information is useful in cases where some cluster-wide configuration may need to occur, but should not be repeated if another CPU in the cluster is already online. Similarly to the above this is determined based upon knowledge of CPU numbering so it makes sense to keep that knowledge in arch/mips/. The function is defined in mips-cm.c rather than in asm/mips-cps.h in order to allow us to use asm/cpu-info.h & linux/smp.h without encountering an include nightmare. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mips-cps.h | 39 ++++++++++++++++++++++++++++++++ arch/mips/kernel/mips-cm.c | 37 ++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h index c077e8d100f58..917009b80e695 100644 --- a/arch/mips/include/asm/mips-cps.h +++ b/arch/mips/include/asm/mips-cps.h @@ -8,6 +8,7 @@ #define __MIPS_ASM_MIPS_CPS_H__ #include +#include #include #include @@ -228,4 +229,42 @@ static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int co return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, cfg + 1); } +/** + * mips_cps_multicluster_cpus() - Detect whether CPUs are in multiple clusters + * + * Determine whether the system includes CPUs in multiple clusters - ie. + * whether we can treat the system as single or multi-cluster as far as CPUs + * are concerned. Note that this is slightly different to simply checking + * whether multiple clusters are present - it is possible for there to be + * clusters which contain no CPUs, which this function will effectively ignore. + * + * Returns true if CPUs are spread across multiple clusters, else false. + */ +static inline bool mips_cps_multicluster_cpus(void) +{ + unsigned int first_cl, last_cl; + + /* + * CPUs are numbered sequentially by cluster - ie. CPUs 0..X will be in + * cluster 0, CPUs X+1..Y in cluster 1, CPUs Y+1..Z in cluster 2 etc. + * + * Thus we can detect multiple clusters trivially by checking whether + * the first & last CPUs belong to the same cluster. + */ + first_cl = cpu_cluster(&boot_cpu_data); + last_cl = cpu_cluster(&cpu_data[nr_cpu_ids - 1]); + return first_cl != last_cl; +} + +/** + * mips_cps_first_online_in_cluster() - Detect if CPU is first online in cluster + * + * Determine whether the local CPU is the first to be brought online in its + * cluster - that is, whether there are any other online CPUs in the local + * cluster. + * + * Returns true if this CPU is first online, else false. + */ +extern unsigned int mips_cps_first_online_in_cluster(void); + #endif /* __MIPS_ASM_MIPS_CPS_H__ */ diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 3a115fab55739..3eb2cfb893e19 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -512,3 +512,40 @@ void mips_cm_error_report(void) /* reprime cause register */ write_gcr_error_cause(cm_error); } + +unsigned int mips_cps_first_online_in_cluster(void) +{ + unsigned int local_cl; + int i; + + local_cl = cpu_cluster(¤t_cpu_data); + + /* + * We rely upon knowledge that CPUs are numbered sequentially by + * cluster - ie. CPUs 0..X will be in cluster 0, CPUs X+1..Y in cluster + * 1, CPUs Y+1..Z in cluster 2 etc. This means that CPUs in the same + * cluster will immediately precede or follow one another. + * + * First we scan backwards, until we find an online CPU in the cluster + * or we move on to another cluster. + */ + for (i = smp_processor_id() - 1; i >= 0; i--) { + if (cpu_cluster(&cpu_data[i]) != local_cl) + break; + if (!cpu_online(i)) + continue; + return false; + } + + /* Then do the same for higher numbered CPUs */ + for (i = smp_processor_id() + 1; i < nr_cpu_ids; i++) { + if (cpu_cluster(&cpu_data[i]) != local_cl) + break; + if (!cpu_online(i)) + continue; + return false; + } + + /* We found no online CPUs in the local cluster */ + return true; +} From 680e7863de0c3d3551d247200fd1cb41ec874650 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 11 May 2024 12:43:29 +0200 Subject: [PATCH 43/58] MIPS: GIC: Generate redirect block accessors With CM 3.5 the "core-other" register block evolves into the "redirect" register block, which is capable of accessing not only the core local registers of other cores but also the shared/global registers of other clusters. This patch generates accessor functions for shared/global registers accessed via the redirect block, with "redir_" inserted after "gic_" in their names. For example the accessor function: read_gic_config() ...accesses the GIC_CONFIG register of the GIC in the local cluster. With this patch a new function: read_gic_redir_config() ...is added which accesses the GIC_CONFIG register of the GIC in whichever cluster the GCR_CL_REDIRECT register is configured to access. This mirrors the similar redirect block accessors already provided for the CM & CPC. Reviewed-by: Jiaxun Yang Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mips-gic.h | 50 ++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 084cac1c5ea2c..fd9da5e3beaae 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -28,11 +28,13 @@ extern void __iomem *mips_gic_base; /* For read-only shared registers */ #define GIC_ACCESSOR_RO(sz, off, name) \ - CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) + CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \ + CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name) /* For read-write shared registers */ #define GIC_ACCESSOR_RW(sz, off, name) \ - CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) + CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \ + CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name) /* For read-only local registers */ #define GIC_VX_ACCESSOR_RO(sz, off, name) \ @@ -45,7 +47,7 @@ extern void __iomem *mips_gic_base; CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name) /* For read-only shared per-interrupt registers */ -#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ +#define _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ static inline void __iomem *addr_gic_##name(unsigned int intr) \ { \ return mips_gic_base + (off) + (intr * (stride)); \ @@ -58,8 +60,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \ } /* For read-write shared per-interrupt registers */ -#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ - GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ +#define _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ \ static inline void write_gic_##name(unsigned int intr, \ unsigned int val) \ @@ -68,22 +70,30 @@ static inline void write_gic_##name(unsigned int intr, \ __raw_writel(val, addr_gic_##name(intr)); \ } +#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name) + +#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ + _GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name) + /* For read-only local per-interrupt registers */ #define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ - GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ + _GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ stride, vl_##name) \ - GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ + _GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ stride, vo_##name) /* For read-write local per-interrupt registers */ #define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ - GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ + _GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ stride, vl_##name) \ - GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ + _GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ stride, vo_##name) /* For read-only shared bit-per-interrupt registers */ -#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \ +#define _GIC_ACCESSOR_RO_INTR_BIT(off, name) \ static inline void __iomem *addr_gic_##name(void) \ { \ return mips_gic_base + (off); \ @@ -106,8 +116,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \ } /* For read-write shared bit-per-interrupt registers */ -#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \ - GIC_ACCESSOR_RO_INTR_BIT(off, name) \ +#define _GIC_ACCESSOR_RW_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RO_INTR_BIT(off, name) \ \ static inline void write_gic_##name(unsigned int intr) \ { \ @@ -146,6 +156,14 @@ static inline void change_gic_##name(unsigned int intr, \ } \ } +#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RO_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RO_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name) + +#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RW_INTR_BIT(off, name) \ + _GIC_ACCESSOR_RW_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name) + /* For read-only local bit-per-interrupt registers */ #define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \ GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ @@ -155,10 +173,10 @@ static inline void change_gic_##name(unsigned int intr, \ /* For read-write local bit-per-interrupt registers */ #define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \ - GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ - vl_##name) \ - GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \ - vo_##name) + _GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ + vl_##name) \ + _GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \ + vo_##name) /* GIC_SH_CONFIG - Information about the GIC configuration */ GIC_ACCESSOR_RW(32, 0x000, config) From 9c7a86c935074525f24cc20e78a7d5150e4600e3 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Tue, 9 Jul 2024 00:23:04 +0200 Subject: [PATCH 44/58] MIPS: lantiq: improve USB initialization This adds code to initialize the USB controller and PHY also on Danube, Amazon SE and AR10. This code is based on the Vendor driver from different UGW versions and compared to the hardware documentation. This patch is included in OpenWrt for many years. Signed-off-by: Hauke Mehrtens Signed-off-by: Thomas Bogendoerfer --- arch/mips/lantiq/xway/sysctrl.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 3ed0782252229..5a75283d17f10 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -247,6 +247,25 @@ static void pmu_disable(struct clk *clk) pr_warn("deactivating PMU module failed!"); } +static void usb_set_clock(void) +{ + unsigned int val = ltq_cgu_r32(ifccr); + + if (of_machine_is_compatible("lantiq,ar10") || + of_machine_is_compatible("lantiq,grx390")) { + val &= ~0x03; /* XTAL divided by 3 */ + } else if (of_machine_is_compatible("lantiq,ar9") || + of_machine_is_compatible("lantiq,vr9")) { + /* TODO: this depends on the XTAL frequency */ + val |= 0x03; /* XTAL divided by 3 */ + } else if (of_machine_is_compatible("lantiq,ase")) { + val |= 0x20; /* from XTAL */ + } else if (of_machine_is_compatible("lantiq,danube")) { + val |= 0x30; /* 12 MHz, generated from 36 MHz */ + } + ltq_cgu_w32(val, ifccr); +} + /* the pci enable helper */ static int pci_enable(struct clk *clk) { @@ -588,4 +607,5 @@ void __init ltq_soc_init(void) clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); } + usb_set_clock(); } From 59649de96f21dfb0518faa8feaa3d05c2d81b042 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 12 Jun 2024 09:38:19 +0100 Subject: [PATCH 45/58] MIPS: Implement ieee754 NAN2008 emulation mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement ieee754 NAN2008 emulation mode. When this mode is enabled, kernel will accept ELF file compiled for both NaN 2008 and NaN legacy, but if hardware does not have capability to match ELF's NaN mode, __own_fpu will fail for corresponding thread and fpuemu will then kick in. This mode trade performance for correctness, while maintaining support for both NaN mode regardless of hardware capability. It is useful for multilib installation that have both types of binary exist in system. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- Documentation/admin-guide/kernel-parameters.txt | 4 +++- arch/mips/include/asm/fpu.h | 15 +++++++++++++++ arch/mips/kernel/elf.c | 4 ++++ arch/mips/kernel/fpu-probe.c | 9 ++++++++- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index b600df82669db..c49336b8f0313 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2022,7 +2022,7 @@ for the device. By default it is set to false (0). ieee754= [MIPS] Select IEEE Std 754 conformance mode - Format: { strict | legacy | 2008 | relaxed } + Format: { strict | legacy | 2008 | relaxed | emulated } Default: strict Choose which programs will be accepted for execution @@ -2042,6 +2042,8 @@ by the FPU relaxed accept any binaries regardless of whether supported by the FPU + emulated accept any binaries but enable FPU emulator + if binary mode is unsupported by the FPU. The FPU emulator is always able to support both NaN encodings, so if no FPU hardware is present or it has diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h index 86310d6e10352..bc5ac9887d097 100644 --- a/arch/mips/include/asm/fpu.h +++ b/arch/mips/include/asm/fpu.h @@ -129,6 +129,18 @@ static inline int __own_fpu(void) if (ret) return ret; + if (current->thread.fpu.fcr31 & FPU_CSR_NAN2008) { + if (!cpu_has_nan_2008) { + ret = SIGFPE; + goto failed; + } + } else { + if (!cpu_has_nan_legacy) { + ret = SIGFPE; + goto failed; + } + } + KSTK_STATUS(current) |= ST0_CU1; if (mode == FPU_64BIT || mode == FPU_HYBRID) KSTK_STATUS(current) |= ST0_FR; @@ -137,6 +149,9 @@ static inline int __own_fpu(void) set_thread_flag(TIF_USEDFPU); return 0; +failed: + __disable_fpu(); + return ret; } static inline int own_fpu_inatomic(int restore) diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 7aa2c2360ff60..f0e7fe85a42a7 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -318,6 +318,10 @@ void mips_set_personality_nan(struct arch_elf_state *state) t->thread.fpu.fcr31 = c->fpu_csr31; switch (state->nan_2008) { case 0: + if (!(c->fpu_msk31 & FPU_CSR_NAN2008)) + t->thread.fpu.fcr31 &= ~FPU_CSR_NAN2008; + if (!(c->fpu_msk31 & FPU_CSR_ABS2008)) + t->thread.fpu.fcr31 &= ~FPU_CSR_ABS2008; break; case 1: if (!(c->fpu_msk31 & FPU_CSR_NAN2008)) diff --git a/arch/mips/kernel/fpu-probe.c b/arch/mips/kernel/fpu-probe.c index e689d6a832342..6bf3f19b1c335 100644 --- a/arch/mips/kernel/fpu-probe.c +++ b/arch/mips/kernel/fpu-probe.c @@ -144,7 +144,7 @@ static void cpu_set_fpu_2008(struct cpuinfo_mips *c) * IEEE 754 conformance mode to use. Affects the NaN encoding and the * ABS.fmt/NEG.fmt execution mode. */ -static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; +static enum { STRICT, EMULATED, LEGACY, STD2008, RELAXED } ieee754 = STRICT; /* * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes @@ -160,6 +160,7 @@ static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) switch (ieee754) { case STRICT: + case EMULATED: if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | @@ -204,6 +205,10 @@ static void cpu_set_nan_2008(struct cpuinfo_mips *c) mips_use_nan_legacy = !cpu_has_nan_2008; mips_use_nan_2008 = !!cpu_has_nan_2008; break; + case EMULATED: + /* Pretend ABS2008/NAN2008 options are dynamic */ + c->fpu_msk31 &= ~(FPU_CSR_NAN2008 | FPU_CSR_ABS2008); + fallthrough; case RELAXED: mips_use_nan_legacy = true; mips_use_nan_2008 = true; @@ -226,6 +231,8 @@ static int __init ieee754_setup(char *s) return -1; else if (!strcmp(s, "strict")) ieee754 = STRICT; + else if (!strcmp(s, "emulated")) + ieee754 = EMULATED; else if (!strcmp(s, "legacy")) ieee754 = LEGACY; else if (!strcmp(s, "2008")) From b1428c6860af10649cead288b8fc81efec6115c2 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:15 +1200 Subject: [PATCH 46/58] mips: dts: realtek: use "serial" instead of "uart" in node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the node name for the UARTs to resolve the following dtbs_check complaints: uart@2000: $nodename:0: 'uart@2000' does not match '^serial(@.*)?$' uart@2100: $nodename:0: 'uart@2100' does not match '^serial(@.*)?$' Signed-off-by: Chris Packham Reviewed-by: Marek Behún Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/realtek/rtl83xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi index de65a111b6263..03ddc61f7c9e9 100644 --- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi +++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi @@ -22,7 +22,7 @@ #size-cells = <1>; ranges = <0x0 0x18000000 0x10000>; - uart0: uart@2000 { + uart0: serial@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; @@ -39,7 +39,7 @@ status = "disabled"; }; - uart1: uart@2100 { + uart1: serial@2100 { compatible = "ns16550a"; reg = <0x2100 0x100>; From 75eb0cbe6e2220feffc7c6219b7dc80c56068bb9 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:16 +1200 Subject: [PATCH 47/58] mips: dts: realtek: add device_type property to cpu node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device_type = "cpu" to the cpu node for the rtl838x SoC. This resolves the following dtbs_check complaint: cpus: cpu@0: 'cache-level' is a required property Signed-off-by: Chris Packham Reviewed-by: Marek Behún Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/realtek/rtl838x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index 6cc4ff5c0d198..722106e39194b 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -6,6 +6,7 @@ #size-cells = <0>; cpu@0 { + device_type = "cpu"; compatible = "mips,mips4KEc"; reg = <0>; clocks = <&baseclk 0>; From a9b516f3e92688a3d0f84a4dbaffb2b73b652348 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:17 +1200 Subject: [PATCH 48/58] dt-bindings: vendor-prefixes: Add Cameo Communications Add entry for Cameo Communications (https://www.cameo.com.tw/) Signed-off-by: Chris Packham Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1a..67550f0dd189b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -246,6 +246,8 @@ patternProperties: description: CALAO Systems SAS "^calxeda,.*": description: Calxeda + "^cameo,.*": + description: Cameo Communications, Inc "^canaan,.*": description: Canaan, Inc. "^caninos,.*": From 93eed6356d9ed26011f979ceb613c8ef3963cd10 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:18 +1200 Subject: [PATCH 49/58] dt-bindings: mips: realtek: Add rtl930x-soc compatible Add the rtl9302 SoC and the Cameo RTL9302C_2xRTL8224_2XGE reference board to the list of Realtek compatible strings. Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/realtek-rtl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/realtek-rtl.yaml b/Documentation/devicetree/bindings/mips/realtek-rtl.yaml index f8ac309d2994c..d337655bfbf8e 100644 --- a/Documentation/devicetree/bindings/mips/realtek-rtl.yaml +++ b/Documentation/devicetree/bindings/mips/realtek-rtl.yaml @@ -20,5 +20,9 @@ properties: - enum: - cisco,sg220-26 - const: realtek,rtl8382-soc + - items: + - enum: + - cameo,rtl9302c-2x-rtl8224-2xge + - const: realtek,rtl9302-soc additionalProperties: true From 371c358d523f3e6878587ddb16dd61a4a89bef9e Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:20 +1200 Subject: [PATCH 50/58] dt-bindings: interrupt-controller: realtek,rtl-intc: Add rtl9300-intc Add a compatible string for the interrupt controller found on the rtl930x SoCs. The interrupt controller has registers for VPE1 so these are added as a second reg cell. Signed-off-by: Chris Packham Reviewed-by: Rob Herring (Arm) Signed-off-by: Thomas Bogendoerfer --- .../realtek,rtl-intc.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml index fb5593724059d..833a01cdd1b17 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - realtek,rtl8380-intc + - realtek,rtl9300-intc - const: realtek,rtl-intc - const: realtek,rtl-intc deprecated: true @@ -35,7 +36,10 @@ properties: const: 1 reg: - maxItems: 1 + minItems: 1 + items: + - description: vpe0 registers + - description: vpe1 registers interrupts: minItems: 1 @@ -71,6 +75,20 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: realtek,rtl9300-intc + then: + properties: + reg: + minItems: 2 + maxItems: 2 + else: + properties: + reg: + maxItems: 1 additionalProperties: false From 62b8db3afe3e93dd14baeddf081fe1200d5610e3 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:22 +1200 Subject: [PATCH 51/58] mips: select REALTEK_OTTO_TIMER for Realtek platforms When MACH_REALTEK_RTL is selected automatically select the REALTEK_OTTO_TIMER option in order to support the Realtek platforms that require it. Signed-off-by: Chris Packham Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c14192514e9db..28af3d9e6bc0c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -667,6 +667,7 @@ config MACH_REALTEK_RTL select BOOT_RAW select PINCTRL select USE_OF + select REALTEK_OTTO_TIMER config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" From 662c0002ca2e1379d0e80be1a4e07ab47c9eee48 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:23 +1200 Subject: [PATCH 52/58] mips: generic: add fdt fixup for Realtek reference board The bootloader used on the Realtek RTL9302C boards is an ancient vendor fork of U-Boot that doesn't understand device trees. So to run a modern kernel it is necessary use one of the APPENDED_DTB options. When appending the DTB the inintrd information, if present, needs to be inserted into the /chosen device tree node. The bootloader provides the initrd start/size via the firmware environment. Add a fdt fixup that will update the device tree with the initrd information. Signed-off-by: Chris Packham Signed-off-by: Thomas Bogendoerfer --- arch/mips/generic/Makefile | 1 + arch/mips/generic/board-realtek.c | 79 +++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 arch/mips/generic/board-realtek.c diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile index 56011d738441f..ea0e4ad5e6007 100644 --- a/arch/mips/generic/Makefile +++ b/arch/mips/generic/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o obj-$(CONFIG_MACH_INGENIC) += board-ingenic.o obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o +obj-$(CONFIG_MACH_REALTEK_RTL) += board-realtek.o diff --git a/arch/mips/generic/board-realtek.c b/arch/mips/generic/board-realtek.c new file mode 100644 index 0000000000000..9cce6103d24e0 --- /dev/null +++ b/arch/mips/generic/board-realtek.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Allied Telesis + */ + +#include +#include +#include +#include + +#include +#include + +static __init int realtek_add_initrd(void *fdt) +{ + int node, err; + u32 start, size; + + node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) { + pr_err("/chosen node not found\n"); + return -ENOENT; + } + + start = fw_getenvl("initrd_start"); + size = fw_getenvl("initrd_size"); + + if (start == 0 && size == 0) + return 0; + + pr_info("Adding initrd info from environment\n"); + + err = fdt_setprop_u32(fdt, node, "linux,initrd-start", start); + if (err) { + pr_err("unable to set initrd-start: %d\n", err); + return err; + } + + err = fdt_setprop_u32(fdt, node, "linux,initrd-end", start + size); + if (err) { + pr_err("unable to set initrd-end: %d\n", err); + return err; + } + + return 0; +} + +static const struct mips_fdt_fixup realtek_fdt_fixups[] __initconst = { + { realtek_add_initrd, "add initrd" }, + {}, +}; + +static __init const void *realtek_fixup_fdt(const void *fdt, const void *match_data) +{ + static unsigned char fdt_buf[16 << 10] __initdata; + int err; + + if (fdt_check_header(fdt)) + panic("Corrupt DT"); + + fw_init_cmdline(); + + err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf), fdt, realtek_fdt_fixups); + if (err) + panic("Unable to fixup FDT: %d", err); + + return fdt_buf; + +} + +static const struct of_device_id realtek_of_match[] __initconst = { + { .compatible = "realtek,rtl9302-soc" }, + {} +}; + +MIPS_MACHINE(realtek) = { + .matches = realtek_of_match, + .fixup_fdt = realtek_fixup_fdt, +}; From 74beefb5935a67f9fa60f8103e3f69d42d6a08d7 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 10 Jul 2024 16:35:24 +1200 Subject: [PATCH 53/58] mips: dts: realtek: Add RTL9302C board Add support for the RTL9302 SoC and the RTL9302C_2xRTL8224_2XGE reference board. The RTL930x family of SoCs are Realtek switches with an embedded MIPS core (800MHz 34Kc). Most of the peripherals are similar to the RTL838x SoC and can make use of many existing drivers. Add in full DSA switch support is still a work in progress. Signed-off-by: Chris Packham Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/realtek/Makefile | 1 + .../cameo-rtl9302c-2x-rtl8224-2xge.dts | 73 +++++++++++++++++ arch/mips/boot/dts/realtek/rtl930x.dtsi | 79 +++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts create mode 100644 arch/mips/boot/dts/realtek/rtl930x.dtsi diff --git a/arch/mips/boot/dts/realtek/Makefile b/arch/mips/boot/dts/realtek/Makefile index fba4e93187a60..d2709798763ff 100644 --- a/arch/mips/boot/dts/realtek/Makefile +++ b/arch/mips/boot/dts/realtek/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-y += cisco_sg220-26.dtb +dtb-y += cameo-rtl9302c-2x-rtl8224-2xge.dtb diff --git a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts new file mode 100644 index 0000000000000..77d2566545f26 --- /dev/null +++ b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "rtl930x.dtsi" + +#include +#include +#include +#include + +/ { + compatible = "cameo,rtl9302c-2x-rtl8224-2xge", "realtek,rtl9302-soc"; + model = "RTL9302C Development Board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "LOADER"; + reg = <0x0 0xe0000>; + read-only; + }; + partition@e0000 { + label = "BDINFO"; + reg = <0xe0000 0x10000>; + }; + partition@f0000 { + label = "SYSINFO"; + reg = <0xf0000 0x10000>; + read-only; + }; + partition@100000 { + label = "JFFS2 CFG"; + reg = <0x100000 0x100000>; + }; + partition@200000 { + label = "JFFS2 LOG"; + reg = <0x200000 0x100000>; + }; + partition@300000 { + label = "RUNTIME"; + reg = <0x300000 0xe80000>; + }; + partition@1180000 { + label = "RUNTIME2"; + reg = <0x1180000 0xe80000>; + }; + }; + }; +}; diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi new file mode 100644 index 0000000000000..f271940f82bea --- /dev/null +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + +#include "rtl83xx.dtsi" + +/ { + compatible = "realtek,rtl9302-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips34Kc"; + reg = <0>; + clocks = <&baseclk 0>; + clock-names = "cpu"; + }; + }; + + baseclk: clock-800mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + }; + + lx_clk: clock-175mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <175000000>; + }; +}; + +&soc { + intc: interrupt-controller@3000 { + compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; + reg = <0x3000 0x18>, <0x3018 0x18>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>, <7>; + }; + + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + timer0: timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; + + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; +}; + +&uart0 { + /delete-property/ clock-frequency; + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <30>; +}; + +&uart1 { + /delete-property/ clock-frequency; + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <31>; +}; + From 2326c8f2022636a1e47402ffd09a3b28f737275f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sun, 14 Jul 2024 10:52:57 +0800 Subject: [PATCH 54/58] MIPS: Fix fallback march for SB1 Fallback march for SB1 should be mips64 instead of mips64r1. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202407111851.LwDasTcp-lkp@intel.com/ Fixes: bfc0a330c1b4 ("MIPS: Fallback CPU -march flag to ISA level if unsupported") Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 80aecba248922..5785a3d5ccfbb 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -170,7 +170,7 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64r1) \ +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64) \ -Wa,--trap cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) From 9ce4250eeed47d732015c459726fc2c32481395f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sun, 14 Jul 2024 10:20:47 +0800 Subject: [PATCH 55/58] MIPS: config: Enable MSA and virtualization for MIPS64R6 All MIPS64R6 cores so far supports MSA and vz, so it makes sense to enable them in 64R6 default config. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/generic/64r6.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/configs/generic/64r6.config b/arch/mips/configs/generic/64r6.config index 5dd8e8503e34b..63b4e95f303de 100644 --- a/arch/mips/configs/generic/64r6.config +++ b/arch/mips/configs/generic/64r6.config @@ -3,4 +3,6 @@ CONFIG_64BIT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y +CONFIG_CPU_HAS_MSA=y CONFIG_CRYPTO_CRC32_MIPS=y +CONFIG_VIRTUALIZATION=y From 10f338bd0a42140d8a18a31c89309c5a03e38fc2 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sun, 14 Jul 2024 10:20:48 +0800 Subject: [PATCH 56/58] MIPS: config: generic: Add board-litex The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs. We have implemented LiteX support for a couple of opensource MIPS CPU cores including microAptiv UP from MIPS, GS232 from Loongson, and CDIM from CQU. For this platform, devicetree is generated by litex python scripts so there is no devicetree addition necessary. Link: https://github.com/enjoy-digital/litex/pull/1990 Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/generic/board-litex.config | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/mips/configs/generic/board-litex.config diff --git a/arch/mips/configs/generic/board-litex.config b/arch/mips/configs/generic/board-litex.config new file mode 100644 index 0000000000000..f372d0647bfc5 --- /dev/null +++ b/arch/mips/configs/generic/board-litex.config @@ -0,0 +1,8 @@ +CONFIG_LITEX_LITEETH=y +CONFIG_SERIAL_LITEUART=y +CONFIG_SERIAL_LITEUART_CONSOLE=y +CONFIG_MMC=y +CONFIG_MMC_LITEX=y +CONFIG_LITEX_SOC_CONTROLLER=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y From 31ebd6e11f2450f20317e399b08680a80cbff484 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sun, 14 Jul 2024 10:20:49 +0800 Subject: [PATCH 57/58] MIPS: config: lemote2f: Regenerate defconfig Regenerate defconfig to include some drivers that are used by this platform, including sm712fb, simplefb, rtl8187. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/lemote2f_defconfig | 54 ++++++++++++---------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index 3389e6e885d9f..71d6340497c96 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -12,15 +12,14 @@ CONFIG_LOG_BUF_SHIFT=15 CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_PROFILING=y +CONFIG_KEXEC=y CONFIG_MACH_LOONGSON2EF=y CONFIG_LEMOTE_MACH2F=y -CONFIG_KEXEC=y -# CONFIG_SECCOMP is not set -CONFIG_PCI=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_HIBERNATION=y CONFIG_PM_STD_PARTITION="/dev/hda3" +# CONFIG_SECCOMP is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y @@ -68,10 +67,10 @@ CONFIG_BT_HIDP=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIVHCI=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m +CONFIG_CFG80211=y +CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y -CONFIG_RFKILL=m +CONFIG_RFKILL=y CONFIG_RFKILL_INPUT=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y @@ -83,13 +82,10 @@ CONFIG_ATA=y CONFIG_PATA_AMD=y CONFIG_MD=y CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m CONFIG_MD_RAID10=m CONFIG_MD_RAID456=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m CONFIG_BLK_DEV_DM=m CONFIG_DM_DEBUG=y CONFIG_DM_CRYPT=m @@ -112,6 +108,10 @@ CONFIG_8139TOO=y CONFIG_R8169=y CONFIG_USB_USBNET=m CONFIG_USB_NET_CDC_EEM=m +CONFIG_RTL8180=m +CONFIG_RTL8187=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8XXXU=m CONFIG_INPUT_EVDEV=y # CONFIG_MOUSE_PS2_ALPS is not set # CONFIG_MOUSE_PS2_LOGIPS2PP is not set @@ -119,27 +119,27 @@ CONFIG_INPUT_EVDEV=y CONFIG_MOUSE_APPLETOUCH=m # CONFIG_SERIO_SERPORT is not set CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_NONSTANDARD=y CONFIG_SERIAL_8250=m # CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_NR_UARTS=16 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_FOURPORT=y +CONFIG_SERIAL_NONSTANDARD=y CONFIG_HW_RANDOM=y CONFIG_GPIO_LOONGSON=y CONFIG_THERMAL=y CONFIG_MEDIA_SUPPORT=m CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y CONFIG_FB_SIS=y CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y -# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_FB_SIMPLE=y +CONFIG_FB_SM712=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_LOGO=y @@ -238,7 +238,6 @@ CONFIG_BTRFS_FS=m CONFIG_QUOTA=y CONFIG_QFMT_V2=m CONFIG_AUTOFS_FS=m -CONFIG_NETFS_SUPPORT=m CONFIG_FSCACHE=y CONFIG_CACHEFILES=m CONFIG_ISO9660_FS=m @@ -247,7 +246,6 @@ CONFIG_ZISOFS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_CRAMFS=m @@ -299,29 +297,23 @@ CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=y CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_LZO=m CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_6x11=y From bb2d63500b5c8fd1ea425caffe2d44c931fefc6b Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sun, 14 Jul 2024 10:20:50 +0800 Subject: [PATCH 58/58] MIPS: config: Add ip30_defconfig Add ip30_defconfig derived from ip27_defconfig to ensure this target is build tested by various kernel testing projects. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/ip30_defconfig | 183 +++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 arch/mips/configs/ip30_defconfig diff --git a/arch/mips/configs/ip30_defconfig b/arch/mips/configs/ip30_defconfig new file mode 100644 index 0000000000000..178d61645ceaf --- /dev/null +++ b/arch/mips/configs/ip30_defconfig @@ -0,0 +1,183 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_CGROUPS=y +CONFIG_CPUSETS=y +CONFIG_RELAY=y +CONFIG_EXPERT=y +CONFIG_SGI_IP30=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_HZ_1000=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_PM=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_SGI_PARTITION=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SKBEDIT=m +# CONFIG_VGA_ARB is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SCSI_FC_ATTRS=y +CONFIG_LIBFC=m +CONFIG_SCSI_QLOGIC_1280=y +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_SGI_IOC3_ETH=y +CONFIG_INPUT_SPARSEKMAP=y +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_EVDEV=y +CONFIG_SERIO_SGI_IOC3=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_VT is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_IOC3=y +CONFIG_NOZOMI=m +CONFIG_HW_RANDOM_TIMERIOMEM=m +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_SGI_MFD_IOC3=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_M48T35=y +CONFIG_UIO=y +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_SQUASHFS=m +CONFIG_OMFS_FS=m +CONFIG_NFS_FS=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZO=m +CONFIG_CRC_T10DIF=m