From 100b54e47162d07a931236073b31602284670e7d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:27 +0200 Subject: [PATCH 001/118] pinctrl: intel: Introduce INTEL_COMMUNITY_*() to unify community macros Now it becomes visible that we can deduplicate SoC specific *_COMMUNITY() macros across the Intel pin control drivers. For that, introduce a common INTEL_COMMUNITY_GPPS() and INTEL_COMMUNITY_SIZE() macros in the pinctrl-intel.h. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 65628423bf639..b0f2be4c1fd1c 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -143,6 +143,28 @@ struct intel_community { #define PINCTRL_FEATURE_BLINK BIT(4) #define PINCTRL_FEATURE_EXP BIT(5) +#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \ + { \ + .barno = (b), \ + .padown_offset = soc ## _PAD_OWN, \ + .padcfglock_offset = soc ## _PADCFGLOCK, \ + .hostown_offset = soc ## _HOSTSW_OWN, \ + .is_offset = soc ## _GPI_IS, \ + .ie_offset = soc ## _GPI_IE, \ + .gpp_size = (gs), \ + .gpp_num_padown_regs = (gn), \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = (n), \ + } + +#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \ + __INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc) + +#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \ + __INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc) + /** * PIN_GROUP - Declare a pin group * @n: Name of the group From 6b432d13ea1abce513f34b18a4c4c9e5390e1cea Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:28 +0200 Subject: [PATCH 002/118] pinctrl: alderlake: Replace ADL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom ADL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-alderlake.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index 427febe09b698..55bbfd647ba41 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -34,25 +34,11 @@ .gpio_base = (g), \ } -#define ADL_COMMUNITY(b, s, e, g, v) \ - { \ - .barno = (b), \ - .padown_offset = ADL_##v##_PAD_OWN, \ - .padcfglock_offset = ADL_##v##_PADCFGLOCK, \ - .hostown_offset = ADL_##v##_HOSTSW_OWN, \ - .is_offset = ADL_##v##_GPI_IS, \ - .ie_offset = ADL_##v##_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } - #define ADL_N_COMMUNITY(b, s, e, g) \ - ADL_COMMUNITY(b, s, e, g, N) + INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N) #define ADL_S_COMMUNITY(b, s, e, g) \ - ADL_COMMUNITY(b, s, e, g, S) + INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_S) /* Alder Lake-N */ static const struct pinctrl_pin_desc adln_pins[] = { From 7466214413d11f4b2fd2b0c8616d20cdeba1b3f1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:29 +0200 Subject: [PATCH 003/118] pinctrl: broxton: Replace BXT_COMMUNITY() by INTEL_COMMUNITY_SIZE() Use INTEL_COMMUNITY_SIZE() common macro instead custom BXT_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-broxton.c | 31 +++++++++---------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index fb15cd10a32f6..77e921b2178d5 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -20,17 +20,8 @@ #define BXT_GPI_IS 0x100 #define BXT_GPI_IE 0x110 -#define BXT_COMMUNITY(s, e) \ - { \ - .padown_offset = BXT_PAD_OWN, \ - .padcfglock_offset = BXT_PADCFGLOCK, \ - .hostown_offset = BXT_HOSTSW_OWN, \ - .is_offset = BXT_GPI_IS, \ - .ie_offset = BXT_GPI_IE, \ - .gpp_size = 32, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - } +#define BXT_COMMUNITY(b, s, e) \ + INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, BXT) /* BXT */ static const struct pinctrl_pin_desc bxt_north_pins[] = { @@ -172,7 +163,7 @@ static const struct intel_function bxt_north_functions[] = { }; static const struct intel_community bxt_north_communities[] = { - BXT_COMMUNITY(0, 82), + BXT_COMMUNITY(0, 0, 82), }; static const struct intel_pinctrl_soc_data bxt_north_soc_data = { @@ -289,7 +280,7 @@ static const struct intel_function bxt_northwest_functions[] = { }; static const struct intel_community bxt_northwest_communities[] = { - BXT_COMMUNITY(0, 71), + BXT_COMMUNITY(0, 0, 71), }; static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = { @@ -396,7 +387,7 @@ static const struct intel_function bxt_west_functions[] = { }; static const struct intel_community bxt_west_communities[] = { - BXT_COMMUNITY(0, 41), + BXT_COMMUNITY(0, 0, 41), }; static const struct intel_pinctrl_soc_data bxt_west_soc_data = { @@ -472,7 +463,7 @@ static const struct intel_function bxt_southwest_functions[] = { }; static const struct intel_community bxt_southwest_communities[] = { - BXT_COMMUNITY(0, 30), + BXT_COMMUNITY(0, 0, 30), }; static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = { @@ -511,7 +502,7 @@ static const struct pinctrl_pin_desc bxt_south_pins[] = { }; static const struct intel_community bxt_south_communities[] = { - BXT_COMMUNITY(0, 19), + BXT_COMMUNITY(0, 0, 19), }; static const struct intel_pinctrl_soc_data bxt_south_soc_data = { @@ -650,7 +641,7 @@ static const struct intel_function apl_north_functions[] = { }; static const struct intel_community apl_north_communities[] = { - BXT_COMMUNITY(0, 77), + BXT_COMMUNITY(0, 0, 77), }; static const struct intel_pinctrl_soc_data apl_north_soc_data = { @@ -770,7 +761,7 @@ static const struct intel_function apl_northwest_functions[] = { }; static const struct intel_community apl_northwest_communities[] = { - BXT_COMMUNITY(0, 76), + BXT_COMMUNITY(0, 0, 76), }; static const struct intel_pinctrl_soc_data apl_northwest_soc_data = { @@ -880,7 +871,7 @@ static const struct intel_function apl_west_functions[] = { }; static const struct intel_community apl_west_communities[] = { - BXT_COMMUNITY(0, 46), + BXT_COMMUNITY(0, 0, 46), }; static const struct intel_pinctrl_soc_data apl_west_soc_data = { @@ -972,7 +963,7 @@ static const struct intel_function apl_southwest_functions[] = { }; static const struct intel_community apl_southwest_communities[] = { - BXT_COMMUNITY(0, 42), + BXT_COMMUNITY(0, 0, 42), }; static const struct intel_pinctrl_soc_data apl_southwest_soc_data = { From 31044d8ec8b7d66d3184c5385b14d101b6723f28 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:30 +0200 Subject: [PATCH 004/118] pinctrl: cannonlake: Replace CNL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom CNL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cannonlake.c | 31 ++++++++-------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index f8a8b9b14de94..88142ec57b258 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -15,12 +15,17 @@ #include "pinctrl-intel.h" -#define CNL_PAD_OWN 0x020 -#define CNL_PADCFGLOCK 0x080 +#define CNL_LP_PAD_OWN 0x020 +#define CNL_LP_PADCFGLOCK 0x080 #define CNL_LP_HOSTSW_OWN 0x0b0 +#define CNL_LP_GPI_IS 0x100 +#define CNL_LP_GPI_IE 0x120 + +#define CNL_H_PAD_OWN 0x020 +#define CNL_H_PADCFGLOCK 0x080 #define CNL_H_HOSTSW_OWN 0x0c0 -#define CNL_GPI_IS 0x100 -#define CNL_GPI_IE 0x120 +#define CNL_H_GPI_IS 0x100 +#define CNL_H_GPI_IE 0x120 #define CNL_GPP(r, s, e, g) \ { \ @@ -30,25 +35,11 @@ .gpio_base = (g), \ } -#define CNL_COMMUNITY(b, s, e, g, v) \ - { \ - .barno = (b), \ - .padown_offset = CNL_PAD_OWN, \ - .padcfglock_offset = CNL_PADCFGLOCK, \ - .hostown_offset = CNL_##v##_HOSTSW_OWN, \ - .is_offset = CNL_GPI_IS, \ - .ie_offset = CNL_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } - #define CNL_LP_COMMUNITY(b, s, e, g) \ - CNL_COMMUNITY(b, s, e, g, LP) + INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP) #define CNL_H_COMMUNITY(b, s, e, g) \ - CNL_COMMUNITY(b, s, e, g, H) + INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_H) /* Cannon Lake-H */ static const struct pinctrl_pin_desc cnlh_pins[] = { From e83d7ef0298283cd8f50960dd5256b7b09133103 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:31 +0200 Subject: [PATCH 005/118] pinctrl: cedarfork: Replace CDF_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom CDF_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cedarfork.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c index aa6f9040d3d89..2ab52b1fbc597 100644 --- a/drivers/pinctrl/intel/pinctrl-cedarfork.c +++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c @@ -28,18 +28,7 @@ } #define CDF_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = CDF_PAD_OWN, \ - .padcfglock_offset = CDF_PADCFGLOCK, \ - .hostown_offset = CDF_HOSTSW_OWN, \ - .is_offset = CDF_GPI_IS, \ - .ie_offset = CDF_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + INTEL_COMMUNITY_GPPS(b, s, e, g, CDF) /* Cedar Fork PCH */ static const struct pinctrl_pin_desc cdf_pins[] = { From 3cbb3c4b98524fc58388e5e9765d40f3720a414a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:32 +0200 Subject: [PATCH 006/118] pinctrl: denverton: Replace DNV_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom DNV_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-denverton.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index f26d030b9b411..c1a9db091c6e7 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -28,18 +28,7 @@ } #define DNV_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = DNV_PAD_OWN, \ - .padcfglock_offset = DNV_PADCFGLOCK, \ - .hostown_offset = DNV_HOSTSW_OWN, \ - .is_offset = DNV_GPI_IS, \ - .ie_offset = DNV_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + INTEL_COMMUNITY_GPPS(b, s, e, g, DNV) /* Denverton */ static const struct pinctrl_pin_desc dnv_pins[] = { From d83bc222202095b12db0a5b43ba880a1ed91a30a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:33 +0200 Subject: [PATCH 007/118] pinctrl: elkhartlake: Replace EHL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom EHL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-elkhartlake.c | 24 ++++++--------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c index 4702bdfa10e31..64b1997df0bef 100644 --- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -27,18 +27,8 @@ .size = ((e) - (s) + 1), \ } -#define EHL_COMMUNITY(s, e, g) \ - { \ - .padown_offset = EHL_PAD_OWN, \ - .padcfglock_offset = EHL_PADCFGLOCK, \ - .hostown_offset = EHL_HOSTSW_OWN, \ - .is_offset = EHL_GPI_IS, \ - .ie_offset = EHL_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } +#define EHL_COMMUNITY(b, s, e, g) \ + INTEL_COMMUNITY_GPPS(b, s, e, g, EHL) /* Elkhart Lake */ static const struct pinctrl_pin_desc ehl_community0_pins[] = { @@ -121,7 +111,7 @@ static const struct intel_padgroup ehl_community0_gpps[] = { }; static const struct intel_community ehl_community0[] = { - EHL_COMMUNITY(0, 66, ehl_community0_gpps), + EHL_COMMUNITY(0, 0, 66, ehl_community0_gpps), }; static const struct intel_pinctrl_soc_data ehl_community0_soc_data = { @@ -262,7 +252,7 @@ static const struct intel_padgroup ehl_community1_gpps[] = { }; static const struct intel_community ehl_community1[] = { - EHL_COMMUNITY(0, 112, ehl_community1_gpps), + EHL_COMMUNITY(0, 0, 112, ehl_community1_gpps), }; static const struct intel_pinctrl_soc_data ehl_community1_soc_data = { @@ -335,7 +325,7 @@ static const struct intel_padgroup ehl_community3_gpps[] = { }; static const struct intel_community ehl_community3[] = { - EHL_COMMUNITY(0, 46, ehl_community3_gpps), + EHL_COMMUNITY(0, 0, 46, ehl_community3_gpps), }; static const struct intel_pinctrl_soc_data ehl_community3_soc_data = { @@ -441,7 +431,7 @@ static const struct intel_padgroup ehl_community4_gpps[] = { }; static const struct intel_community ehl_community4[] = { - EHL_COMMUNITY(0, 79, ehl_community4_gpps), + EHL_COMMUNITY(0, 0, 79, ehl_community4_gpps), }; static const struct intel_pinctrl_soc_data ehl_community4_soc_data = { @@ -469,7 +459,7 @@ static const struct intel_padgroup ehl_community5_gpps[] = { }; static const struct intel_community ehl_community5[] = { - EHL_COMMUNITY(0, 7, ehl_community5_gpps), + EHL_COMMUNITY(0, 0, 7, ehl_community5_gpps), }; static const struct intel_pinctrl_soc_data ehl_community5_soc_data = { From 902b266edcf61c67ebb71080358c5c7fe2aa31ad Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:34 +0200 Subject: [PATCH 008/118] pinctrl: emmitsburg: Replace EBG_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom EBG_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-emmitsburg.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-emmitsburg.c b/drivers/pinctrl/intel/pinctrl-emmitsburg.c index f6114dbf75200..cc8f0baabc915 100644 --- a/drivers/pinctrl/intel/pinctrl-emmitsburg.c +++ b/drivers/pinctrl/intel/pinctrl-emmitsburg.c @@ -28,18 +28,7 @@ } #define EBG_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = EBG_PAD_OWN, \ - .padcfglock_offset = EBG_PADCFGLOCK, \ - .hostown_offset = EBG_HOSTSW_OWN, \ - .is_offset = EBG_GPI_IS, \ - .ie_offset = EBG_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + INTEL_COMMUNITY_GPPS(b, s, e, g, EBG) /* Emmitsburg */ static const struct pinctrl_pin_desc ebg_pins[] = { From f4cf30886ab1c447231ead686ef7d16080e5ad39 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:35 +0200 Subject: [PATCH 009/118] pinctrl: geminilake: Replace GLK_COMMUNITY() by INTEL_COMMUNITY_SIZE() Use INTEL_COMMUNITY_SIZE() common macro instead custom GLK_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-geminilake.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c index df02028b40f3d..918cc9f261cf1 100644 --- a/drivers/pinctrl/intel/pinctrl-geminilake.c +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -20,17 +20,8 @@ #define GLK_GPI_IS 0x100 #define GLK_GPI_IE 0x110 -#define GLK_COMMUNITY(s, e) \ - { \ - .padown_offset = GLK_PAD_OWN, \ - .padcfglock_offset = GLK_PADCFGLOCK, \ - .hostown_offset = GLK_HOSTSW_OWN, \ - .is_offset = GLK_GPI_IS, \ - .ie_offset = GLK_GPI_IE, \ - .gpp_size = 32, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - } +#define GLK_COMMUNITY(b, s, e) \ + INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK) /* GLK */ static const struct pinctrl_pin_desc glk_northwest_pins[] = { @@ -173,7 +164,7 @@ static const struct intel_function glk_northwest_functions[] = { }; static const struct intel_community glk_northwest_communities[] = { - GLK_COMMUNITY(0, 79), + GLK_COMMUNITY(0, 0, 79), }; static const struct intel_pinctrl_soc_data glk_northwest_soc_data = { @@ -306,7 +297,7 @@ static const struct intel_function glk_north_functions[] = { }; static const struct intel_community glk_north_communities[] = { - GLK_COMMUNITY(0, 79), + GLK_COMMUNITY(0, 0, 79), }; static const struct intel_pinctrl_soc_data glk_north_soc_data = { @@ -345,7 +336,7 @@ static const struct pinctrl_pin_desc glk_audio_pins[] = { }; static const struct intel_community glk_audio_communities[] = { - GLK_COMMUNITY(0, 19), + GLK_COMMUNITY(0, 0, 19), }; static const struct intel_pinctrl_soc_data glk_audio_soc_data = { @@ -427,7 +418,7 @@ static const struct intel_function glk_scc_functions[] = { }; static const struct intel_community glk_scc_communities[] = { - GLK_COMMUNITY(0, 34), + GLK_COMMUNITY(0, 0, 34), }; static const struct intel_pinctrl_soc_data glk_scc_soc_data = { From 3df5f0043de833c45d2645da3d63d9e1b4daac0d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:36 +0200 Subject: [PATCH 010/118] pinctrl: icelake: Replace ICL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom ICL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-icelake.c | 35 +++++++++---------------- 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 84a56d9ae47ea..1c64b4a1c4917 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -15,12 +15,17 @@ #include "pinctrl-intel.h" -#define ICL_PAD_OWN 0x020 -#define ICL_PADCFGLOCK 0x080 -#define ICL_HOSTSW_OWN 0x0b0 -#define ICL_GPI_IS 0x100 -#define ICL_LP_GPI_IE 0x110 -#define ICL_N_GPI_IE 0x120 +#define ICL_LP_PAD_OWN 0x020 +#define ICL_LP_PADCFGLOCK 0x080 +#define ICL_LP_HOSTSW_OWN 0x0b0 +#define ICL_LP_GPI_IS 0x100 +#define ICL_LP_GPI_IE 0x110 + +#define ICL_N_PAD_OWN 0x020 +#define ICL_N_PADCFGLOCK 0x080 +#define ICL_N_HOSTSW_OWN 0x0b0 +#define ICL_N_GPI_IS 0x100 +#define ICL_N_GPI_IE 0x120 #define ICL_GPP(r, s, e, g) \ { \ @@ -30,25 +35,11 @@ .gpio_base = (g), \ } -#define ICL_COMMUNITY(b, s, e, g, v) \ - { \ - .barno = (b), \ - .padown_offset = ICL_PAD_OWN, \ - .padcfglock_offset = ICL_PADCFGLOCK, \ - .hostown_offset = ICL_HOSTSW_OWN, \ - .is_offset = ICL_GPI_IS, \ - .ie_offset = ICL_##v##_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } - #define ICL_LP_COMMUNITY(b, s, e, g) \ - ICL_COMMUNITY(b, s, e, g, LP) + INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP) #define ICL_N_COMMUNITY(b, s, e, g) \ - ICL_COMMUNITY(b, s, e, g, N) + INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_N) /* Ice Lake-LP */ static const struct pinctrl_pin_desc icllp_pins[] = { From 6ab57fb3f1f8c6d039f4ba72f404ab5aced1904c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:37 +0200 Subject: [PATCH 011/118] pinctrl: jasperlake: Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom JSL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-jasperlake.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index ec435b7ab392e..086ab7fe08dd9 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -29,18 +29,7 @@ } #define JSL_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = JSL_PAD_OWN, \ - .padcfglock_offset = JSL_PADCFGLOCK, \ - .hostown_offset = JSL_HOSTSW_OWN, \ - .is_offset = JSL_GPI_IS, \ - .ie_offset = JSL_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + INTEL_COMMUNITY_GPPS(b, s, e, g, JSL) /* Jasper Lake */ static const struct pinctrl_pin_desc jsl_pins[] = { From 4bc3e4313e28316e1d1255cddf584e438d9f6a26 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:38 +0200 Subject: [PATCH 012/118] pinctrl: lakefield: Replace LKF_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom LKF_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lakefield.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c index 3c6283c4827fc..8dac2d6012b10 100644 --- a/drivers/pinctrl/intel/pinctrl-lakefield.c +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -29,18 +29,7 @@ } #define LKF_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = LKF_PAD_OWN, \ - .padcfglock_offset = LKF_PADCFGLOCK, \ - .hostown_offset = LKF_HOSTSW_OWN, \ - .is_offset = LKF_GPI_IS, \ - .ie_offset = LKF_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + INTEL_COMMUNITY_GPPS(b, s, e, g, LKF) /* Lakefield */ static const struct pinctrl_pin_desc lkf_pins[] = { From 6a0662636cdd77ee8b90783a94626c6c8a6b8271 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:39 +0200 Subject: [PATCH 013/118] pinctrl: lewisburg: Replace LBG_COMMUNITY() by INTEL_COMMUNITY_SIZE() Use INTEL_COMMUNITY_SIZE() common macro instead custom LBG_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lewisburg.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c index ad4b446d588e6..7aac1bbde2e9f 100644 --- a/drivers/pinctrl/intel/pinctrl-lewisburg.c +++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c @@ -21,17 +21,7 @@ #define LBG_GPI_IE 0x110 #define LBG_COMMUNITY(b, s, e) \ - { \ - .barno = (b), \ - .padown_offset = LBG_PAD_OWN, \ - .padcfglock_offset = LBG_PADCFGLOCK, \ - .hostown_offset = LBG_HOSTSW_OWN, \ - .is_offset = LBG_GPI_IS, \ - .ie_offset = LBG_GPI_IE, \ - .gpp_size = 24, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - } + INTEL_COMMUNITY_SIZE(b, s, e, 24, 3, LBG) /* Lewisburg */ static const struct pinctrl_pin_desc lbg_pins[] = { From 1c96fa614c18fdb090cd075d81112e5612373698 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:40 +0200 Subject: [PATCH 014/118] pinctrl: meteorlake: Replace MTL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom MTL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-meteorlake.c | 23 ++++++---------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-meteorlake.c b/drivers/pinctrl/intel/pinctrl-meteorlake.c index 9576dcd1cb299..a82f6754c45bf 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorlake.c +++ b/drivers/pinctrl/intel/pinctrl-meteorlake.c @@ -14,11 +14,11 @@ #include "pinctrl-intel.h" -#define MTL_PAD_OWN 0x0b0 -#define MTL_PADCFGLOCK 0x110 -#define MTL_HOSTSW_OWN 0x140 -#define MTL_GPI_IS 0x200 -#define MTL_GPI_IE 0x210 +#define MTL_P_PAD_OWN 0x0b0 +#define MTL_P_PADCFGLOCK 0x110 +#define MTL_P_HOSTSW_OWN 0x140 +#define MTL_P_GPI_IS 0x200 +#define MTL_P_GPI_IE 0x210 #define MTL_GPP(r, s, e, g) \ { \ @@ -29,18 +29,7 @@ } #define MTL_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = MTL_PAD_OWN, \ - .padcfglock_offset = MTL_PADCFGLOCK, \ - .hostown_offset = MTL_HOSTSW_OWN, \ - .is_offset = MTL_GPI_IS, \ - .ie_offset = MTL_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P) /* Meteor Lake-P */ static const struct pinctrl_pin_desc mtlp_pins[] = { From f72a86236a6b84dcea8007115dea486007a482da Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:41 +0200 Subject: [PATCH 015/118] pinctrl: tigerlake: Replace TGL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom TGL_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 30 ++++++++--------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 431352fa2ab52..6e3a651d12417 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -15,13 +15,17 @@ #include "pinctrl-intel.h" -#define TGL_PAD_OWN 0x020 +#define TGL_LP_PAD_OWN 0x020 #define TGL_LP_PADCFGLOCK 0x080 -#define TGL_H_PADCFGLOCK 0x090 #define TGL_LP_HOSTSW_OWN 0x0b0 +#define TGL_LP_GPI_IS 0x100 +#define TGL_LP_GPI_IE 0x120 + +#define TGL_H_PAD_OWN 0x020 +#define TGL_H_PADCFGLOCK 0x090 #define TGL_H_HOSTSW_OWN 0x0c0 -#define TGL_GPI_IS 0x100 -#define TGL_GPI_IE 0x120 +#define TGL_H_GPI_IS 0x100 +#define TGL_H_GPI_IE 0x120 #define TGL_GPP(r, s, e, g) \ { \ @@ -31,25 +35,11 @@ .gpio_base = (g), \ } -#define TGL_COMMUNITY(b, s, e, g, v) \ - { \ - .barno = (b), \ - .padown_offset = TGL_PAD_OWN, \ - .padcfglock_offset = TGL_##v##_PADCFGLOCK, \ - .hostown_offset = TGL_##v##_HOSTSW_OWN, \ - .is_offset = TGL_GPI_IS, \ - .ie_offset = TGL_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } - #define TGL_LP_COMMUNITY(b, s, e, g) \ - TGL_COMMUNITY(b, s, e, g, LP) + INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP) #define TGL_H_COMMUNITY(b, s, e, g) \ - TGL_COMMUNITY(b, s, e, g, H) + INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H) /* Tiger Lake-LP */ static const struct pinctrl_pin_desc tgllp_pins[] = { From df8467df2e65d4e6d103169d62e079f73c7db144 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:42 +0200 Subject: [PATCH 016/118] pinctrl: sunrisepoint: Replace SPT_COMMUNITY() by INTEL_COMMUNITY_*() Use INTEL_COMMUNITY_*() common macro instead custom SPT_COMMUNITY(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 37 +++++++------------- 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 292b660067e97..f91e27feb7c37 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -15,31 +15,17 @@ #include "pinctrl-intel.h" -#define SPT_PAD_OWN 0x020 +#define SPT_H_PAD_OWN 0x020 #define SPT_H_PADCFGLOCK 0x090 -#define SPT_LP_PADCFGLOCK 0x0a0 -#define SPT_HOSTSW_OWN 0x0d0 -#define SPT_GPI_IS 0x100 -#define SPT_GPI_IE 0x120 - -#define SPT_COMMUNITY(b, s, e, g, n, v, gs, gn) \ - { \ - .barno = (b), \ - .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_##v##_PADCFGLOCK, \ - .hostown_offset = SPT_HOSTSW_OWN, \ - .is_offset = SPT_GPI_IS, \ - .ie_offset = SPT_GPI_IE, \ - .gpp_size = (gs), \ - .gpp_num_padown_regs = (gn), \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = (n), \ - } +#define SPT_H_HOSTSW_OWN 0x0d0 +#define SPT_H_GPI_IS 0x100 +#define SPT_H_GPI_IE 0x120 -#define SPT_LP_COMMUNITY(b, s, e) \ - SPT_COMMUNITY(b, s, e, NULL, 0, LP, 24, 4) +#define SPT_LP_PAD_OWN 0x020 +#define SPT_LP_PADCFGLOCK 0x0a0 +#define SPT_LP_HOSTSW_OWN 0x0d0 +#define SPT_LP_GPI_IS 0x100 +#define SPT_LP_GPI_IE 0x120 #define SPT_H_GPP(r, s, e, g) \ { \ @@ -50,7 +36,10 @@ } #define SPT_H_COMMUNITY(b, s, e, g) \ - SPT_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), H, 0, 0) + INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H) + +#define SPT_LP_COMMUNITY(b, s, e) \ + INTEL_COMMUNITY_SIZE(b, s, e, 24, 4, SPT_LP) /* Sunrisepoint-LP */ static const struct pinctrl_pin_desc sptlp_pins[] = { From cd025b1c31432575b7aaa73dce9e5af189795a83 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:26:43 +0200 Subject: [PATCH 017/118] pinctrl: intel: Always use gpp_num_padown_regs in the main driver For the size-based communities, always use gpp_num_padown_regs, which is now provided explicitly via INTEL_COMMUNITY_SIZE() macro. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 9 +-------- drivers/pinctrl/intel/pinctrl-intel.h | 13 +++++++------ 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index cc3aaba241882..4029891ba6282 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1451,14 +1451,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, gpps[i].gpio_base = gpps[i].base; gpps[i].padown_num = padown_num; - /* - * In older hardware the number of padown registers per - * group is fixed regardless of the group size. - */ - if (community->gpp_num_padown_regs) - padown_num += community->gpp_num_padown_regs; - else - padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); + padown_num += community->gpp_num_padown_regs; } community->ngpps = ngpps; diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index b0f2be4c1fd1c..981c1f520f13a 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -96,8 +96,7 @@ enum { * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. * @gpp_num_padown_regs: Number of pad registers each pad group consumes at - * minimum. Use %0 if the number of registers can be - * determined by the size of the group. + * minimum. Used when @gpps is %NULL. * @gpps: Pad groups if the controller has variable size pad groups * @ngpps: Number of pad groups in this community * @pad_map: Optional non-linear mapping of the pads @@ -106,11 +105,13 @@ enum { * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * - * In some of Intel GPIO host controllers this driver supports each pad group + * In older Intel GPIO host controllers, this driver supports, each pad group * is of equal size (except the last one). In that case the driver can just - * fill in @gpp_size field and let the core driver to handle the rest. If - * the controller has pad groups of variable size the client driver can - * pass custom @gpps and @ngpps instead. + * fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver + * to handle the rest. + * + * In newer Intel GPIO host controllers each pad group is of variable size, + * so the client driver can pass custom @gpps and @ngpps instead. */ struct intel_community { unsigned int barno; From 4019bd6d8163a4d0d2e9c74e37243ddcf9a79480 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:27:22 +0200 Subject: [PATCH 018/118] pinctrl: intel: Convert to generic_handle_domain_irq() Replace construct that matches generic_handle_irq(irq_find_mapping()) to a single call to generic_handle_domain_irq(). Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 4029891ba6282..8181a65fb8153 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1215,13 +1215,8 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, /* Only interrupts that are enabled */ pending &= enabled; - for_each_set_bit(gpp_offset, &pending, padgrp->size) { - unsigned int irq; - - irq = irq_find_mapping(gc->irq.domain, - padgrp->gpio_base + gpp_offset); - generic_handle_irq(irq); - } + for_each_set_bit(gpp_offset, &pending, padgrp->size) + generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset); ret += pending ? 1 : 0; } From 61ef0e49f9cb350b522e27c55401bfd23d5ea2bb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:32:05 +0200 Subject: [PATCH 019/118] pinctrl: intel: Add default case to intel_config_set_pull() For the sake of symmetry with intel_config_get_pull(), add a default case to the outer switch. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 8181a65fb8153..4b1d5a21aa681 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -758,6 +758,10 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, } break; + + default: + ret = -EINVAL; + break; } if (!ret) From cd535346d4363dedaf1b4c7ba071768287817ccb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:32:06 +0200 Subject: [PATCH 020/118] pinctrl: intel: Deduplicate some code in intel_config_set_pull() First part is to assign default argument for all cases, since bias disablement doesn't use it anyway. Second part is to clear all bits in the bias setting and depending on the argument and parameter set them as asked. While at it, add break statement to the default cases. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 4b1d5a21aa681..4a0f7412b6e7b 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -691,21 +691,17 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, raw_spin_lock_irqsave(&pctrl->lock, flags); value = readl(padcfg1); + value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); + + /* Set default strength value in case none is given */ + if (arg == 1) + arg = 5000; switch (param) { case PIN_CONFIG_BIAS_DISABLE: - value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); break; case PIN_CONFIG_BIAS_PULL_UP: - value &= ~PADCFG1_TERM_MASK; - - value |= PADCFG1_TERM_UP; - - /* Set default strength value in case none is given */ - if (arg == 1) - arg = 5000; - switch (arg) { case 20000: value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; @@ -721,17 +717,13 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, break; default: ret = -EINVAL; + break; } + value |= PADCFG1_TERM_UP; break; case PIN_CONFIG_BIAS_PULL_DOWN: - value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); - - /* Set default strength value in case none is given */ - if (arg == 1) - arg = 5000; - switch (arg) { case 20000: value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; @@ -755,6 +747,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, break; default: ret = -EINVAL; + break; } break; From a63dd601bcc2209658d71394a9160833ba559272 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:32:07 +0200 Subject: [PATCH 021/118] pinctrl: intel: Add definitions to all possible biases Add definitions to all possible biases, i.e. add ~800 Ohms, ~952 Ohms, ~4 kOhms. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 4a0f7412b6e7b..f72db3093981b 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -81,8 +81,11 @@ #define PADCFG1_TERM_MASK GENMASK(12, 10) #define PADCFG1_TERM_20K BIT(2) #define PADCFG1_TERM_5K BIT(1) +#define PADCFG1_TERM_4K (BIT(2) | BIT(1)) #define PADCFG1_TERM_1K BIT(0) +#define PADCFG1_TERM_952 (BIT(2) | BIT(0)) #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) +#define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) #define PADCFG2 0x008 #define PADCFG2_DEBEN BIT(0) From 346c8364613a9862323386d75f511785696fbe52 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:32:08 +0200 Subject: [PATCH 022/118] pinctrl: intel: Add ~4k bias support All versions that have 20k and 5k resistance, i.e. all that the driver supports, may support ~4k when the above mentioned are connected in parallel. Add such a support. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index f72db3093981b..ad32e3cfb4a7b 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -577,6 +577,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, case PADCFG1_TERM_1K: *arg = 1000; break; + case PADCFG1_TERM_4K: + *arg = 4000; + break; case PADCFG1_TERM_5K: *arg = 5000; break; @@ -602,6 +605,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, return -EINVAL; *arg = 1000; break; + case PADCFG1_TERM_4K: + *arg = 4000; + break; case PADCFG1_TERM_5K: *arg = 5000; break; @@ -712,6 +718,9 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, case 5000: value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; break; + case 4000: + value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT; + break; case 1000: value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; break; @@ -734,6 +743,9 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, case 5000: value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; break; + case 4000: + value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT; + break; case 1000: if (!(community->features & PINCTRL_FEATURE_1K_PD)) { ret = -EINVAL; From 203a1c3ecae70076e14a652ca44b7ad9302eecd3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:32:29 +0200 Subject: [PATCH 023/118] pinctrl: intel: Use same order of bit fields for PADCFG2 PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. No functional changes intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index ad32e3cfb4a7b..038a5721ae521 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -88,9 +88,9 @@ #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) #define PADCFG2 0x008 -#define PADCFG2_DEBEN BIT(0) #define PADCFG2_DEBOUNCE_SHIFT 1 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) +#define PADCFG2_DEBEN BIT(0) #define DEBOUNCE_PERIOD_NSEC 31250 From ed153b0793ba8a3b11d909a78ff48b16878bd2f3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:32:40 +0200 Subject: [PATCH 024/118] pinctrl: intel: Define maximum pad number in the group Instead of using hard coded magic number here and there, define maximum pad number in the group in newly added INTEL_PINCTRL_MAX_GPP_SIZE. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 6 +++--- drivers/pinctrl/intel/pinctrl-intel.h | 4 +++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 038a5721ae521..1e6d49b18d5c5 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1406,7 +1406,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, for (i = 0; i < ngpps; i++) { gpps[i] = community->gpps[i]; - if (gpps[i].size > 32) + if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE) return -EINVAL; /* Special treatment for GPIO base */ @@ -1424,7 +1424,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, } gpps[i].padown_num = padown_num; - padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); + padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE); } community->gpps = gpps; @@ -1440,7 +1440,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, unsigned int padown_num = 0; size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); - if (community->gpp_size > 32) + if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE) return -EINVAL; gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 981c1f520f13a..3b0e2d3f15d52 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -46,11 +46,13 @@ struct intel_function { size_t ngroups; }; +#define INTEL_PINCTRL_MAX_GPP_SIZE 32 + /** * struct intel_padgroup - Hardware pad group information * @reg_num: GPI_IS register number * @base: Starting pin of this group - * @size: Size of this group (maximum is 32). + * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE). * @gpio_base: Starting GPIO base of this group * @padown_num: PAD_OWN register number (assigned by the core driver) * From df72b4a692b60d3e5d99d9ef662b2d03c44bb9c0 Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Thu, 8 Dec 2022 15:07:04 +0530 Subject: [PATCH 025/118] pinctrl: amd: Add Z-state wake control bits GPIO registers include Bit 27 for WakeCntrlZ used to enable wake in Z state. Hence add Z-state wake control bits to debugfs output to debug and analyze Z-states problems. Signed-off-by: Basavaraj Natikar Suggested-by: Mario Limonciello Tested-by: Guruvendra Punugupati Link: https://lore.kernel.org/r/20221208093704.1151928-1-Basavaraj.Natikar@amd.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 7 +++++++ drivers/pinctrl/pinctrl-amd.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9bc6e3922e78e..ce3893dc85e63 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -218,6 +218,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) char *orientation; char debounce_value[40]; char *debounce_enable; + char *wake_cntrlz; for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { unsigned int time = 0; @@ -305,6 +306,12 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) wake_cntrl2 = " ∅"; seq_printf(s, "S4/S5 %s| ", wake_cntrl2); + if (pin_reg & BIT(WAKECNTRL_Z_OFF)) + wake_cntrlz = "⏰"; + else + wake_cntrlz = " ∅"; + seq_printf(s, "Z %s| ", wake_cntrlz); + if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { pull_up_enable = "+"; if (pin_reg & BIT(PULL_UP_SEL_OFF)) diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index c8635998465db..81ae8319a1f0a 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -42,6 +42,7 @@ #define OUTPUT_ENABLE_OFF 23 #define SW_CNTRL_IN_OFF 24 #define SW_CNTRL_EN_OFF 25 +#define WAKECNTRL_Z_OFF 27 #define INTERRUPT_STS_OFF 28 #define WAKE_STS_OFF 29 From b7f44e1249cc2831600802bd43474c75f75a9e0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 13 Dec 2022 19:21:25 +0100 Subject: [PATCH 026/118] pinctrl: da850-pupd: Drop empty platform remove function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A remove callback just returning 0 is equivalent to no remove callback at all. So drop the useless function. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20221213182125.929303-1-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-da850-pupd.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-da850-pupd.c b/drivers/pinctrl/pinctrl-da850-pupd.c index 5a0a1f20c843e..5eb248663e170 100644 --- a/drivers/pinctrl/pinctrl-da850-pupd.c +++ b/drivers/pinctrl/pinctrl-da850-pupd.c @@ -173,11 +173,6 @@ static int da850_pupd_probe(struct platform_device *pdev) return 0; } -static int da850_pupd_remove(struct platform_device *pdev) -{ - return 0; -} - static const struct of_device_id da850_pupd_of_match[] = { { .compatible = "ti,da850-pupd" }, { } @@ -190,7 +185,6 @@ static struct platform_driver da850_pupd_driver = { .of_match_table = da850_pupd_of_match, }, .probe = da850_pupd_probe, - .remove = da850_pupd_remove, }; module_platform_driver(da850_pupd_driver); From f3cd465bbd15960f30668c7b4a2ac18a0708bc39 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 13 Dec 2022 19:23:22 +0100 Subject: [PATCH 027/118] pinctrl: thunderbay: Drop empty platform remove function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A remove callback just returning 0 is equivalent to no remove callback at all. So drop the useless function. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20221213182322.962345-1-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-thunderbay.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-thunderbay.c b/drivers/pinctrl/pinctrl-thunderbay.c index 590bbbf619afc..7a5ff955877cb 100644 --- a/drivers/pinctrl/pinctrl-thunderbay.c +++ b/drivers/pinctrl/pinctrl-thunderbay.c @@ -1278,19 +1278,12 @@ static int thunderbay_pinctrl_probe(struct platform_device *pdev) return 0; } -static int thunderbay_pinctrl_remove(struct platform_device *pdev) -{ - /* thunderbay_pinctrl_remove function to clear the assigned memory */ - return 0; -} - static struct platform_driver thunderbay_pinctrl_driver = { .driver = { .name = "thunderbay-pinctrl", .of_match_table = thunderbay_pinctrl_match, }, .probe = thunderbay_pinctrl_probe, - .remove = thunderbay_pinctrl_remove, }; builtin_platform_driver(thunderbay_pinctrl_driver); From a3a7482a0dbce502331caaa9aa8346e72e84b38d Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 15 Dec 2022 10:21:28 +0100 Subject: [PATCH 028/118] pinctrl: mxs: avoid defines prefixed with CONFIG Defines prefixed with "CONFIG" should be limited to proper Kconfig options, that are introduced in a Kconfig file. Here, expressions to convert pin configurations to booleans for pull-up, voltage and mA are macro definitions that begin with "CONFIG". To avoid defines prefixed with "CONFIG", rename these defines to begin with "PIN_CONFIG" instead. No functional change. Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20221215092128.3954-1-lukas.bulwahn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-mxs.c | 6 +++--- drivers/pinctrl/freescale/pinctrl-mxs.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index 9f78c9b29ddd9..cf3f4d2e0c168 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -269,9 +269,9 @@ static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, for (n = 0; n < num_configs; n++) { config = configs[n]; - ma = CONFIG_TO_MA(config); - vol = CONFIG_TO_VOL(config); - pull = CONFIG_TO_PULL(config); + ma = PIN_CONFIG_TO_MA(config); + vol = PIN_CONFIG_TO_VOL(config); + pull = PIN_CONFIG_TO_PULL(config); for (i = 0; i < g->npins; i++) { bank = PINID_TO_BANK(g->pins[i]); diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.h b/drivers/pinctrl/freescale/pinctrl-mxs.h index ab9f834b03e6b..5b26511d56aac 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.h +++ b/drivers/pinctrl/freescale/pinctrl-mxs.h @@ -44,9 +44,9 @@ #define VOL_SHIFT 3 #define MA_PRESENT (1 << 2) #define MA_SHIFT 0 -#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) -#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) -#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) +#define PIN_CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) +#define PIN_CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) +#define PIN_CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) struct mxs_function { const char *name; From 5d8ae2928f71f0f9c2c3f8f13d00ecec35649ad3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 15 Dec 2022 17:42:54 +0100 Subject: [PATCH 029/118] pinctrl: at91: convert to NOIRQ_SYSTEM_SLEEP_PM_OPS With the old SET_NOIRQ_SYSTEM_SLEEP_PM_OPS, some configs result in a build warning: drivers/pinctrl/pinctrl-at91.c:1668:12: error: 'at91_gpio_resume' defined but not used [-Werror=unused-function] 1668 | static int at91_gpio_resume(struct device *dev) | ^~~~~~~~~~~~~~~~ drivers/pinctrl/pinctrl-at91.c:1650:12: error: 'at91_gpio_suspend' defined but not used [-Werror=unused-function] 1650 | static int at91_gpio_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~ Signed-off-by: Arnd Bergmann Reviewed-by: Ryan Wanner Link: https://lore.kernel.org/r/20221215164301.934805-1-arnd@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 1e1813d7c5508..cf2423855a80a 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1923,7 +1923,7 @@ static int at91_gpio_probe(struct platform_device *pdev) } static const struct dev_pm_ops at91_gpio_pm_ops = { - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume) + NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume) }; static struct platform_driver at91_gpio_driver = { From 84f0b1ea2a7e27f4e0885a9ebf71ae98069513ad Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Dec 2022 21:31:58 +0000 Subject: [PATCH 030/118] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG). Signed-off-by: Biju Das Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221215213206.56666-2-biju.das.jz@bp.renesas.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml new file mode 100644 index 0000000000000..ab2d456c93e4e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Port Output Enable for GPT (POEG) + +maintainers: + - Biju Das + +description: | + The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be + disabled by using the port output enabling function for the GPT (POEG). + Specifically, either of the following ways can be used. + * Input level detection of the GTETRGA to GTETRGD pins. + * Output-disable request from the GPT. + * SSF bit setting(ie, by setting POEGGn.SSF to 1) + + The state of the GTIOCxA and the GTIOCxB pins when the output is disabled, + are controlled by the GPT module. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-poeg # RZ/G2{L,LC} + - renesas,r9a07g054-poeg # RZ/V2L + - const: renesas,rzg2l-poeg + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,gpt: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to gpt instance that serves the pwm operation. + + renesas,poeg-id: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + POEG group index. Valid values are: + <0> : POEG group A + <1> : POEG group B + <2> : POEG group C + <3> : POEG group D + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + - renesas,poeg-id + - renesas,gpt + +additionalProperties: false + +examples: + - | + #include + #include + + poeggd: poeg@10049400 { + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg"; + reg = <0x10049400 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_POEG_D_RST>; + renesas,poeg-id = <3>; + renesas,gpt = <&gpt>; + }; From 2daa14811e36fccdc4d130db9be4f959275c6165 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 16 Dec 2022 15:08:51 -0800 Subject: [PATCH 031/118] dt-bindings: pinctrl: qcom: Add QDU1000 and QRU1000 pinctrl Add device tree bindings for QDU1000 and QRU1000 TLMM devices. Signed-off-by: Melody Olvera Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221216230852.21691-2-quic_molvera@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,qdu1000-tlmm.yaml | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml new file mode 100644 index 0000000000000..7e5fb9a6e7d35 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block + +maintainers: + - Melody Olvera + +description: | + Top Level Mode Multiplexer pin controller found in the QDU1000 and + QRU1000 SoCs. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qdu1000-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 76 + + gpio-line-names: + maxItems: 151 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qdu1000-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qdu1000-tlmm-state" + additionalProperties: false + +$defs: + qcom-qdu1000-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng, + dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, + ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in, + intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist, + pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, + qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable, + qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request, + qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss, + qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs, + qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04, + qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert, + smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2, + usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1, + vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + }; From 51a8f99718573b543197871a652b338c454806cd Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Fri, 16 Dec 2022 15:08:52 -0800 Subject: [PATCH 032/118] pinctrl: qcom: Add QDU1000/QRU1000 pinctrl driver Add pin control driver for the TLMM block found in the QDU1000 and QRU1000 SoC. Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20221216230852.21691-3-quic_molvera@quicinc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-qdu1000.c | 1274 ++++++++++++++++++++++++ 3 files changed, 1285 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-qdu1000.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 1378ddca084f8..9ff4145646a39 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -248,6 +248,16 @@ config PINCTRL_QCOM_SSBI_PMIC which are using SSBI for communication with SoC. Example PMIC's devices are pm8058 and pm8921. +config PINCTRL_QDU1000 + tristate "Qualcomm Tehcnologies Inc QDU1000/QRU1000 pin controller driver" + depends on GPIOLIB && OF + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf, and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc QDU1000 and QRU1000 platforms. + config PINCTRL_SC7180 tristate "Qualcomm Technologies Inc SC7180 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a5c40f552e5c2..aca888bc78652 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o +obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c new file mode 100644 index 0000000000000..b1d7674a2bec6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -0,0 +1,1274 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = REG_BASE + ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define QUP_I3C(qup_mode, qup_offset) \ + { \ + .mode = qup_mode, \ + .offset = qup_offset, \ + } + +static const struct pinctrl_pin_desc qdu1000_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "SDC1_RCLK"), + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); + +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; + +enum qdu1000_functions { + msm_mux_gpio, + msm_mux_cmo_pri, + msm_mux_si5518_int, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_char_exec, + msm_mux_cmu_rng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_ddr_pxi6, + msm_mux_ddr_pxi7, + msm_mux_eth012_int_n, + msm_mux_eth345_int_n, + msm_mux_eth6_int_n, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gps_pps_in, + msm_mux_hardsync_pps_in, + msm_mux_intr_c, + msm_mux_jitter_bist_ref, + msm_mux_pcie_clkreqn, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qlink3_enable, + msm_mux_qlink3_request, + msm_mux_qlink3_wmss, + msm_mux_qlink4_enable, + msm_mux_qlink4_request, + msm_mux_qlink4_wmss, + msm_mux_qlink5_enable, + msm_mux_qlink5_request, + msm_mux_qlink5_wmss, + msm_mux_qlink6_enable, + msm_mux_qlink6_request, + msm_mux_qlink6_wmss, + msm_mux_qlink7_enable, + msm_mux_qlink7_request, + msm_mux_qlink7_wmss, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup03, + msm_mux_qup04, + msm_mux_qup05, + msm_mux_qup06, + msm_mux_qup07, + msm_mux_qup08, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup22, + msm_mux_smb_alert, + msm_mux_smb_clk, + msm_mux_smb_dat, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tgu_ch4, + msm_mux_tgu_ch5, + msm_mux_tgu_ch6, + msm_mux_tgu_ch7, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tod_pps_in, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_usb2phy_ac, + msm_mux_usb_con_det, + msm_mux_usb_dfp_en, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", +}; +static const char * const cmo_pri_groups[] = { + "gpio103", +}; +static const char * const si5518_int_groups[] = { + "gpio44", +}; +static const char * const atest_char_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio95", +}; +static const char * const atest_usb_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const char_exec_groups[] = { + "gpio99", "gpio100", +}; +static const char * const cmu_rng_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const dbg_out_clk_groups[] = { + "gpio136", +}; +static const char * const ddr_bist_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio114", "gpio115", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio116", "gpio117", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio118", "gpio119", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio120", "gpio121", +}; +static const char * const ddr_pxi4_groups[] = { + "gpio122", "gpio123", +}; +static const char * const ddr_pxi5_groups[] = { + "gpio124", "gpio125", +}; +static const char * const ddr_pxi6_groups[] = { + "gpio126", "gpio127", +}; +static const char * const ddr_pxi7_groups[] = { + "gpio128", "gpio129", +}; +static const char * const eth012_int_n_groups[] = { + "gpio86", +}; +static const char * const eth345_int_n_groups[] = { + "gpio87", +}; +static const char * const eth6_int_n_groups[] = { + "gpio88", +}; +static const char * const gcc_gp1_groups[] = { + "gpio86", "gpio134", +}; +static const char * const gcc_gp2_groups[] = { + "gpio87", "gpio135", +}; +static const char * const gcc_gp3_groups[] = { + "gpio88", "gpio136", +}; +static const char * const gps_pps_in_groups[] = { + "gpio49", +}; +static const char * const hardsync_pps_in_groups[] = { + "gpio47", +}; +static const char * const intr_c_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio141", "gpio142", "gpio143", +}; +static const char * const jitter_bist_ref_groups[] = { + "gpio130", +}; +static const char * const pcie_clkreqn_groups[] = { + "gpio98", "gpio99", "gpio100", +}; +static const char * const phase_flag_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio20", "gpio22", "gpio21", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio42", "gpio43", "gpio89", "gpio90", "gpio91", "gpio92", + "gpio95", "gpio96", "gpio97", "gpio102", +}; +static const char * const pll_bist_groups[] = { + "gpio20", +}; +static const char * const pll_clk_groups[] = { + "gpio98", +}; +static const char * const prng_rosc_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const qdss_cti_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio48", + "gpio49", "gpio86", "gpio87", "gpio93", "gpio94", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio144", "gpio145", +}; +static const char * const qdss_gpio_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio24", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio42", "gpio43", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio95", "gpio96", "gpio97", "gpio102", + "gpio103", +}; +static const char * const qlink0_enable_groups[] = { + "gpio67", +}; +static const char * const qlink0_request_groups[] = { + "gpio66", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio82", +}; +static const char * const qlink1_enable_groups[] = { + "gpio69", +}; +static const char * const qlink1_request_groups[] = { + "gpio68", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio83", +}; +static const char * const qlink2_enable_groups[] = { + "gpio71", +}; +static const char * const qlink2_request_groups[] = { + "gpio70", +}; +static const char * const qlink2_wmss_groups[] = { + "gpio138", +}; +static const char * const qlink3_enable_groups[] = { + "gpio73", +}; +static const char * const qlink3_request_groups[] = { + "gpio72", +}; +static const char * const qlink3_wmss_groups[] = { + "gpio139", +}; +static const char * const qlink4_enable_groups[] = { + "gpio75", +}; +static const char * const qlink4_request_groups[] = { + "gpio74", +}; +static const char * const qlink4_wmss_groups[] = { + "gpio84", +}; +static const char * const qlink5_enable_groups[] = { + "gpio77", +}; +static const char * const qlink5_request_groups[] = { + "gpio76", +}; +static const char * const qlink5_wmss_groups[] = { + "gpio85", +}; +static const char * const qlink6_enable_groups[] = { + "gpio79", +}; +static const char * const qlink6_request_groups[] = { + "gpio78", +}; +static const char * const qlink6_wmss_groups[] = { + "gpio56", +}; +static const char * const qlink7_enable_groups[] = { + "gpio81", +}; +static const char * const qlink7_request_groups[] = { + "gpio80", +}; +static const char * const qlink7_wmss_groups[] = { + "gpio57", +}; +static const char * const qspi0_groups[] = { + "gpio114", +}; +static const char * const qspi1_groups[] = { + "gpio115", +}; +static const char * const qspi2_groups[] = { + "gpio116", +}; +static const char * const qspi3_groups[] = { + "gpio117", +}; +static const char * const qspi_clk_groups[] = { + "gpio126", +}; +static const char * const qspi_cs_groups[] = { + "gpio125", +}; +static const char * const qup00_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; +static const char * const qup01_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; +static const char * const qup02_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; +static const char * const qup03_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const qup04_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; +static const char * const qup05_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133", +}; +static const char * const qup06_groups[] = { + "gpio130", "gpio131", "gpio132", "gpio133", +}; +static const char * const qup07_groups[] = { + "gpio134", "gpio135", +}; +static const char * const qup08_groups[] = { + "gpio134", "gpio135", +}; +static const char * const qup10_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const qup11_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; +static const char * const qup12_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; +static const char * const qup13_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; +static const char * const qup14_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; +static const char * const qup15_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const qup16_groups[] = { + "gpio29", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup17_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio30", "gpio31", "gpio40", "gpio41", +}; +static const char * const qup20_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup21_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup22_groups[] = { + "gpio4", "gpio5", "gpio128", "gpio129", +}; +static const char * const smb_alert_groups[] = { + "gpio88", "gpio101", +}; +static const char * const smb_clk_groups[] = { + "gpio133", +}; +static const char * const smb_dat_groups[] = { + "gpio132", +}; +static const char * const tb_trig_groups[] = { + "gpio114", +}; +static const char * const tgu_ch0_groups[] = { + "gpio6", +}; +static const char * const tgu_ch1_groups[] = { + "gpio7", +}; +static const char * const tgu_ch2_groups[] = { + "gpio8", +}; +static const char * const tgu_ch3_groups[] = { + "gpio9", +}; +static const char * const tgu_ch4_groups[] = { + "gpio44", +}; +static const char * const tgu_ch5_groups[] = { + "gpio45", +}; +static const char * const tgu_ch6_groups[] = { + "gpio46", +}; +static const char * const tgu_ch7_groups[] = { + "gpio47", +}; +static const char * const tmess_prng0_groups[] = { + "gpio33", +}; +static const char * const tmess_prng1_groups[] = { + "gpio32", +}; +static const char * const tmess_prng2_groups[] = { + "gpio31", +}; +static const char * const tmess_prng3_groups[] = { + "gpio30", +}; +static const char * const tod_pps_in_groups[] = { + "gpio48", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio2", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio3", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio90", +}; +static const char * const usb_con_det_groups[] = { + "gpio42", +}; +static const char * const usb_dfp_en_groups[] = { + "gpio43", +}; +static const char * const usb_phy_groups[] = { + "gpio91", +}; +static const char * const vfr_0_groups[] = { + "gpio93", +}; +static const char * const vfr_1_groups[] = { + "gpio94", +}; +static const char * const vsense_trigger_groups[] = { + "gpio135", +}; + +static const struct msm_function qdu1000_functions[] = { + FUNCTION(gpio), + FUNCTION(cmo_pri), + FUNCTION(si5518_int), + FUNCTION(atest_char), + FUNCTION(atest_usb), + FUNCTION(char_exec), + FUNCTION(cmu_rng), + FUNCTION(dbg_out_clk), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(ddr_pxi4), + FUNCTION(ddr_pxi5), + FUNCTION(ddr_pxi6), + FUNCTION(ddr_pxi7), + FUNCTION(eth012_int_n), + FUNCTION(eth345_int_n), + FUNCTION(eth6_int_n), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gps_pps_in), + FUNCTION(hardsync_pps_in), + FUNCTION(intr_c), + FUNCTION(jitter_bist_ref), + FUNCTION(pcie_clkreqn), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_clk), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qlink0_enable), + FUNCTION(qlink0_request), + FUNCTION(qlink0_wmss), + FUNCTION(qlink1_enable), + FUNCTION(qlink1_request), + FUNCTION(qlink1_wmss), + FUNCTION(qlink2_enable), + FUNCTION(qlink2_request), + FUNCTION(qlink2_wmss), + FUNCTION(qlink3_enable), + FUNCTION(qlink3_request), + FUNCTION(qlink3_wmss), + FUNCTION(qlink4_enable), + FUNCTION(qlink4_request), + FUNCTION(qlink4_wmss), + FUNCTION(qlink5_enable), + FUNCTION(qlink5_request), + FUNCTION(qlink5_wmss), + FUNCTION(qlink6_enable), + FUNCTION(qlink6_request), + FUNCTION(qlink6_wmss), + FUNCTION(qlink7_enable), + FUNCTION(qlink7_request), + FUNCTION(qlink7_wmss), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup00), + FUNCTION(qup01), + FUNCTION(qup02), + FUNCTION(qup03), + FUNCTION(qup04), + FUNCTION(qup05), + FUNCTION(qup06), + FUNCTION(qup07), + FUNCTION(qup08), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup20), + FUNCTION(qup21), + FUNCTION(qup22), + FUNCTION(smb_alert), + FUNCTION(smb_clk), + FUNCTION(smb_dat), + FUNCTION(tb_trig), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tgu_ch4), + FUNCTION(tgu_ch5), + FUNCTION(tgu_ch6), + FUNCTION(tgu_ch7), + FUNCTION(tmess_prng0), + FUNCTION(tmess_prng1), + FUNCTION(tmess_prng2), + FUNCTION(tmess_prng3), + FUNCTION(tod_pps_in), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(usb2phy_ac), + FUNCTION(usb_con_det), + FUNCTION(usb_dfp_en), + FUNCTION(usb_phy), + FUNCTION(vfr_0), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup qdu1000_groups[] = { + [0] = PINGROUP(0, qup20, qup21, ddr_bist, _, _, _, _, _, _), + [1] = PINGROUP(1, qup20, qup21, ddr_bist, _, _, _, _, _, _), + [2] = PINGROUP(2, qup21, qup20, ddr_bist, _, + tsense_pwm1, _, _, _, _), + [3] = PINGROUP(3, qup21, qup20, ddr_bist, _, + tsense_pwm2, _, _, _, _), + [4] = PINGROUP(4, qup22, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup22, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup00, tgu_ch0, phase_flag, _, + qdss_gpio, _, _, _, _), + [7] = PINGROUP(7, qup00, tgu_ch1, phase_flag, _, + qdss_gpio, _, _, _, _), + [8] = PINGROUP(8, qup00, tgu_ch2, phase_flag, _, + qdss_gpio, _, _, _, _), + [9] = PINGROUP(9, qup00, tgu_ch3, phase_flag, _, + qdss_gpio, _, _, _, _), + [10] = PINGROUP(10, qup01, qup02, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup01, qup02, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup02, qup01, qup17, _, _, _, _, _, _), + [13] = PINGROUP(13, qup02, qup01, qup17, _, _, _, _, _, _), + [14] = PINGROUP(14, qup03, qup04, qup17, _, _, _, _, _, _), + [15] = PINGROUP(15, qup03, qup04, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup04, qup03, phase_flag, _, + qdss_gpio, _, _, _, _), + [17] = PINGROUP(17, qup04, qup03, phase_flag, _, + qdss_gpio, _, _, _, _), + [18] = PINGROUP(18, qup10, prng_rosc, phase_flag, + _, qdss_gpio, _, _, _, _), + [19] = PINGROUP(19, qup10, prng_rosc, phase_flag, + _, qdss_gpio, _, _, _, _), + [20] = PINGROUP(20, qup10, prng_rosc, pll_bist, + phase_flag, _, qdss_gpio, _, _, _), + [21] = PINGROUP(21, qup10, prng_rosc, phase_flag, + _, qdss_gpio, _, _, _, _), + [22] = PINGROUP(22, qup11, qup12, phase_flag, _, + qdss_gpio, _, _, _, _), + [23] = PINGROUP(23, qup11, qup12, phase_flag, _, + qdss_gpio, _, _, _, _), + [24] = PINGROUP(24, qup12, qup11, phase_flag, _, + qdss_gpio, _, _, _, _), + [25] = PINGROUP(25, qup12, qup11, phase_flag, _, + qdss_gpio, _, _, _, _), + [26] = PINGROUP(26, qup13, qup14, intr_c, + phase_flag, _, qdss_gpio, _, _, _), + [27] = PINGROUP(27, qup13, qup14, intr_c, + phase_flag, _, qdss_gpio, _, _, _), + [28] = PINGROUP(28, qup14, qup13, intr_c, + phase_flag, _, qdss_gpio, _, _, _), + [29] = PINGROUP(29, qup14, qup13, qup16, + phase_flag, _, qdss_gpio, _, _, _), + [30] = PINGROUP(30, qup17, qup15, tmess_prng3, + phase_flag, _, qdss_gpio, _, _, _), + [31] = PINGROUP(31, qup17, qup15, tmess_prng2, + phase_flag, _, qdss_gpio, _, _, _), + [32] = PINGROUP(32, qup15, tmess_prng1, phase_flag, + _, qdss_gpio, _, _, _, _), + [33] = PINGROUP(33, qup15, tmess_prng0, phase_flag, + _, qdss_gpio, _, _, _, _), + [34] = PINGROUP(34, qup16, qdss_gpio, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup16, qdss_gpio, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup16, qdss_cti, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup16, qdss_cti, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup16, qdss_cti, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup16, qdss_cti, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup17, qdss_cti, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup17, qdss_cti, _, _, _, _, _, _, _), + [42] = PINGROUP(42, usb_con_det, phase_flag, _, + qdss_gpio, _, _, _, _, _), + [43] = PINGROUP(43, usb_dfp_en, phase_flag, _, + qdss_gpio, _, _, _, _, _), + [44] = PINGROUP(44, si5518_int, tgu_ch4, _, _, _, _, _, _, _), + [45] = PINGROUP(45, tgu_ch5, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, tgu_ch6, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, hardsync_pps_in, tgu_ch7, _, _, _, _, _, _, _), + [48] = PINGROUP(48, tod_pps_in, qdss_cti, _, _, _, _, _, _, _), + [49] = PINGROUP(49, gps_pps_in, qdss_cti, _, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, _, qlink6_wmss, _, _, _, _, _, _, _), + [57] = PINGROUP(57, _, qlink7_wmss, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, qlink0_request, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, qlink0_enable, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, qlink1_request, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qlink1_enable, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qlink2_request, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qlink2_enable, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qlink3_request, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink3_enable, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink4_request, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qlink4_enable, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qlink5_request, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qlink5_enable, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qlink6_request, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qlink6_enable, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qlink7_request, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qlink7_enable, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qlink0_wmss, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qlink1_wmss, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qlink4_wmss, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qlink5_wmss, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, eth012_int_n, gcc_gp1, _, qdss_cti, _, _, _, _, _), + [87] = PINGROUP(87, eth345_int_n, gcc_gp2, _, qdss_cti, _, _, _, _, _), + [88] = PINGROUP(88, eth6_int_n, smb_alert, gcc_gp3, _, + qdss_gpio, _, _, _, _), + [89] = PINGROUP(89, phase_flag, cmu_rng, _, + qdss_gpio, atest_char, _, _, _, _), + [90] = PINGROUP(90, usb2phy_ac, phase_flag, + cmu_rng, _, qdss_gpio, + atest_char, _, _, _), + [91] = PINGROUP(91, usb_phy, phase_flag, cmu_rng, + _, qdss_gpio, atest_char, _, _, _), + [92] = PINGROUP(92, phase_flag, cmu_rng, _, + qdss_gpio, atest_char, _, _, _, _), + [93] = PINGROUP(93, vfr_0, qdss_cti, _, _, _, _, _, _, _), + [94] = PINGROUP(94, vfr_1, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, phase_flag, _, qdss_gpio, + atest_char, _, _, _, _, _), + [96] = PINGROUP(96, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [97] = PINGROUP(97, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [98] = PINGROUP(98, pll_clk, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, pcie_clkreqn, char_exec, _, _, _, _, _, _, _), + [100] = PINGROUP(100, char_exec, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, smb_alert, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, phase_flag, _, qdss_gpio, _, _, _, _, _, _), + [103] = PINGROUP(103, cmo_pri, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, qspi0, tb_trig, _, + atest_usb, ddr_pxi0, _, _, _, _), + [115] = PINGROUP(115, qspi1, _, atest_usb, + ddr_pxi0, _, _, _, _, _), + [116] = PINGROUP(116, qspi2, _, atest_usb, + ddr_pxi1, _, _, _, _, _), + [117] = PINGROUP(117, qspi3, _, atest_usb, + ddr_pxi1, _, _, _, _, _), + [118] = PINGROUP(118, _, atest_usb, ddr_pxi2, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, ddr_pxi2, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, ddr_pxi3, _, _, _, _, _, _), + [121] = PINGROUP(121, _, ddr_pxi3, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, ddr_pxi4, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, ddr_pxi4, _, _, _, _, _, _, _), + [124] = PINGROUP(124, _, ddr_pxi5, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qspi_cs, _, ddr_pxi5, _, _, _, _, _, _), + [126] = PINGROUP(126, qspi_clk, _, ddr_pxi6, _, _, _, _, _, _), + [127] = PINGROUP(127, _, ddr_pxi6, _, _, _, _, _, _, _), + [128] = PINGROUP(128, qup22, _, ddr_pxi7, _, _, _, _, _, _), + [129] = PINGROUP(129, qup22, ddr_pxi7, _, _, _, _, _, _, _), + [130] = PINGROUP(130, qup05, qup06, jitter_bist_ref, + qdss_cti, _, _, _, _, _), + [131] = PINGROUP(131, qup05, qup06, qdss_cti, _, _, _, _, _, _), + [132] = PINGROUP(132, qup06, qup05, smb_dat, + qdss_cti, _, _, _, _, _), + [133] = PINGROUP(133, qup06, qup05, smb_clk, + qdss_cti, _, _, _, _, _), + [134] = PINGROUP(134, qup08, qup07, gcc_gp1, _, + qdss_cti, _, _, _, _), + [135] = PINGROUP(135, qup08, qup07, gcc_gp2, _, + qdss_cti, vsense_trigger, _, _, _), + [136] = PINGROUP(136, gcc_gp3, dbg_out_clk, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, qlink2_wmss, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, qlink3_wmss, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, intr_c, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, intr_c, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, intr_c, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, qdss_cti, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, qdss_cti, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _), + [151] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9e000, 0, 0), + [152] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9d000, 13, 6), + [153] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9d000, 11, 3), + [154] = SDC_QDSD_PINGROUP(sdc1_data, 0x9d000, 9, 0), +}; +static const struct msm_pinctrl_soc_data qdu1000_tlmm = { + .pins = qdu1000_pins, + .npins = ARRAY_SIZE(qdu1000_pins), + .functions = qdu1000_functions, + .nfunctions = ARRAY_SIZE(qdu1000_functions), + .groups = qdu1000_groups, + .ngroups = ARRAY_SIZE(qdu1000_groups), + .ngpios = 151, +}; + +static int qdu1000_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &qdu1000_tlmm); +} + +static const struct of_device_id qdu1000_tlmm_of_match[] = { + { .compatible = "qcom,qdu1000-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qdu1000_tlmm_of_match); + +static struct platform_driver qdu1000_tlmm_driver = { + .driver = { + .name = "qdu1000-tlmm", + .of_match_table = qdu1000_tlmm_of_match, + }, + .probe = qdu1000_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init qdu1000_tlmm_init(void) +{ + return platform_driver_register(&qdu1000_tlmm_driver); +} +arch_initcall(qdu1000_tlmm_init); + +static void __exit qdu1000_tlmm_exit(void) +{ + platform_driver_unregister(&qdu1000_tlmm_driver); +} +module_exit(qdu1000_tlmm_exit); + +MODULE_DESCRIPTION("QTI QDU1000 TLMM driver"); +MODULE_LICENSE("GPL"); From 443a0a0f0cf4f432c7af6654b7f2f920d411d379 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:33 +0200 Subject: [PATCH 033/118] pinctrl: Introduce struct pinfunction and PINCTRL_PINFUNCTION() macro There are many pin control drivers define their own data type for pin function representation which is the same or embed the same data as newly introduced one. Provide the data type and convenient macro for all pin control drivers. Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij Acked-by: Mika Westerberg --- include/linux/pinctrl/pinctrl.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index a0d39b3034311..4d252ea00ed1a 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -206,6 +206,26 @@ extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group, const unsigned **pins, unsigned *num_pins); +/** + * struct pinfunction - Description about a function + * @name: Name of the function + * @groups: An array of groups for this function + * @ngroups: Number of groups in @groups + */ +struct pinfunction { + const char *name; + const char * const *groups; + size_t ngroups; +}; + +/* Convenience macro to define a single named pinfunction */ +#define PINCTRL_PINFUNCTION(_name, _groups, _ngroups) \ +(struct pinfunction) { \ + .name = (_name), \ + .groups = (_groups), \ + .ngroups = (_ngroups), \ + } + #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PINCTRL) extern struct pinctrl_dev *of_pinctrl_get(struct device_node *np); #else From 999b85bfd765f273208cd7348b2977d3c5ae0753 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:34 +0200 Subject: [PATCH 034/118] pinctrl: intel: Make use of struct pinfunction and PINCTRL_PINFUNCTION() Since pin control provides a generic data type and a macro for the pin function definition, use them in the Intel driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 6 +++--- drivers/pinctrl/intel/pinctrl-intel.h | 13 ++++++++----- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 1e6d49b18d5c5..1bb2a0bb65dbb 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -372,7 +372,7 @@ static const char *intel_get_function_name(struct pinctrl_dev *pctldev, { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - return pctrl->soc->functions[function].name; + return pctrl->soc->functions[function].func.name; } static int intel_get_function_groups(struct pinctrl_dev *pctldev, @@ -382,8 +382,8 @@ static int intel_get_function_groups(struct pinctrl_dev *pctldev, { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - *groups = pctrl->soc->functions[function].groups; - *ngroups = pctrl->soc->functions[function].ngroups; + *groups = pctrl->soc->functions[function].func.groups; + *ngroups = pctrl->soc->functions[function].func.ngroups; return 0; } diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 3b0e2d3f15d52..91e5bedba00bb 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -36,11 +36,13 @@ struct intel_pingroup { /** * struct intel_function - Description about a function + * @func: Generic data of the pin function (name and groups of pins) * @name: Name of the function * @groups: An array of groups for this function * @ngroups: Number of groups in @groups */ struct intel_function { + struct pinfunction func; const char *name; const char * const *groups; size_t ngroups; @@ -183,11 +185,12 @@ struct intel_community { .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \ } -#define FUNCTION(n, g) \ - { \ - .name = (n), \ - .groups = (g), \ - .ngroups = ARRAY_SIZE((g)), \ +#define FUNCTION(n, g) \ + { \ + .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \ + .name = (n), \ + .groups = (g), \ + .ngroups = ARRAY_SIZE((g)), \ } /** From 988ac1a4689a3fcd8f72595773550d7f862a68b5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:35 +0200 Subject: [PATCH 035/118] pinctrl: baytrail: Convert to use new memeber in struct intel_function Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-baytrail.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 67db79f380510..770a2723ef817 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -637,18 +637,18 @@ static const char *byt_get_function_name(struct pinctrl_dev *pctldev, { struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - return vg->soc->functions[selector].name; + return vg->soc->functions[selector].func.name; } static int byt_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, const char * const **groups, - unsigned int *num_groups) + unsigned int *ngroups) { struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); - *groups = vg->soc->functions[selector].groups; - *num_groups = vg->soc->functions[selector].ngroups; + *groups = vg->soc->functions[selector].func.groups; + *ngroups = vg->soc->functions[selector].func.ngroups; return 0; } @@ -722,7 +722,7 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, if (group.modes) byt_set_group_mixed_mux(vg, group, group.modes); - else if (!strcmp(func.name, "gpio")) + else if (!strcmp(func.func.name, "gpio")) byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); else byt_set_group_simple_mux(vg, group, group.mode); From 3899707add6ac3e5cb0d91973ac81aa451915d95 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:36 +0200 Subject: [PATCH 036/118] pinctrl: cherryview: Convert to use new memeber in struct intel_function Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 11b81213922d8..722990e278361 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -694,7 +694,7 @@ static const char *chv_get_function_name(struct pinctrl_dev *pctldev, { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - return pctrl->soc->functions[function].name; + return pctrl->soc->functions[function].func.name; } static int chv_get_function_groups(struct pinctrl_dev *pctldev, @@ -704,8 +704,8 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev, { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - *groups = pctrl->soc->functions[function].groups; - *ngroups = pctrl->soc->functions[function].ngroups; + *groups = pctrl->soc->functions[function].func.groups; + *ngroups = pctrl->soc->functions[function].func.ngroups; return 0; } From b19d82e1f7f446507cbe575039029809a63b0adb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:37 +0200 Subject: [PATCH 037/118] pinctrl: lynxpoint: Convert to use new memeber in struct intel_function Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 8d05dad38556c..cdace55aaeac8 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -341,18 +341,18 @@ static const char *lp_get_function_name(struct pinctrl_dev *pctldev, { struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - return lg->soc->functions[selector].name; + return lg->soc->functions[selector].func.name; } static int lp_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, const char * const **groups, - unsigned int *num_groups) + unsigned int *ngroups) { struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); - *groups = lg->soc->functions[selector].groups; - *num_groups = lg->soc->functions[selector].ngroups; + *groups = lg->soc->functions[selector].func.groups; + *ngroups = lg->soc->functions[selector].func.ngroups; return 0; } From de82e6f018664eff594aef11e7377af3898c0d95 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:38 +0200 Subject: [PATCH 038/118] pinctrl: merrifield: Convert to use new memeber in struct intel_function Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-merrifield.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index c0845bb1e9e36..365c391c97a3f 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -576,7 +576,7 @@ static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev, { struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - return mp->functions[function].name; + return mp->functions[function].func.name; } static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, @@ -586,8 +586,8 @@ static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, { struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - *groups = mp->functions[function].groups; - *ngroups = mp->functions[function].ngroups; + *groups = mp->functions[function].func.groups; + *ngroups = mp->functions[function].func.ngroups; return 0; } From 3b954b31e027ae2a46cae8482de87679bedd22b8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:39 +0200 Subject: [PATCH 039/118] pinctrl: moorefield: Convert to use new memeber in struct intel_function Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-moorefield.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c index e3eec671e15da..3c9a8484b4427 100644 --- a/drivers/pinctrl/intel/pinctrl-moorefield.c +++ b/drivers/pinctrl/intel/pinctrl-moorefield.c @@ -530,7 +530,7 @@ static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned { struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - return mp->functions[function].name; + return mp->functions[function].func.name; } static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, @@ -538,8 +538,8 @@ static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int f { struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); - *groups = mp->functions[function].groups; - *ngroups = mp->functions[function].ngroups; + *groups = mp->functions[function].func.groups; + *ngroups = mp->functions[function].func.ngroups; return 0; } From afa349bbb5d75e072e641234f1cb5d2264bd6ed0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 19 Dec 2022 14:42:40 +0200 Subject: [PATCH 040/118] pinctrl: intel: Get rid of unused members in struct intel_function The driver has been converted to a generic data type and macro for the pin function definition, hence get rid of not used members in the struct intel_function. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 91e5bedba00bb..1faf2ada480a8 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -37,15 +37,9 @@ struct intel_pingroup { /** * struct intel_function - Description about a function * @func: Generic data of the pin function (name and groups of pins) - * @name: Name of the function - * @groups: An array of groups for this function - * @ngroups: Number of groups in @groups */ struct intel_function { struct pinfunction func; - const char *name; - const char * const *groups; - size_t ngroups; }; #define INTEL_PINCTRL_MAX_GPP_SIZE 32 @@ -188,9 +182,6 @@ struct intel_community { #define FUNCTION(n, g) \ { \ .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \ - .name = (n), \ - .groups = (g), \ - .ngroups = ARRAY_SIZE((g)), \ } /** From 15dfa161cc2c11ecc5a461a4896983cbe21a0b45 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 30 Dec 2022 22:36:36 +0200 Subject: [PATCH 041/118] dt-bindings: pinctrl: qcom: Add SM8550 pinctrl Add device tree binding Documentation details for Qualcomm SM8550 TLMM device Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221230203637.2539900-2-abel.vesa@linaro.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8550-tlmm.yaml | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml new file mode 100644 index 0000000000000..a457425ba112d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8550 TLMM block + +maintainers: + - Abel Vesa + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8550-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 105 + + gpio-line-names: + maxItems: 210 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8550-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8550-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8550-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aon_cci, aoss_cti, atest_char, atest_usb, + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, + cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx, + coex_uart1_tx, coex_uart2_rx, coex_uart2_tx, + cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, + i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, + i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, + ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, + qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, + qlink2_enable, qlink2_request, qlink2_wmss, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup1_se7, qup2_se0, + qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira, + qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb, + qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qup2_se7, sd_write_protect, sdc40, sdc41, sdc42, + sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, + tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, + uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, + usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8550-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup2_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup2_se7"; + bias-disable; + }; + }; + }; +... From fcd26bf51c0e74af764f2a52bd1baddd4bf3b6cb Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 30 Dec 2022 22:36:37 +0200 Subject: [PATCH 042/118] pinctrl: qcom: Add SM8550 pinctrl driver Add pinctrl driver for TLMM block found in SM8550 SoC. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20221230203637.2539900-3-abel.vesa@linaro.org Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 1789 +++++++++++++++++++++++++ 3 files changed, 1800 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8550.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 9ff4145646a39..2a517775a61ec 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -467,6 +467,16 @@ config PINCTRL_SC8280XP_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform. +config PINCTRL_SM8550 + tristate "Qualcomm Technologies Inc SM8550 pin controller driver" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8550 platform. + config PINCTRL_LPASS_LPI tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" select PINMUX diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index aca888bc78652..952f784d08881 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -48,5 +48,6 @@ obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c new file mode 100644 index 0000000000000..0b7db7d4054ab --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -0,0 +1,1789 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8550_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "UFS_RESET"), + PINCTRL_PIN(211, "SDC2_CLK"), + PINCTRL_PIN(212, "SDC2_CMD"), + PINCTRL_PIN(213, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); + +static const unsigned int ufs_reset_pins[] = { 210 }; +static const unsigned int sdc2_clk_pins[] = { 211 }; +static const unsigned int sdc2_cmd_pins[] = { 212 }; +static const unsigned int sdc2_data_pins[] = { 213 }; + +enum sm8550_functions { + msm_mux_gpio, + msm_mux_aon_cci, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_aon_mclk4, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_coex_uart2_rx, + msm_mux_coex_uart2_tx, + msm_mux_cri_trng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2chub0_se5, + msm_mux_i2chub0_se6, + msm_mux_i2chub0_se7, + msm_mux_i2chub0_se8, + msm_mux_i2chub0_se9, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s1_data0, + msm_mux_i2s1_data1, + msm_mux_i2s1_sck, + msm_mux_i2s1_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qlink2_enable, + msm_mux_qlink2_request, + msm_mux_qlink2_wmss, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se0_l0_mira, + msm_mux_qup2_se0_l0_mirb, + msm_mux_qup2_se0_l1_mira, + msm_mux_qup2_se0_l1_mirb, + msm_mux_qup2_se0_l2_mira, + msm_mux_qup2_se0_l2_mirb, + msm_mux_qup2_se0_l3_mira, + msm_mux_qup2_se0_l3_mirb, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup2_se7, + msm_mux_resout_n, + msm_mux_sd_write_protect, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_tb_trig_sdc2, + msm_mux_tb_trig_sdc4, + msm_mux_tgu_ch0_trigout, + msm_mux_tgu_ch1_trigout, + msm_mux_tgu_ch2_trigout, + msm_mux_tgu_ch3_trigout, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb1_hs, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + +static const char * const aon_cci_groups[] = { + "gpio208", "gpio209", +}; + +static const char * const aoss_cti_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const atest_char_groups[] = { + "gpio130", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char *const atest_usb_groups[] = { + "gpio37", "gpio39", "gpio55", "gpio149", "gpio148", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio125", +}; + +static const char *const audio_ext_mclk1_groups[] = { + "gpio124", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio124", +}; + +static const char *const cam_aon_mclk4_groups[] = { + "gpio104", +}; + +static const char *const cam_mclk_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", + "gpio105", "gpio106", "gpio107", +}; + +static const char *const cci_async_in_groups[] = { + "gpio71", "gpio72", "gpio109", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio111", "gpio113", "gpio115", "gpio75", "gpio1", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio110", "gpio112", "gpio114", "gpio74", "gpio0", +}; + +static const char *const cci_timer_groups[] = { + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const cmu_rng_groups[] = { + "gpio129", "gpio128", "gpio127", "gpio122", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio148", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio149", +}; + +static const char *const coex_uart2_rx_groups[] = { + "gpio150", +}; + +static const char *const coex_uart2_tx_groups[] = { + "gpio151", +}; + +static const char *const cri_trng_groups[] = { + "gpio187", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio89", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio40", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio36", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio37", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio41", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio51", + "gpio52", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio40", + "gpio41", +}; + +static const char *const ddr_pxi2_groups[] = { + "gpio45", + "gpio47", +}; + +static const char *const ddr_pxi3_groups[] = { + "gpio43", + "gpio44", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio86", + "gpio134", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio87", + "gpio135", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio88", + "gpio136", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio16", + "gpio17", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio18", + "gpio19", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio20", + "gpio21", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio22", + "gpio23", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio4", + "gpio5", +}; + +static const char *const i2chub0_se5_groups[] = { + "gpio6", + "gpio7", +}; + +static const char *const i2chub0_se6_groups[] = { + "gpio8", + "gpio9", +}; + +static const char *const i2chub0_se7_groups[] = { + "gpio10", + "gpio11", +}; + +static const char *const i2chub0_se8_groups[] = { + "gpio206", + "gpio207", +}; + +static const char *const i2chub0_se9_groups[] = { + "gpio84", + "gpio85", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio127", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio128", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio126", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio129", +}; + +static const char *const i2s1_data0_groups[] = { + "gpio122", +}; + +static const char *const i2s1_data1_groups[] = { + "gpio124", +}; + +static const char *const i2s1_sck_groups[] = { + "gpio121", +}; + +static const char *const i2s1_ws_groups[] = { + "gpio123", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio28", "gpio29", "gpio32", + "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", +}; + +static const char *const jitter_bist_groups[] = { + "gpio43", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", + "gpio87", + "gpio133", + "gpio137", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio88", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio154", +}; + +static const char *const nav_gpio1_groups[] = { + "gpio155", +}; + +static const char *const nav_gpio2_groups[] = { + "gpio153", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio95", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio98", +}; + +static const char *const phase_flag_groups[] = { + "gpio0", "gpio2", "gpio3", "gpio10", "gpio11", "gpio12", "gpio13", "gpio59", + "gpio63", "gpio64", "gpio65", "gpio67", "gpio68", "gpio69", "gpio75", "gpio76", + "gpio77", "gpio79", "gpio80", "gpio81", "gpio92", "gpio83", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio116", "gpio117", "gpio119", "gpio120", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio20", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio107", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio186", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio183", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio182", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio181", +}; + +static const char *const qdss_cti_groups[] = { + "gpio10", "gpio11", "gpio75", "gpio79", + "gpio159", "gpio160", "gpio161", "gpio162", +}; + +static const char *const qdss_gpio_groups[] = { + "gpio59", "gpio64", "gpio73", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio120", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", + "gpio157", +}; + +static const char *const qlink0_enable_groups[] = { + "gpio157", +}; + +static const char *const qlink0_request_groups[] = { + "gpio156", +}; + +static const char *const qlink0_wmss_groups[] = { + "gpio158", +}; + +static const char *const qlink1_enable_groups[] = { + "gpio160", +}; + +static const char *const qlink1_request_groups[] = { + "gpio159", +}; + +static const char *const qlink1_wmss_groups[] = { + "gpio161", +}; + +static const char *const qlink2_enable_groups[] = { + "gpio163", +}; + +static const char *const qlink2_request_groups[] = { + "gpio162", +}; + +static const char *const qlink2_wmss_groups[] = { + "gpio164", +}; + +static const char *const qspi0_groups[] = { + "gpio89", +}; + +static const char *const qspi1_groups[] = { + "gpio90", +}; + +static const char *const qspi2_groups[] = { + "gpio48", +}; + +static const char *const qspi3_groups[] = { + "gpio49", +}; + +static const char *const qspi_clk_groups[] = { + "gpio50", +}; + +static const char *const qspi_cs_groups[] = { + "gpio51", "gpio91", +}; + +static const char *const qup1_se0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup1_se1_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio36", + "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se3_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char *const qup1_se4_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup1_se7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup2_se0_groups[] = { + "gpio63", "gpio66", "gpio67", +}; + +static const char *const qup2_se0_l0_mira_groups[] = { + "gpio56", +}; + +static const char *const qup2_se0_l0_mirb_groups[] = { + "gpio0", +}; + +static const char *const qup2_se0_l1_mira_groups[] = { + "gpio57", +}; + +static const char *const qup2_se0_l1_mirb_groups[] = { + "gpio1", +}; + +static const char *const qup2_se0_l2_mira_groups[] = { + "gpio58", +}; + +static const char *const qup2_se0_l2_mirb_groups[] = { + "gpio109", +}; + +static const char *const qup2_se0_l3_mira_groups[] = { + "gpio59", +}; + +static const char *const qup2_se0_l3_mirb_groups[] = { + "gpio107", +}; + +static const char *const qup2_se1_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se2_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char *const qup2_se3_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char *const qup2_se4_groups[] = { + "gpio2", "gpio3", "gpio118", "gpio119", +}; + +static const char *const qup2_se5_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup2_se6_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char *const qup2_se7_groups[] = { + "gpio72", "gpio106", "gpio74", "gpio75", +}; + +static const char * const resout_n_groups[] = { + "gpio92", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio93", +}; + +static const char *const sdc40_groups[] = { + "gpio89", +}; + +static const char *const sdc41_groups[] = { + "gpio90", +}; + +static const char *const sdc42_groups[] = { + "gpio48", +}; + +static const char *const sdc43_groups[] = { + "gpio49", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio50", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio51", +}; + +static const char * const tb_trig_sdc2_groups[] = { + "gpio64", +}; + +static const char * const tb_trig_sdc4_groups[] = { + "gpio91", +}; + +static const char * const tgu_ch0_trigout_groups[] = { + "gpio64", +}; + +static const char * const tgu_ch1_trigout_groups[] = { + "gpio65", +}; + +static const char * const tgu_ch2_trigout_groups[] = { + "gpio66", +}; + +static const char * const tgu_ch3_trigout_groups[] = { + "gpio67", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio92", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio94", +}; + +static const char *const tmess_prng2_groups[] = { + "gpio95", +}; + +static const char *const tmess_prng3_groups[] = { + "gpio96", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio50", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio50", +}; + +static const char *const tsense_pwm3_groups[] = { + "gpio50", +}; + +static const char *const uim0_clk_groups[] = { + "gpio131", +}; + +static const char *const uim0_data_groups[] = { + "gpio130", +}; + +static const char *const uim0_present_groups[] = { + "gpio27", +}; + +static const char *const uim0_reset_groups[] = { + "gpio132", +}; + +static const char *const uim1_clk_groups[] = { + "gpio135", +}; + +static const char *const uim1_data_groups[] = { + "gpio134", +}; + +static const char *const uim1_present_groups[] = { + "gpio26", +}; + +static const char *const uim1_reset_groups[] = { + "gpio136", +}; + +static const char *const usb1_hs_groups[] = { + "gpio90", +}; + +static const char *const usb_phy_groups[] = { + "gpio11", + "gpio48", +}; + +static const char *const vfr_0_groups[] = { + "gpio150", +}; + +static const char *const vfr_1_groups[] = { + "gpio155", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio24", +}; + +static const struct msm_function sm8550_functions[] = { + FUNCTION(gpio), + FUNCTION(aon_cci), + FUNCTION(aoss_cti), + FUNCTION(atest_char), + FUNCTION(atest_usb), + FUNCTION(audio_ext_mclk0), + FUNCTION(audio_ext_mclk1), + FUNCTION(audio_ref_clk), + FUNCTION(cam_aon_mclk4), + FUNCTION(cam_mclk), + FUNCTION(cci_async_in), + FUNCTION(cci_i2c_scl), + FUNCTION(cci_i2c_sda), + FUNCTION(cci_timer), + FUNCTION(cmu_rng), + FUNCTION(coex_uart1_rx), + FUNCTION(coex_uart1_tx), + FUNCTION(coex_uart2_rx), + FUNCTION(coex_uart2_tx), + FUNCTION(cri_trng), + FUNCTION(dbg_out_clk), + FUNCTION(ddr_bist_complete), + FUNCTION(ddr_bist_fail), + FUNCTION(ddr_bist_start), + FUNCTION(ddr_bist_stop), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(dp_hot), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(i2chub0_se0), + FUNCTION(i2chub0_se1), + FUNCTION(i2chub0_se2), + FUNCTION(i2chub0_se3), + FUNCTION(i2chub0_se4), + FUNCTION(i2chub0_se5), + FUNCTION(i2chub0_se6), + FUNCTION(i2chub0_se7), + FUNCTION(i2chub0_se8), + FUNCTION(i2chub0_se9), + FUNCTION(i2s0_data0), + FUNCTION(i2s0_data1), + FUNCTION(i2s0_sck), + FUNCTION(i2s0_ws), + FUNCTION(i2s1_data0), + FUNCTION(i2s1_data1), + FUNCTION(i2s1_sck), + FUNCTION(i2s1_ws), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0_out), + FUNCTION(mdp_vsync1_out), + FUNCTION(mdp_vsync2_out), + FUNCTION(mdp_vsync3_out), + FUNCTION(mdp_vsync_e), + FUNCTION(nav_gpio0), + FUNCTION(nav_gpio1), + FUNCTION(nav_gpio2), + FUNCTION(pcie0_clk_req_n), + FUNCTION(pcie1_clk_req_n), + FUNCTION(phase_flag), + FUNCTION(pll_bist_sync), + FUNCTION(pll_clk_aux), + FUNCTION(prng_rosc0), + FUNCTION(prng_rosc1), + FUNCTION(prng_rosc2), + FUNCTION(prng_rosc3), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qlink0_enable), + FUNCTION(qlink0_request), + FUNCTION(qlink0_wmss), + FUNCTION(qlink1_enable), + FUNCTION(qlink1_request), + FUNCTION(qlink1_wmss), + FUNCTION(qlink2_enable), + FUNCTION(qlink2_request), + FUNCTION(qlink2_wmss), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup1_se0), + FUNCTION(qup1_se1), + FUNCTION(qup1_se2), + FUNCTION(qup1_se3), + FUNCTION(qup1_se4), + FUNCTION(qup1_se5), + FUNCTION(qup1_se6), + FUNCTION(qup1_se7), + FUNCTION(qup2_se0), + FUNCTION(qup2_se0_l0_mira), + FUNCTION(qup2_se0_l0_mirb), + FUNCTION(qup2_se0_l1_mira), + FUNCTION(qup2_se0_l1_mirb), + FUNCTION(qup2_se0_l2_mira), + FUNCTION(qup2_se0_l2_mirb), + FUNCTION(qup2_se0_l3_mira), + FUNCTION(qup2_se0_l3_mirb), + FUNCTION(qup2_se1), + FUNCTION(qup2_se2), + FUNCTION(qup2_se3), + FUNCTION(qup2_se4), + FUNCTION(qup2_se5), + FUNCTION(qup2_se6), + FUNCTION(qup2_se7), + FUNCTION(resout_n), + FUNCTION(sd_write_protect), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(tb_trig_sdc2), + FUNCTION(tb_trig_sdc4), + FUNCTION(tgu_ch0_trigout), + FUNCTION(tgu_ch1_trigout), + FUNCTION(tgu_ch2_trigout), + FUNCTION(tgu_ch3_trigout), + FUNCTION(tmess_prng0), + FUNCTION(tmess_prng1), + FUNCTION(tmess_prng2), + FUNCTION(tmess_prng3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsense_pwm3), + FUNCTION(uim0_clk), + FUNCTION(uim0_data), + FUNCTION(uim0_present), + FUNCTION(uim0_reset), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(usb1_hs), + FUNCTION(usb_phy), + FUNCTION(vfr_0), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger_mirnat), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8550_groups[] = { + [0] = PINGROUP(0, cci_i2c_sda, qup2_se0_l0_mirb, ibi_i3c, phase_flag, _, _, _, _, _), + [1] = PINGROUP(1, cci_i2c_scl, qup2_se0_l1_mirb, ibi_i3c, _, _, _, _, _, _), + [2] = PINGROUP(2, qup2_se4, phase_flag, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup2_se4, phase_flag, _, _, _, _, _, _, _), + [4] = PINGROUP(4, i2chub0_se4, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, i2chub0_se4, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, i2chub0_se5, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, i2chub0_se5, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, i2chub0_se6, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, i2chub0_se6, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, i2chub0_se7, qdss_cti, phase_flag, _, _, _, _, _, _), + [11] = PINGROUP(11, i2chub0_se7, usb_phy, qdss_cti, phase_flag, _, _, _, _, _), + [12] = PINGROUP(12, phase_flag, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, phase_flag, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, _, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, i2chub0_se0, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, i2chub0_se0, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, i2chub0_se1, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, i2chub0_se1, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, i2chub0_se2, pll_bist_sync, _, _, _, _, _, _, _), + [21] = PINGROUP(21, i2chub0_se2, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, i2chub0_se3, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, i2chub0_se3, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup1_se7, vsense_trigger_mirnat, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup1_se7, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup1_se7, uim1_present, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup1_se7, uim0_present, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup1_se0, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup1_se0, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup1_se1, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup1_se1, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se2, ddr_bist_fail, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se2, ddr_bist_start, _, atest_usb, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se2, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se2, _, atest_usb, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se3, qup1_se2, ddr_bist_complete, _, ddr_pxi1, _, _, _, _), + [41] = PINGROUP(41, qup1_se3, qup1_se2, ddr_bist_stop, _, ddr_pxi1, _, _, _, _), + [42] = PINGROUP(42, qup1_se3, qup1_se2, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se3, jitter_bist, ddr_pxi3, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se4, aoss_cti, ddr_pxi3, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se4, aoss_cti, ddr_pxi2, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se4, aoss_cti, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se4, aoss_cti, dp_hot, ddr_pxi2, _, _, _, _, _), + [48] = PINGROUP(48, usb_phy, qup1_se6, qspi2, sdc42, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se6, qspi3, sdc43, _, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se6, qspi_clk, sdc4_clk, tsense_pwm1, tsense_pwm2, tsense_pwm3, _, _, _), + [51] = PINGROUP(51, qup1_se6, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), + [52] = PINGROUP(52, _, qup1_se5, ddr_pxi0, _, _, _, _, _, _), + [53] = PINGROUP(53, _, qup1_se5, _, _, _, _, _, _, _), + [54] = PINGROUP(54, _, qup1_se5, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, atest_usb, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup2_se0_l0_mira, ibi_i3c, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup2_se0_l1_mira, ibi_i3c, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup2_se0_l2_mira, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup2_se0_l3_mira, phase_flag, _, qdss_gpio, _, _, _, _, _), + [60] = PINGROUP(60, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup2_se1, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup2_se1, qup2_se0, phase_flag, _, _, _, _, _, _), + [64] = PINGROUP(64, qup2_se2, tb_trig_sdc2, phase_flag, tgu_ch0_trigout, _, qdss_gpio, _, _, _), + [65] = PINGROUP(65, qup2_se2, phase_flag, tgu_ch1_trigout, _, _, _, _, _, _), + [66] = PINGROUP(66, qup2_se2, qup2_se0, tgu_ch2_trigout, _, _, _, _, _, _), + [67] = PINGROUP(67, qup2_se2, qup2_se0, phase_flag, tgu_ch3_trigout, _, _, _, _, _), + [68] = PINGROUP(68, qup2_se3, phase_flag, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup2_se3, phase_flag, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup2_se3, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_async_in, qup2_se3, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cci_async_in, qup2_se7, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qdss_gpio, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cci_i2c_sda, qup2_se7, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cci_i2c_scl, qup2_se7, qdss_cti, phase_flag, _, _, _, _, _), + [76] = PINGROUP(76, qup2_se6, phase_flag, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup2_se6, phase_flag, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup2_se6, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qup2_se6, qdss_cti, phase_flag, _, _, _, _, _, _), + [80] = PINGROUP(80, qup2_se5, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup2_se5, phase_flag, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qup2_se5, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qup2_se5, phase_flag, _, _, _, _, _, _, _), + [84] = PINGROUP(84, i2chub0_se9, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, i2chub0_se9, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp1, _, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, gcc_gp2, _, _, _, _, _), + [88] = PINGROUP(88, mdp_vsync_e, gcc_gp3, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qspi0, sdc40, dbg_out_clk, _, _, _, _, _, _), + [90] = PINGROUP(90, usb1_hs, qspi1, sdc41, _, _, _, _, _, _), + [91] = PINGROUP(91, qspi_cs, tb_trig_sdc4, _, _, _, _, _, _, _), + [92] = PINGROUP(92, resout_n, phase_flag, tmess_prng0, _, _, _, _, _, _), + [93] = PINGROUP(93, sd_write_protect, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, phase_flag, tmess_prng1, _, _, _, _, _, _, _), + [95] = PINGROUP(95, pcie0_clk_req_n, phase_flag, tmess_prng2, _, _, _, _, _, _), + [96] = PINGROUP(96, phase_flag, tmess_prng3, _, _, _, _, _, _, _), + [97] = PINGROUP(97, phase_flag, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, pcie1_clk_req_n, phase_flag, _, _, _, _, _, _, _), + [99] = PINGROUP(99, phase_flag, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [104] = PINGROUP(104, cam_aon_mclk4, qdss_gpio, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, cam_mclk, qup2_se7, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cam_mclk, qup2_se0_l3_mirb, pll_clk_aux, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_async_in, qup2_se0_l2_mirb, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), + [117] = PINGROUP(117, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), + [118] = PINGROUP(118, qup2_se4, cci_timer, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup2_se4, cci_timer, phase_flag, _, _, _, _, _, _), + [120] = PINGROUP(120, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), + [121] = PINGROUP(121, i2s1_sck, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, i2s1_data0, cmu_rng, _, _, _, _, _, _, _), + [123] = PINGROUP(123, i2s1_ws, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, i2s1_data1, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _), + [125] = PINGROUP(125, audio_ext_mclk0, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, i2s0_sck, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, i2s0_data0, cmu_rng, _, _, _, _, _, _, _), + [128] = PINGROUP(128, i2s0_data1, cmu_rng, _, _, _, _, _, _, _), + [129] = PINGROUP(129, i2s0_ws, cmu_rng, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim0_data, atest_char, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim0_reset, atest_char, _, _, _, _, _, _, _), + [133] = PINGROUP(133, mdp_vsync, atest_char, _, _, _, _, _, _, _), + [134] = PINGROUP(134, uim1_data, gcc_gp1, atest_char, _, _, _, _, _, _), + [135] = PINGROUP(135, uim1_clk, gcc_gp2, atest_char, _, _, _, _, _, _), + [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), + [137] = PINGROUP(137, mdp_vsync, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, qdss_gpio, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, qdss_gpio, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, qdss_gpio, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, qdss_gpio, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, qdss_gpio, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, qdss_gpio, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, qdss_gpio, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, qdss_gpio, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, coex_uart1_rx, qdss_gpio, atest_usb, _, _, _, _, _, _), + [149] = PINGROUP(149, coex_uart1_tx, qdss_gpio, atest_usb, _, _, _, _, _, _), + [150] = PINGROUP(150, coex_uart2_rx, _, vfr_0, qdss_gpio, _, _, _, _, _), + [151] = PINGROUP(151, coex_uart2_tx, _, qdss_gpio, _, _, _, _, _, _), + [152] = PINGROUP(152, _, qdss_gpio, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, nav_gpio2, qdss_gpio, _, _, _, _, _, _), + [154] = PINGROUP(154, nav_gpio0, qdss_gpio, _, _, _, _, _, _, _), + [155] = PINGROUP(155, nav_gpio1, vfr_1, qdss_gpio, _, _, _, _, _, _), + [156] = PINGROUP(156, qlink0_request, qdss_gpio, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qlink0_enable, qdss_gpio, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qlink1_request, qdss_cti, _, _, _, _, _, _, _), + [160] = PINGROUP(160, qlink1_enable, qdss_cti, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qlink1_wmss, qdss_cti, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qlink2_request, qdss_cti, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), + [181] = PINGROUP(181, prng_rosc3, _, _, _, _, _, _, _, _), + [182] = PINGROUP(182, prng_rosc2, _, _, _, _, _, _, _, _), + [183] = PINGROUP(183, prng_rosc1, _, _, _, _, _, _, _, _), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), + [186] = PINGROUP(186, prng_rosc0, _, _, _, _, _, _, _, _), + [187] = PINGROUP(187, cri_trng, _, _, _, _, _, _, _, _), + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _), + [192] = PINGROUP(192, _, _, _, _, _, _, _, _, _), + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _), + [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _), + [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _), + [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _), + [206] = PINGROUP(206, i2chub0_se8, _, _, _, _, _, _, _, _), + [207] = PINGROUP(207, i2chub0_se8, _, _, _, _, _, _, _, _), + [208] = PINGROUP(208, aon_cci, _, _, _, _, _, _, _, _), + [209] = PINGROUP(209, aon_cci, _, _, _, _, _, _, _, _), + [210] = UFS_RESET(ufs_reset, 0xde000), + [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), + [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), + [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sm8550_pdc_map[] = { + { 0, 118 }, { 2, 90 }, { 3, 101 }, { 8, 60 }, { 9, 67 }, + { 11, 103 }, { 14, 136 }, { 15, 78 }, { 16, 138 }, { 17, 80 }, + { 18, 71 }, { 19, 59 }, { 25, 57 }, { 26, 74 }, { 27, 76 }, + { 28, 62 }, { 31, 88 }, { 32, 63 }, { 35, 124 }, { 39, 92 }, + { 40, 77 }, { 41, 83 }, { 43, 86 }, { 44, 75 }, { 45, 93 }, + { 46, 96 }, { 47, 64 }, { 48, 110 }, { 51, 89 }, { 55, 95 }, + { 56, 68 }, { 59, 87 }, { 60, 65 }, { 62, 100 }, { 63, 81 }, + { 67, 79 }, { 71, 102 }, { 73, 82 }, { 75, 72 }, { 79, 140 }, + { 82, 105 }, { 83, 104 }, { 84, 126 }, { 85, 142 }, { 86, 106 }, + { 87, 107 }, { 88, 61 }, { 89, 111 }, { 95, 108 }, { 96, 109 }, + { 98, 97 }, { 99, 58 }, { 107, 139 }, { 119, 94 }, { 120, 135 }, + { 133, 52 }, { 137, 84 }, { 148, 66 }, { 150, 73 }, { 153, 70 }, + { 154, 53 }, { 155, 69 }, { 156, 54 }, { 159, 55 }, { 162, 56 }, + { 166, 116 }, { 169, 119 }, { 171, 120 }, { 172, 85 }, { 174, 98 }, + { 176, 112 }, { 177, 51 }, { 181, 114 }, { 182, 115 }, { 185, 117 }, + { 187, 91 }, { 188, 123 }, { 190, 127 }, { 191, 113 }, { 192, 128 }, + { 193, 129 }, { 196, 133 }, { 197, 134 }, { 198, 50 }, { 199, 99 }, + { 200, 49 }, { 201, 48 }, { 203, 125 }, { 205, 141 }, { 206, 137 }, + { 207, 47 }, { 208, 121 }, { 209, 122 }, +}; + +static const struct msm_pinctrl_soc_data sm8550_tlmm = { + .pins = sm8550_pins, + .npins = ARRAY_SIZE(sm8550_pins), + .functions = sm8550_functions, + .nfunctions = ARRAY_SIZE(sm8550_functions), + .groups = sm8550_groups, + .ngroups = ARRAY_SIZE(sm8550_groups), + .ngpios = 211, + .wakeirq_map = sm8550_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8550_pdc_map), + .egpio_func = 9, +}; + +static int sm8550_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8550_tlmm); +} + +static const struct of_device_id sm8550_tlmm_of_match[] = { + { .compatible = "qcom,sm8550-tlmm", }, + {}, +}; + +static struct platform_driver sm8550_tlmm_driver = { + .driver = { + .name = "sm8550-tlmm", + .of_match_table = sm8550_tlmm_of_match, + }, + .probe = sm8550_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8550_tlmm_init(void) +{ + return platform_driver_register(&sm8550_tlmm_driver); +} +arch_initcall(sm8550_tlmm_init); + +static void __exit sm8550_tlmm_exit(void) +{ + platform_driver_unregister(&sm8550_tlmm_driver); +} +module_exit(sm8550_tlmm_exit); + +MODULE_DESCRIPTION("QTI SM8550 TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); From a7cc0e2685082a0d79baec02df184dfa83cbfac3 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 31 Dec 2022 17:42:50 +0100 Subject: [PATCH 043/118] pinctrl: qcom: pinctrl-msm8976: Correct function names for wcss pins Adjust names of function for wcss pins, also fix third gpio in bt group. Fixes: bcd11493f0ab ("pinctrl: qcom: Add a pinctrl driver for MSM8976 and 8956") Signed-off-by: Adam Skladowski Reviewed-by: Marijn Suijten Link: https://lore.kernel.org/r/20221231164250.74550-1-a39.skl@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm8976.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index ec43edf9b660a..e11d845847190 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -733,7 +733,7 @@ static const char * const codec_int2_groups[] = { "gpio74", }; static const char * const wcss_bt_groups[] = { - "gpio39", "gpio47", "gpio88", + "gpio39", "gpio47", "gpio48", }; static const char * const sdc3_groups[] = { "gpio39", "gpio40", "gpio41", @@ -958,9 +958,9 @@ static const struct msm_pingroup msm8976_groups[] = { PINGROUP(37, NA, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA), PINGROUP(39, wcss_bt, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), - PINGROUP(40, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), - PINGROUP(41, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), - PINGROUP(42, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(40, wcss_wlan2, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(41, wcss_wlan1, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(42, wcss_wlan0, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA), PINGROUP(43, wcss_wlan, sdc3, NA, NA, qdss_tracedata_a, NA, NA, NA, NA), PINGROUP(44, wcss_wlan, sdc3, NA, NA, NA, NA, NA, NA, NA), PINGROUP(45, wcss_fm, NA, qdss_tracectl_a, NA, NA, NA, NA, NA, NA), From dcef18c8ac40aa85bb339f64c1dd31dd458b06fb Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Mon, 2 Jan 2023 12:24:56 +0400 Subject: [PATCH 044/118] pinctrl: stm32: Fix refcount leak in stm32_pctrl_get_irq_domain of_irq_find_parent() returns a node pointer with refcount incremented, We should use of_node_put() on it when not needed anymore. Add missing of_node_put() to avoid refcount leak. Fixes: d86f4d71e42a ("pinctrl: stm32: check irq controller availability at probe") Signed-off-by: Miaoqian Lin Link: https://lore.kernel.org/r/20230102082503.3944927-1-linmq006@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 1cddca506ad7e..cb33a23ab0c11 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1382,6 +1382,7 @@ static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pde return ERR_PTR(-ENXIO); domain = irq_find_host(parent); + of_node_put(parent); if (!domain) /* domain not registered yet */ return ERR_PTR(-EPROBE_DEFER); From c818ae563bf99457f02e8170aabd6b174f629f65 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Mon, 2 Jan 2023 15:28:45 +0400 Subject: [PATCH 045/118] pinctrl: rockchip: Fix refcount leak in rockchip_pinctrl_parse_groups of_find_node_by_phandle() returns a node pointer with refcount incremented, We should use of_node_put() on it when not needed anymore. Add missing of_node_put() to avoid refcount leak. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Signed-off-by: Miaoqian Lin Link: https://lore.kernel.org/r/20230102112845.3982407-1-linmq006@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index da974ff2d75d0..0bc3dc2220fdc 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3036,6 +3036,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); ret = pinconf_generic_parse_dt_config(np_config, NULL, &grp->data[j].configs, &grp->data[j].nconfigs); + of_node_put(np_config); if (ret) return ret; } From b754f00dd90dd86cda39ca3d733cd00bbbbf2fe9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 18 Nov 2022 09:24:39 +0100 Subject: [PATCH 046/118] dt-bindings: pinctrl: qcom,pmic-gpio: document pm8550, pm8550b, pm8550ve, pm8550vs, pmk8550 & pmr735d Document compatible, pin count & pin names for pm8550, pm8550b, pm8550ve, pm8550vs, pmk8550 & pmr735d SPMI GPIO controllers. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221114-narmstrong-sm8550-upstream-spmi-v2-2-b839bf2d558a@linaro.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,pmic-gpio.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 29dd503f95221..db505fdeac86f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -40,6 +40,10 @@ properties: - qcom,pm8350b-gpio - qcom,pm8350c-gpio - qcom,pm8450-gpio + - qcom,pm8550-gpio + - qcom,pm8550b-gpio + - qcom,pm8550ve-gpio + - qcom,pm8550vs-gpio - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio @@ -52,10 +56,12 @@ properties: - qcom,pmi8994-gpio - qcom,pmi8998-gpio - qcom,pmk8350-gpio + - qcom,pmk8550-gpio - qcom,pmm8155au-gpio - qcom,pmp8074-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio + - qcom,pmr735d-gpio - qcom,pms405-gpio - qcom,pmx55-gpio - qcom,pmx65-gpio @@ -111,6 +117,7 @@ allOf: enum: - qcom,pm8008-gpio - qcom,pmi8950-gpio + - qcom,pmr735d-gpio then: properties: gpio-line-names: @@ -146,6 +153,8 @@ allOf: enum: - qcom,pm8018-gpio - qcom,pm8019-gpio + - qcom,pm8550vs-gpio + - qcom,pmk8550-gpio then: properties: gpio-line-names: @@ -162,6 +171,7 @@ allOf: enum: - qcom,pm8226-gpio - qcom,pm8350b-gpio + - qcom,pm8550ve-gpio - qcom,pm8950-gpio then: properties: @@ -236,6 +246,8 @@ allOf: - qcom,pm8038-gpio - qcom,pm8150b-gpio - qcom,pm8150l-gpio + - qcom,pm8550-gpio + - qcom,pm8550b-gpio - qcom,pmc8180c-gpio - qcom,pmp8074-gpio - qcom,pms405-gpio @@ -411,6 +423,10 @@ $defs: - gpio1-gpio8 for pm8350b - gpio1-gpio9 for pm8350c - gpio1-gpio4 for pm8450 + - gpio1-gpio12 for pm8550 + - gpio1-gpio12 for pm8550b + - gpio1-gpio8 for pm8550ve + - gpio1-gpio6 for pm8550vs - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 - gpio1-gpio36 for pm8941 @@ -421,10 +437,12 @@ $defs: - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio4 for pmk8350 + - gpio1-gpio6 for pmk8550 - gpio1-gpio10 for pmm8155au - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) - gpio1-gpio4 for pmr735a - gpio1-gpio4 for pmr735b + - gpio1-gpio2 for pmr735d - gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 From e8c39b3eba42311b4e6ba5a41676acabefe9b858 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 18 Nov 2022 09:24:40 +0100 Subject: [PATCH 047/118] pinctrl: qcom: spmi-gpio: add support for pm8550 & pmr735d gpio control Add support for the pm8550, pm8550b, pm8550ve, pm8550vs, pmk8550 & pmr735d gpio controllers providing GPIO control over SPMI. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20221114-narmstrong-sm8550-upstream-spmi-v2-3-b839bf2d558a@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 89695b5a2ce73..66d6d7ffbd432 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1221,6 +1221,10 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8550-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8550b-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 }, { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, /* pm8950 has 8 GPIOs with holes on 3 */ @@ -1232,11 +1236,13 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, /* pmp8074 has 12 GPIOs with holes on 1 and 12 */ { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmr735d-gpio", .data = (void *) 2 }, /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ From f4720b845b15456719d88bb8408d82cb5ea6132b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 4 Jan 2023 10:14:30 +0800 Subject: [PATCH 048/118] dt-bindings: pinctrl: imx8m: Integrate duplicated i.MX 8M schemas The i.MX8MM/N/P/Q IOMUXC schemas are basically the same, it does not to have four schemas for almost the same binding. Signed-off-by: Peng Fan Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230104021430.3503497-1-peng.fan@oss.nxp.com Signed-off-by: Linus Walleij --- ...mm-pinctrl.yaml => fsl,imx8m-pinctrl.yaml} | 24 ++++-- .../bindings/pinctrl/fsl,imx8mn-pinctrl.yaml | 84 ------------------- .../bindings/pinctrl/fsl,imx8mp-pinctrl.yaml | 84 ------------------- .../bindings/pinctrl/fsl,imx8mq-pinctrl.yaml | 84 ------------------- 4 files changed, 15 insertions(+), 261 deletions(-) rename Documentation/devicetree/bindings/pinctrl/{fsl,imx8mm-pinctrl.yaml => fsl,imx8m-pinctrl.yaml} (76%) delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml similarity index 76% rename from Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml index 6717f163390b2..7ae0843972585 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml @@ -1,13 +1,13 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale IMX8MM IOMUX Controller +title: Freescale IMX8M IOMUX Controller maintainers: - - Anson Huang + - Peng Fan description: Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory @@ -15,7 +15,11 @@ description: properties: compatible: - const: fsl,imx8mm-iomuxc + enum: + - fsl,imx8mm-iomuxc + - fsl,imx8mn-iomuxc + - fsl,imx8mp-iomuxc + - fsl,imx8mq-iomuxc reg: maxItems: 1 @@ -34,9 +38,10 @@ patternProperties: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can - be found in . The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Mini Reference Manual for detailed CONFIG settings. + be found in . + The last integer CONFIG is the pad setting value like pull-up on this + pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for + detailed CONFIG settings. $ref: /schemas/types.yaml#/definitions/uint32-matrix items: items: @@ -51,7 +56,8 @@ patternProperties: - description: | "input_val" indicates the select input value to be applied. - description: | - "pad_setting" indicates the pad configuration value to be applied. + "pad_setting" indicates the pad configuration value to be + applied. required: - fsl,pins diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml deleted file mode 100644 index b1cdbb56d4e40..0000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml +++ /dev/null @@ -1,84 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX8MN IOMUX Controller - -maintainers: - - Anson Huang - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -properties: - compatible: - const: fsl,imx8mn-iomuxc - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can - be found in . The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Nano Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. - - required: - - fsl,pins - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mn-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_uart2: uart2grp { - fsl,pins = - <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, - <0x240 0x4A8 0x000 0x0 0x0 0x140>; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml deleted file mode 100644 index 4eed3a4e153a0..0000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml +++ /dev/null @@ -1,84 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX8MP IOMUX Controller - -maintainers: - - Anson Huang - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -properties: - compatible: - const: fsl,imx8mp-iomuxc - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can - be found in . The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. - - required: - - fsl,pins - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mp-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_uart2: uart2grp { - fsl,pins = - <0x228 0x488 0x5F0 0x0 0x6 0x49>, - <0x228 0x488 0x000 0x0 0x0 0x49>; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml deleted file mode 100644 index d4a8ea5551a5f..0000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml +++ /dev/null @@ -1,84 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Freescale IMX8MQ IOMUX Controller - -maintainers: - - Anson Huang - -description: - Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory - for common binding part and usage. - -properties: - compatible: - const: fsl,imx8mq-iomuxc - - reg: - maxItems: 1 - -# Client device subnode's properties -patternProperties: - 'grp$': - type: object - description: - Pinctrl node's client devices use subnodes for desired pin configuration. - Client device subnodes use below standard properties. - - properties: - fsl,pins: - description: - each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can - be found in . The last - integer CONFIG is the pad setting value like pull-up on this pin. Please - refer to i.MX8M Quad Reference Manual for detailed CONFIG settings. - $ref: /schemas/types.yaml#/definitions/uint32-matrix - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. - - required: - - fsl,pins - - additionalProperties: false - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - -additionalProperties: false - -examples: - # Pinmux controller node - - | - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_uart1: uart1grp { - fsl,pins = - <0x234 0x49C 0x4F4 0x0 0x0 0x49>, - <0x238 0x4A0 0x4F4 0x0 0x0 0x49>; - }; - }; - -... From ef6c2d856632b0fd10e60c93950d4d89e99a0ada Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Fri, 6 Jan 2023 13:44:01 +0200 Subject: [PATCH 049/118] dt-bindings: pinctrl: msm8226: Add General Purpose clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the general purpose clock functions that are found on MSM8226. Signed-off-by: Matti Lehtimäki Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230106114403.275865-2-matti.lehtimaki@gmail.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml index 3b79f5be860ba..6e3808065845e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -66,8 +66,8 @@ $defs: enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2, - blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3, - wlan ] + blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, + gp0_clk, gp1_clk, sdc3, wlan ] bias-pull-down: true bias-pull-up: true From 814ee08d9ea9f234fedbca29f9d96990f3fc06b3 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 6 Jan 2023 13:44:02 +0200 Subject: [PATCH 050/118] pinctrl: qcom: msm8226: Add General Purpose clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the general purpose clocks that are found on MSM8226. Signed-off-by: Luca Weiss Co-developed-by: Matti Lehtimäki Signed-off-by: Matti Lehtimäki Link: https://lore.kernel.org/r/20230106114403.275865-3-matti.lehtimaki@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm8226.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index fca0645e8008d..0f05725e0a211 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -362,6 +362,8 @@ enum msm8226_functions { MSM_MUX_cam_mclk0, MSM_MUX_cam_mclk1, MSM_MUX_cci_i2c0, + MSM_MUX_gp0_clk, + MSM_MUX_gp1_clk, MSM_MUX_gpio, MSM_MUX_sdc3, MSM_MUX_wlan, @@ -447,6 +449,9 @@ static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" }; static const char * const cam_mclk0_groups[] = { "gpio26" }; static const char * const cam_mclk1_groups[] = { "gpio27" }; +static const char * const gp0_clk_groups[] = { "gpio33" }; +static const char * const gp1_clk_groups[] = { "gpio34" }; + static const char * const sdc3_groups[] = { "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" }; @@ -480,6 +485,8 @@ static const struct msm_function msm8226_functions[] = { FUNCTION(cam_mclk0), FUNCTION(cam_mclk1), FUNCTION(cci_i2c0), + FUNCTION(gp0_clk), + FUNCTION(gp1_clk), FUNCTION(gpio), FUNCTION(sdc3), FUNCTION(wlan), @@ -519,8 +526,8 @@ static const struct msm_pingroup msm8226_groups[] = { PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA), PINGROUP(31, NA, NA, NA, NA, NA, NA, NA), PINGROUP(32, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, gp0_clk, NA, NA, NA, NA), + PINGROUP(34, NA, NA, gp1_clk, NA, NA, NA, NA), PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), From 8bb5811129f9e40fb5f3aef6807b3920881140b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 18 Nov 2022 23:44:04 +0100 Subject: [PATCH 051/118] pinctrl: mcp23s08: Convert to i2c's .probe_new() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit .probe_new() doesn't get the i2c_device_id * parameter, so determine that explicitly in the probe function. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20221118224540.619276-511-uwe@kleine-koenig.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08_i2c.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c index e0b001c8c08c0..b635c5737e0c5 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c +++ b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c @@ -8,8 +8,9 @@ #include "pinctrl-mcp23s08.h" -static int mcp230xx_probe(struct i2c_client *client, const struct i2c_device_id *id) +static int mcp230xx_probe(struct i2c_client *client) { + const struct i2c_device_id *id = i2c_client_get_device_id(client); struct device *dev = &client->dev; unsigned int type = id->driver_data; struct mcp23s08 *mcp; @@ -100,7 +101,7 @@ static struct i2c_driver mcp230xx_driver = { .name = "mcp230xx", .of_match_table = mcp23s08_i2c_of_match, }, - .probe = mcp230xx_probe, + .probe_new = mcp230xx_probe, .id_table = mcp230xx_id, }; From 091e81b867796130a08be162ff8d9332492de26e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 9 Jan 2023 15:27:19 +0200 Subject: [PATCH 052/118] pinctrl: pinmux: Drop duplicate error message in pinmux_select() pinctrl_get_group_selector() prints an error message when group is not found in the list. No need to repeat this in the caller. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230109132719.86009-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinmux.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 6bd7ac37a0e0e..0213826326080 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -744,10 +744,8 @@ static ssize_t pinmux_select(struct file *file, const char __user *user_buf, } ret = pinctrl_get_group_selector(pctldev, gname); - if (ret < 0) { - dev_err(pctldev->dev, "failed to get group selector for %s", gname); + if (ret < 0) goto exit_free_buf; - } gsel = ret; ret = pmxops->set_mux(pctldev, fsel, gsel); From 3ecc01c5e0682dee4819eac3d67a4c07f113fda4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 23 Dec 2022 14:22:26 +0100 Subject: [PATCH 053/118] dt-bindings: pinctrl: qcom,sm8450-tlmm: correct gpio-line-names size The SM8450 has GPIOs from 0 to 209, so 210 in total: sm8450-sony-xperia-nagara-pdx223.dtb: pinctrl@f100000: gpio-line-names: ['NC', 'NC', 'NC', 'NC', 'WLC_I2C_SDA', 'WLC_I2C_SCL', ... 'APPS_I2C_0_SDA', 'APPS_I2C_0_SCL', 'CCI_I2C3_SDA', 'CCI_I2C3_SCL'] is too long Fixes: 9779ed30f92c ("dt-bindings: pinctrl: qcom,sm8450-pinctrl: add gpio-line-names") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20221223132226.81340-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml index 4a1d10d6c5e7e..b5356d0f89f97 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml @@ -32,7 +32,7 @@ properties: maxItems: 105 gpio-line-names: - maxItems: 209 + maxItems: 210 "#gpio-cells": true gpio-ranges: true From 697550668be5c1edbd0a7347ecbe6769dc54ccc9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 22 Dec 2022 17:14:20 +0100 Subject: [PATCH 054/118] dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: add input-enable and bias-bus-hold Allow bias-bus-hold and input-enable properties (already used in SM8450): sm8450-qrd.dtb: pinctrl@3440000: dmic02-default-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+' 'input-enable' does not match any of the regexes: 'pinctrl-[0-9]+' Compact the properties which are just set to true for readability. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Link: https://lore.kernel.org/r/20221222161420.172824-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index 01a0a4a40ba57..e04d094d19465 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -96,14 +96,12 @@ $defs: 2: Lower Slew rate (slower edges) 3: Reserved (No adjustments) + bias-bus-hold: true bias-pull-down: true - bias-pull-up: true - bias-disable: true - + input-enable: true output-high: true - output-low: true required: From 9eef05e606387b597a86d071f3d72e8ee3e68df7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 21 Nov 2022 09:12:21 +0100 Subject: [PATCH 055/118] dt-bindings: pinctrl: qcom,sdm845-pinctrl: add GPIO hogs Allow GPIO hogs in pin controller node. qcom/sdm845-cheza.dtsi already uses it. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221121081221.30745-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml index c9627777ceb32..18ddcfe2e088f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -48,6 +48,10 @@ patternProperties: $ref: "#/$defs/qcom-sdm845-tlmm-state" additionalProperties: false + "-hog(-[0-9]+)?$": + required: + - gpio-hog + $defs: qcom-sdm845-tlmm-state: type: object @@ -117,6 +121,7 @@ additionalProperties: false examples: - | + #include #include pinctrl@3400000 { @@ -130,6 +135,12 @@ examples: gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc_intc>; + ap-suspend-l-hog { + gpio-hog; + gpios = <126 GPIO_ACTIVE_LOW>; + output-low; + }; + cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; From 3c90b1ba8cc49b3c485e4477b9977e52a16509d3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:37 +0100 Subject: [PATCH 056/118] dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: correct pins pattern SC8280XP LPASS LPI pin controller has GPIO 0-18: sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+' 'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+' 'gpio2' does not match '^gpio([0-1]|1[0-8])$' Fixes: 958bb025f5b3 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings") Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221230135645.56401-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml index 7d2589387e1ae..309d3dd9013ba 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -65,7 +65,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: - pattern: "^gpio([0-1]|1[0-8])$" + pattern: "^gpio([0-9]|1[0-8])$" function: enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, From a880fafbbac7e229752fb59bed56f55944dbe0e9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:38 +0100 Subject: [PATCH 057/118] dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: add input-enable and bias-bus-hold Allow bias-bus-hold and input-enable properties (already used in SC8280XP LPASS LPI nodes): sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+' 'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20221230135645.56401-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml index 309d3dd9013ba..9a3f1fb8c2f73 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -94,14 +94,12 @@ $defs: 2: Lower Slew rate (slower edges) 3: Reserved (No adjustments) + bias-bus-hold: true bias-pull-down: true - bias-pull-up: true - bias-disable: true - + input-enable: true output-high: true - output-low: true required: From d3431ec2f7cc0bb77f367d27d68fc79650ece864 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:39 +0100 Subject: [PATCH 058/118] dt-bindings: pinctrl: qcom,sm6350-tlmm: add gpio-line-names Allow gpio-line-names property (quite commonly used) and constrain gpio-reserved-ranges. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221230135645.56401-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml index 41e3e0afc9a88..b099649e58f77 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml @@ -26,7 +26,14 @@ properties: interrupt-controller: true "#interrupt-cells": true gpio-controller: true - gpio-reserved-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + "#gpio-cells": true gpio-ranges: true wakeup-parent: true From 86a8754b08de4d9d5bd1f31b56283efb8763b8c7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:40 +0100 Subject: [PATCH 059/118] dt-bindings: pinctrl: qcom,sm8350-tlmm: add gpio-line-names Allow gpio-line-names property (quite commonly used) and constrain gpio-reserved-ranges: sm8350-sony-xperia-sagami-pdx215.dtb: pinctrl@f100000: 'gpio-line-names' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221230135645.56401-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index 0b1e4aa5819e6..7795cae01e268 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -26,7 +26,14 @@ properties: interrupt-controller: true "#interrupt-cells": true gpio-controller: true - gpio-reserved-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 102 + + gpio-line-names: + maxItems: 203 + "#gpio-cells": true gpio-ranges: true wakeup-parent: true From 72283404c2bc82bd7f7196a58f0e14b948e77173 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:41 +0100 Subject: [PATCH 060/118] dt-bindings: pinctrl: qcom,sm6350-tlmm: correct pins pattern SM6350 TLMM pin controller has GPIOs 0-155. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221230135645.56401-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml index b099649e58f77..39f3ec5b71879 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml @@ -68,7 +68,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 From 45277153d46500ce7f4a1637412f0db7c208300a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:42 +0100 Subject: [PATCH 061/118] dt-bindings: pinctrl: qcom,sm8350-tlmm: correct pins pattern SM8350 TLMM pin controller has GPIOs 0-202. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221230135645.56401-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index 7795cae01e268..7b483e93bfe18 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -68,7 +68,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 From 12a18bb74f7500693bdfb6af2f99c05d2d43f9c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Dec 2022 14:56:43 +0100 Subject: [PATCH 062/118] dt-bindings: pinctrl: qcom: allow nine interrupts on SM6350 Almost all Qualcomm SoC Top Level Mode Multiplexers come with only summary interrupt. SM6350 is different because downstream and upstream DTS have nine of the interrupts. Allow such variation. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221230135645.56401-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,ipq8074-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,mdm9607-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,mdm9615-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8660-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8909-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8916-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8953-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8960-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8974-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8976-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8994-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8996-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,msm8998-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,qcm2290-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,qcs404-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sc7180-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sc8180x-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sc8280xp-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sdm630-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sdm670-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sdx65-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sm6115-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sm6125-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sm6350-tlmm.yaml | 16 ++++++++++++++-- .../bindings/pinctrl/qcom,sm6375-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sm8150-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 4 +++- .../bindings/pinctrl/qcom,sm8350-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,sm8450-tlmm.yaml | 4 +++- .../bindings/pinctrl/qcom,tlmm-common.yaml | 5 +++-- 34 files changed, 113 insertions(+), 36 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml index 93f231c7a3b43..28f1b6a07b70d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml index 5687acaf19bfa..3137db927fc0a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml index a0a12171b6d0d..96b598bf9a76f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml index a4f6e4c588f42..c7c94d742ed2b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml index 3b79f5be860ba..ab6672a4c8c12 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -20,7 +20,9 @@ properties: description: Specifies the base address and size of the TLMM register space maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml index ad0cad4694c0d..348d84c3cd216 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml index cc6d0c9c51001..449e6e34be616 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml index 5495f58905af0..633c9e5ed49e0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index c9a4a79e8d01b..6bcd520808016 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml index 33d07d5312730..cf386f644ccb0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml index 9287cbbff7111..afe4a80f0b796 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml index 858f45710fe26..5dfcc3eadbb0c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml index 55d5439c6c249..f4a8180f59590 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml index 8e1cd4ba11164..047b4584e3c01 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml index 21ba32cc204aa..c07ee98680460 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml @@ -20,7 +20,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml index adf64bfaa4ed3..6271fd15e0b67 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml index 29d50c4a0034c..20bc967a17b5a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml @@ -26,7 +26,9 @@ properties: - const: north - const: east - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml index b40f6dc6adaec..f33792a1af6c6 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml @@ -26,7 +26,9 @@ properties: - const: north - const: south - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml index 24191d5f64acd..0ace55c9868ed 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml @@ -28,7 +28,9 @@ properties: - const: east - const: south - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml index 4efde29c36a26..97b27d6835e98 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml index bd4fd8404aa4c..ea6bd0b44f569 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml @@ -31,7 +31,9 @@ properties: - const: center - const: north - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml index 7585117c0f06e..f586b3aa138e5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml index 18ddcfe2e088f..23d7c030fec0a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -23,7 +23,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index a76117e41d930..add3c7e64520b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -20,7 +20,9 @@ properties: description: Specifies the base address and size of the TLMM register space maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml index 2f53905260e61..89c5562583d15 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml @@ -19,7 +19,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml index 164f24db8b2b6..29325483cd2b7 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml @@ -26,7 +26,9 @@ properties: - const: south - const: east - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml index e1dd54a160d55..c9bc4893e8e8a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml @@ -27,7 +27,9 @@ properties: - const: south - const: east - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml index 39f3ec5b71879..d95935fcc8b5a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml @@ -22,7 +22,10 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + minItems: 9 + maxItems: 9 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true @@ -125,7 +128,16 @@ examples: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; reg = <0x0f100000 0x300000>; - interrupts = ; + interrupts = , + , + , + , + , + , + , + , + ; + gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml index d54ebb2bd5a8f..e4231d10d76f5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml index 85adddbdee566..4376a9bd4d70d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml @@ -27,7 +27,9 @@ properties: - const: north - const: south - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index c80f3847ac087..56e058c315f75 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -25,7 +25,9 @@ properties: - const: south - const: north - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index 7b483e93bfe18..49a74f351e996 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml index 4a1d10d6c5e7e..451faad12a667 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml @@ -22,7 +22,9 @@ properties: reg: maxItems: 1 - interrupts: true + interrupts: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": true gpio-controller: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index e1354f0c64f82..cb5ba1bd6f8d2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -16,8 +16,9 @@ description: properties: interrupts: description: - Specifies the TLMM summary IRQ - maxItems: 1 + TLMM summary IRQ and dirconn interrupts. + minItems: 1 + maxItems: 9 interrupt-controller: true From 542c893caa7bc2e5263fe0a4e17d228f9b3d0acd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 18 Nov 2022 23:44:05 +0100 Subject: [PATCH 063/118] pinctrl: sx150x: Convert to i2c's .probe_new() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit .probe_new() doesn't get the i2c_device_id * parameter, so determine that explicitly in the probe function. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20221118224540.619276-512-uwe@kleine-koenig.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sx150x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index a87ea3b95cf47..0b5ff99641e1b 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1094,9 +1094,9 @@ static const struct regmap_config sx150x_regmap_config = { .volatile_reg = sx150x_reg_volatile, }; -static int sx150x_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int sx150x_probe(struct i2c_client *client) { + const struct i2c_device_id *id = i2c_client_get_device_id(client); static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA; struct device *dev = &client->dev; @@ -1252,7 +1252,7 @@ static struct i2c_driver sx150x_driver = { .name = "sx150x-pinctrl", .of_match_table = of_match_ptr(sx150x_of_match), }, - .probe = sx150x_probe, + .probe_new = sx150x_probe, .id_table = sx150x_id, }; From 525792d1d22d2178ee8fad49eaa4b54e0dac76be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 31 Dec 2022 19:08:44 +0300 Subject: [PATCH 064/118] pinctrl: ralink: rename variables which point out the pin group MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These variables define a list of functions which can be muxed to the pin group which the name of the pin group was originally intended to be pointed out on the name of the said variables. Therefore, rename "func" to "grp" across all subdrivers where this applies. Fixes: 18653d4bd8ab ("pinctrl: ralink: rename variable names for functions on MT7620 and MT7621") Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20221231160849.40544-2-arinc.unal@arinc9.com Signed-off-by: Linus Walleij --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 164 ++++++++++++------------ drivers/pinctrl/ralink/pinctrl-mt7621.c | 48 +++---- drivers/pinctrl/ralink/pinctrl-rt2880.c | 28 ++-- drivers/pinctrl/ralink/pinctrl-rt305x.c | 82 ++++++------ drivers/pinctrl/ralink/pinctrl-rt3883.c | 44 +++---- 5 files changed, 183 insertions(+), 183 deletions(-) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 22ff16eff02ff..4e8d26bb34302 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -54,20 +54,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func mdio_func[] = { +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct ralink_pmx_func rgmii1_func[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct ralink_pmx_func refclk_func[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct ralink_pmx_func ephy_func[] = { FUNC("ephy", 0, 40, 5) }; -static struct ralink_pmx_func rgmii2_func[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct ralink_pmx_func wled_func[] = { FUNC("wled", 0, 72, 1) }; -static struct ralink_pmx_func pa_func[] = { FUNC("pa", 0, 18, 4) }; -static struct ralink_pmx_func uartf_func[] = { +static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; +static struct ralink_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; +static struct ralink_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; +static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; +static struct ralink_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; +static struct ralink_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; +static struct ralink_pmx_func uartf_grp[] = { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -76,202 +76,202 @@ static struct ralink_pmx_func uartf_func[] = { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func wdt_func[] = { +static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct ralink_pmx_func pcie_rst_func[] = { +static struct ralink_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct ralink_pmx_func nd_sd_func[] = { +static struct ralink_pmx_func nd_sd_grp[] = { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; static struct ralink_pmx_group mt7620a_pinmux_data[] = { - GRP("i2c", i2c_func, 1, MT7620_GPIO_MODE_I2C), - GRP("uartf", uartf_func, MT7620_GPIO_MODE_UART0_MASK, + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), - GRP("spi", spi_func, 1, MT7620_GPIO_MODE_SPI), - GRP("uartlite", uartlite_func, 1, MT7620_GPIO_MODE_UART1), - GRP_G("wdt", wdt_func, MT7620_GPIO_MODE_WDT_MASK, + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), - GRP_G("mdio", mdio_func, MT7620_GPIO_MODE_MDIO_MASK, + GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii1", rgmii1_func, 1, MT7620_GPIO_MODE_RGMII1), - GRP("spi refclk", refclk_func, 1, MT7620_GPIO_MODE_SPI_REF_CLK), - GRP_G("pcie", pcie_rst_func, MT7620_GPIO_MODE_PCIE_MASK, + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), - GRP_G("nd_sd", nd_sd_func, MT7620_GPIO_MODE_ND_SD_MASK, + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), - GRP("rgmii2", rgmii2_func, 1, MT7620_GPIO_MODE_RGMII2), - GRP("wled", wled_func, 1, MT7620_GPIO_MODE_WLED), - GRP("ephy", ephy_func, 1, MT7620_GPIO_MODE_EPHY), - GRP("pa", pa_func, 1, MT7620_GPIO_MODE_PA), + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), { 0 } }; -static struct ralink_pmx_func pwm1_func_mt76x8[] = { +static struct ralink_pmx_func pwm1_grp_mt76x8[] = { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; -static struct ralink_pmx_func pwm0_func_mt76x8[] = { +static struct ralink_pmx_func pwm0_grp_mt76x8[] = { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; -static struct ralink_pmx_func uart2_func_mt76x8[] = { +static struct ralink_pmx_func uart2_grp_mt76x8[] = { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; -static struct ralink_pmx_func uart1_func_mt76x8[] = { +static struct ralink_pmx_func uart1_grp_mt76x8[] = { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; -static struct ralink_pmx_func i2c_func_mt76x8[] = { +static struct ralink_pmx_func i2c_grp_mt76x8[] = { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; -static struct ralink_pmx_func refclk_func_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; -static struct ralink_pmx_func perst_func_mt76x8[] = { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_func_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_func_mt76x8[] = { FUNC("spi", 0, 7, 4) }; +static struct ralink_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; +static struct ralink_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; -static struct ralink_pmx_func sd_mode_func_mt76x8[] = { +static struct ralink_pmx_func sd_mode_grp_mt76x8[] = { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; -static struct ralink_pmx_func uart0_func_mt76x8[] = { +static struct ralink_pmx_func uart0_grp_mt76x8[] = { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; -static struct ralink_pmx_func i2s_func_mt76x8[] = { +static struct ralink_pmx_func i2s_grp_mt76x8[] = { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; -static struct ralink_pmx_func spi_cs1_func_mt76x8[] = { +static struct ralink_pmx_func spi_cs1_grp_mt76x8[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; -static struct ralink_pmx_func spis_func_mt76x8[] = { +static struct ralink_pmx_func spis_grp_mt76x8[] = { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; -static struct ralink_pmx_func gpio_func_mt76x8[] = { +static struct ralink_pmx_func gpio_grp_mt76x8[] = { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; -static struct ralink_pmx_func p4led_kn_func_mt76x8[] = { +static struct ralink_pmx_func p4led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; -static struct ralink_pmx_func p3led_kn_func_mt76x8[] = { +static struct ralink_pmx_func p3led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; -static struct ralink_pmx_func p2led_kn_func_mt76x8[] = { +static struct ralink_pmx_func p2led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; -static struct ralink_pmx_func p1led_kn_func_mt76x8[] = { +static struct ralink_pmx_func p1led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; -static struct ralink_pmx_func p0led_kn_func_mt76x8[] = { +static struct ralink_pmx_func p0led_kn_grp_mt76x8[] = { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; -static struct ralink_pmx_func wled_kn_func_mt76x8[] = { +static struct ralink_pmx_func wled_kn_grp_mt76x8[] = { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; -static struct ralink_pmx_func p4led_an_func_mt76x8[] = { +static struct ralink_pmx_func p4led_an_grp_mt76x8[] = { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; -static struct ralink_pmx_func p3led_an_func_mt76x8[] = { +static struct ralink_pmx_func p3led_an_grp_mt76x8[] = { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; -static struct ralink_pmx_func p2led_an_func_mt76x8[] = { +static struct ralink_pmx_func p2led_an_grp_mt76x8[] = { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; -static struct ralink_pmx_func p1led_an_func_mt76x8[] = { +static struct ralink_pmx_func p1led_an_grp_mt76x8[] = { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; -static struct ralink_pmx_func p0led_an_func_mt76x8[] = { +static struct ralink_pmx_func p0led_an_grp_mt76x8[] = { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; -static struct ralink_pmx_func wled_an_func_mt76x8[] = { +static struct ralink_pmx_func wled_an_grp_mt76x8[] = { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), @@ -309,55 +309,55 @@ static struct ralink_pmx_func wled_an_func_mt76x8[] = { #define MT76X8_GPIO_MODE_GPIO 0 static struct ralink_pmx_group mt76x8_pinmux_data[] = { - GRP_G("pwm1", pwm1_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_UART2), - GRP_G("uart1", uart1_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_UART1), - GRP_G("i2c", i2c_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_I2C), - GRP("refclk", refclk_func_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), - GRP("perst", perst_func_mt76x8, 1, MT76X8_GPIO_MODE_PERST), - GRP("wdt", wdt_func_mt76x8, 1, MT76X8_GPIO_MODE_WDT), - GRP("spi", spi_func_mt76x8, 1, MT76X8_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_UART0), - GRP_G("i2s", i2s_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_CS1), - GRP_G("spis", spis_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_func_mt76x8, MT76X8_GPIO_MODE_MASK, + GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_P4LED_KN), { 0 } }; diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index b47968f40e0c2..eddc0ba6d468c 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -34,59 +34,59 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 -static struct ralink_pmx_func uart1_func[] = { FUNC("uart1", 0, 1, 2) }; -static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 3, 2) }; -static struct ralink_pmx_func uart3_func[] = { +static struct ralink_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; +static struct ralink_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct ralink_pmx_func uart2_func[] = { +static struct ralink_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 13, 5) }; -static struct ralink_pmx_func wdt_func[] = { +static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; +static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct ralink_pmx_func pcie_rst_func[] = { +static struct ralink_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 20, 2) }; -static struct ralink_pmx_func rgmii2_func[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct ralink_pmx_func spi_func[] = { +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; +static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct ralink_pmx_func sdhci_func[] = { +static struct ralink_pmx_func sdhci_grp[] = { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct ralink_pmx_func rgmii1_func[] = { FUNC("rgmii1", 0, 49, 12) }; +static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; static struct ralink_pmx_group mt7621_pinmux_data[] = { - GRP("uart1", uart1_func, 1, MT7621_GPIO_MODE_UART1), - GRP("i2c", i2c_func, 1, MT7621_GPIO_MODE_I2C), - GRP_G("uart3", uart3_func, MT7621_GPIO_MODE_UART3_MASK, + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), + GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), - GRP_G("uart2", uart2_func, MT7621_GPIO_MODE_UART2_MASK, + GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), - GRP("jtag", jtag_func, 1, MT7621_GPIO_MODE_JTAG), - GRP_G("wdt", wdt_func, MT7621_GPIO_MODE_WDT_MASK, + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), - GRP_G("pcie", pcie_rst_func, MT7621_GPIO_MODE_PCIE_MASK, + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), - GRP_G("mdio", mdio_func, MT7621_GPIO_MODE_MDIO_MASK, + GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii2", rgmii2_func, 1, MT7621_GPIO_MODE_RGMII2), - GRP_G("spi", spi_func, MT7621_GPIO_MODE_SPI_MASK, + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), - GRP_G("sdhci", sdhci_func, MT7621_GPIO_MODE_SDHCI_MASK, + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), - GRP("rgmii1", rgmii1_func, 1, MT7621_GPIO_MODE_RGMII1), + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), { 0 } }; diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c index 811e12df11331..3e2f1aaaf0957 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -15,22 +15,22 @@ #define RT2880_GPIO_MODE_SDRAM BIT(6) #define RT2880_GPIO_MODE_PCI BIT(7) -static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; -static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 7, 8) }; +static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct ralink_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; +static struct ralink_pmx_func pci_grp[] = { FUNC("pci", 0, 40, 32) }; static struct ralink_pmx_group rt2880_pinmux_data_act[] = { - GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI), - GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0), - GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO), - GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM), - GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI), + GRP("i2c", i2c_grp, 1, RT2880_GPIO_MODE_I2C), + GRP("spi", spi_grp, 1, RT2880_GPIO_MODE_SPI), + GRP("uartlite", uartlite_grp, 1, RT2880_GPIO_MODE_UART0), + GRP("jtag", jtag_grp, 1, RT2880_GPIO_MODE_JTAG), + GRP("mdio", mdio_grp, 1, RT2880_GPIO_MODE_MDIO), + GRP("sdram", sdram_grp, 1, RT2880_GPIO_MODE_SDRAM), + GRP("pci", pci_grp, 1, RT2880_GPIO_MODE_PCI), { 0 } }; diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index 5b204b7ca1f3c..bdaee5ce1ee08 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -31,9 +31,9 @@ #define RT3352_GPIO_MODE_LNA 18 #define RT3352_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_func[] = { +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartf_grp[] = { FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), @@ -42,65 +42,65 @@ static struct ralink_pmx_func uartf_func[] = { FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; -static struct ralink_pmx_func rt5350_cs1_func[] = { +static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct ralink_pmx_func rt5350_led_grp[] = { FUNC("led", 0, 22, 5) }; +static struct ralink_pmx_func rt5350_cs1_grp[] = { FUNC("spi_cs1", 0, 27, 1), FUNC("wdg_cs1", 1, 27, 1), }; -static struct ralink_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func rt3352_rgmii_func[] = { +static struct ralink_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; +static struct ralink_pmx_func rt3352_rgmii_grp[] = { FUNC("rgmii", 0, 24, 12) }; -static struct ralink_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; -static struct ralink_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; -static struct ralink_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; -static struct ralink_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; -static struct ralink_pmx_func rt3352_cs1_func[] = { +static struct ralink_pmx_func rgmii_grp[] = { FUNC("rgmii", 0, 40, 12) }; +static struct ralink_pmx_func rt3352_lna_grp[] = { FUNC("lna", 0, 36, 2) }; +static struct ralink_pmx_func rt3352_pa_grp[] = { FUNC("pa", 0, 38, 2) }; +static struct ralink_pmx_func rt3352_led_grp[] = { FUNC("led", 0, 40, 5) }; +static struct ralink_pmx_func rt3352_cs1_grp[] = { FUNC("spi_cs1", 0, 45, 1), FUNC("wdg_cs1", 1, 45, 1), }; static struct ralink_pmx_group rt3050_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, + GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), + GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), + GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), - GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), - GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), + GRP("uartlite", uartlite_grp, 1, RT305X_GPIO_MODE_UART1), + GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG), + GRP("mdio", mdio_grp, 1, RT305X_GPIO_MODE_MDIO), + GRP("rgmii", rgmii_grp, 1, RT305X_GPIO_MODE_RGMII), + GRP("sdram", sdram_grp, 1, RT305X_GPIO_MODE_SDRAM), { 0 } }; static struct ralink_pmx_group rt3352_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, + GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), + GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), + GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), - GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), - GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), - GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), - GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), - GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), + GRP("uartlite", uartlite_grp, 1, RT305X_GPIO_MODE_UART1), + GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG), + GRP("mdio", mdio_grp, 1, RT305X_GPIO_MODE_MDIO), + GRP("rgmii", rt3352_rgmii_grp, 1, RT305X_GPIO_MODE_RGMII), + GRP("lna", rt3352_lna_grp, 1, RT3352_GPIO_MODE_LNA), + GRP("pa", rt3352_pa_grp, 1, RT3352_GPIO_MODE_PA), + GRP("led", rt3352_led_grp, 1, RT5350_GPIO_MODE_PHY_LED), + GRP("spi_cs1", rt3352_cs1_grp, 2, RT5350_GPIO_MODE_SPI_CS1), { 0 } }; static struct ralink_pmx_group rt5350_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, + GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), + GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), + GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), - GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), + GRP("uartlite", uartlite_grp, 1, RT305X_GPIO_MODE_UART1), + GRP("jtag", jtag_grp, 1, RT305X_GPIO_MODE_JTAG), + GRP("led", rt5350_led_grp, 1, RT5350_GPIO_MODE_PHY_LED), + GRP("spi_cs1", rt5350_cs1_grp, 2, RT5350_GPIO_MODE_SPI_CS1), { 0 } }; diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index 44a66c3d2d2a1..392208662355d 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -39,9 +39,9 @@ #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) -static struct ralink_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_func[] = { +static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct ralink_pmx_func uartf_grp[] = { FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), @@ -50,34 +50,34 @@ static struct ralink_pmx_func uartf_func[] = { FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; -static struct ralink_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) }; -static struct ralink_pmx_func pci_func[] = { +static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct ralink_pmx_func lna_a_grp[] = { FUNC("lna a", 0, 32, 3) }; +static struct ralink_pmx_func lna_g_grp[] = { FUNC("lna g", 0, 35, 3) }; +static struct ralink_pmx_func pci_grp[] = { FUNC("pci-dev", 0, 40, 32), FUNC("pci-host2", 1, 40, 32), FUNC("pci-host1", 2, 40, 32), FUNC("pci-fnc", 3, 40, 32) }; -static struct ralink_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) }; -static struct ralink_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) }; +static struct ralink_pmx_func ge1_grp[] = { FUNC("ge1", 0, 72, 12) }; +static struct ralink_pmx_func ge2_grp[] = { FUNC("ge2", 0, 84, 12) }; static struct ralink_pmx_group rt3883_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK, + GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C), + GRP("spi", spi_grp, 1, RT3883_GPIO_MODE_SPI), + GRP("uartf", uartf_grp, RT3883_GPIO_MODE_UART0_MASK, RT3883_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO), - GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A), - GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G), - GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK, + GRP("uartlite", uartlite_grp, 1, RT3883_GPIO_MODE_UART1), + GRP("jtag", jtag_grp, 1, RT3883_GPIO_MODE_JTAG), + GRP("mdio", mdio_grp, 1, RT3883_GPIO_MODE_MDIO), + GRP("lna a", lna_a_grp, 1, RT3883_GPIO_MODE_LNA_A), + GRP("lna g", lna_g_grp, 1, RT3883_GPIO_MODE_LNA_G), + GRP("pci", pci_grp, RT3883_GPIO_MODE_PCI_MASK, RT3883_GPIO_MODE_PCI_SHIFT), - GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1), - GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2), + GRP("ge1", ge1_grp, 1, RT3883_GPIO_MODE_GE1), + GRP("ge2", ge2_grp, 1, RT3883_GPIO_MODE_GE2), { 0 } }; From 4e5410668af5475681793df2bb8c7d8dc6f9c327 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 31 Dec 2022 19:08:45 +0300 Subject: [PATCH 065/118] dt-bindings: pinctrl: mt7620: add proper function muxing binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not every function can be muxed to a group. Add proper binding which documents which function can be muxed to a group or set of groups. Signed-off-by: Arınç ÜNAL Acked-by: Krzysztof Kozlowski Acked-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20221231160849.40544-3-arinc.unal@arinc9.com Signed-off-by: Linus Walleij --- .../pinctrl/ralink,mt7620-pinctrl.yaml | 633 +++++++++++++++++- 1 file changed, 597 insertions(+), 36 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml index 6f17f39916400..1e63ea34146a5 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -29,47 +29,609 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [ - # common - i2c, spi, wdt, - - # For MT7620 SoC - ephy, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi refclk, - uartf, uartlite, wled, - - # For MT7628 and MT7688 SoCs - gpio, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, - p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0, - pwm1, refclk, sdmode, spi cs1, spis, uart0, uart1, uart2, - wled_an, wled_kn, - ] - function: - description: The mux function to select. - enum: [ - # common - gpio, i2c, refclk, spi, - - # For MT7620 SoC - ephy, gpio i2s, gpio uartf, i2s uartf, mdio, nand, pa, - pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, - rgmii1, rgmii2, sd, spi refclk, uartf, uartlite, wdt refclk, - wdt rst, wled, - - # For MT7628 and MT7688 SoCs - antenna, debug, i2s, jtag, p0led_an, p0led_kn, - p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, - p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, - rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi cs1, - spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -, - ] + description: + A string containing the name of the function to mux to the group. + anyOf: + - description: For MT7620 SoC + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa, + pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk, + rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk, + wdt rst, wled] + + - description: For MT7628 and MT7688 SoCs + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, + refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1, + spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 required: - groups - function + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: ephy + then: + properties: + groups: + enum: [ephy] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + anyOf: + - description: For MT7620 SoC + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, + spi, spi refclk, uartf, uartlite, wdt, wled] + + - description: For MT7628 and MT7688 SoCs + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, + p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, perst, pwm0, pwm1, refclk, + sdmode, spi, spi cs1, spis, uart0, uart1, uart2, + wdt, wled_an, wled_kn] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: nand + then: + properties: + groups: + enum: [nd_sd] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcie refclk + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcie rst + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + anyOf: + - description: For MT7620 SoC + enum: [mdio] + + - description: For MT7628 and MT7688 SoCs + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rgmii1 + then: + properties: + groups: + enum: [rgmii1] + + - if: + properties: + function: + const: rgmii2 + then: + properties: + groups: + enum: [rgmii2] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sd + then: + properties: + groups: + enum: [nd_sd] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spi refclk + then: + properties: + groups: + enum: [spi refclk] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt refclk + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt rst + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled + then: + properties: + groups: + enum: [wled] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + additionalProperties: false additionalProperties: false @@ -83,7 +645,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,mt7620-pinctrl"; From 0c9a567651c3b5d433429da2c7d8e8406ddf1076 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 31 Dec 2022 19:08:46 +0300 Subject: [PATCH 066/118] dt-bindings: pinctrl: mt7621: add proper function muxing binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not every function can be muxed to a group. Add proper binding which documents which function can be muxed to a group or set of groups. Signed-off-by: Arınç ÜNAL Acked-by: Krzysztof Kozlowski Acked-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20221231160849.40544-4-arinc.unal@arinc9.com Signed-off-by: Linus Walleij --- .../pinctrl/ralink,mt7621-pinctrl.yaml | 205 +++++++++++++++++- 1 file changed, 198 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml index 61e5c847e8c8b..1b1d37b981d9b 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -29,21 +29,213 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1, - uart2, uart3, wdt] - function: - description: The mux function to select. + description: + A string containing the name of the function to mux to the group. enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi, uart1, uart2, uart3, wdt refclk, wdt rst] + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + required: - groups - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, + uart1, uart2, uart3, wdt] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: nand1 + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: nand2 + then: + properties: + groups: + enum: [sdhci] + + - if: + properties: + function: + const: pcie refclk + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcie rst + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: rgmii1 + then: + properties: + groups: + enum: [rgmii1] + + - if: + properties: + function: + const: rgmii2 + then: + properties: + groups: + enum: [rgmii2] + + - if: + properties: + function: + const: sdhci + then: + properties: + groups: + enum: [sdhci] + + - if: + properties: + function: + const: spdif2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: spdif3 + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: uart3 + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: wdt refclk + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt rst + then: + properties: + groups: + enum: [wdt] + additionalProperties: false additionalProperties: false @@ -57,7 +249,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,mt7621-pinctrl"; From b4ac84395820eaa0b99ec56816e53c9386ca8b38 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 31 Dec 2022 19:08:47 +0300 Subject: [PATCH 067/118] dt-bindings: pinctrl: rt2880: add proper function muxing binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not every function can be muxed to a group. Add proper binding which documents which function can be muxed to a group or set of groups. Signed-off-by: Arınç ÜNAL Acked-by: Krzysztof Kozlowski Acked-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20221231160849.40544-5-arinc.unal@arinc9.com Signed-off-by: Linus Walleij --- .../pinctrl/ralink,rt2880-pinctrl.yaml | 86 +++++++++++++++++-- 1 file changed, 80 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index 56e5becabcfdd..7fd0df880a762 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -29,18 +29,93 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] - function: - description: The mux function to select. + description: + A string containing the name of the function to mux to the group. enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci] + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + required: - groups - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: sdram + then: + properties: + groups: + enum: [sdram] + + - if: + properties: + function: + const: pci + then: + properties: + groups: + enum: [pci] + additionalProperties: false additionalProperties: false @@ -54,7 +129,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,rt2880-pinctrl"; From d648fd64e10d9d1609146d0c4e47b0f5988e2a2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 31 Dec 2022 19:08:48 +0300 Subject: [PATCH 068/118] dt-bindings: pinctrl: rt305x: add proper function muxing binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not every function can be muxed to a group. Add proper binding which documents which function can be muxed to a group or set of groups. Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Acked-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20221231160849.40544-6-arinc.unal@arinc9.com Signed-off-by: Linus Walleij --- .../pinctrl/ralink,rt305x-pinctrl.yaml | 236 ++++++++++++++++-- 1 file changed, 211 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index f602a5d6e13a6..4d66ca752a300 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -30,38 +30,225 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [ - # common - i2c, jtag, led, mdio, rgmii, spi, spi_cs1, uartf, uartlite, - - # For RT3050, RT3052 and RT3350 SoCs - sdram, - - # For RT3352 SoC - lna, pa - ] - function: - description: The mux function to select. - enum: [ - # common - gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, mdio, - pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf, - uartlite, wdg_cs1, + description: + A string containing the name of the function to mux to the group. + anyOf: + - description: For RT3050, RT3052 and RT3350 SoCs + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] - # For RT3050, RT3052 and RT3350 SoCs - sdram, + - description: For RT3352 SoC + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, + spi_cs1, uartf, uartlite, wdg_cs1] - # For RT3352 SoC - lna, pa - ] + - description: For RT5350 SoC + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, + uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 required: - groups - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + anyOf: + - description: For RT3050, RT3052 and RT3350 SoCs + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, + uartlite] + + - description: For RT3352 SoC + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, + uartf, uartlite] + + - description: For RT5350 SoC + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: sdram + then: + properties: + groups: + enum: [sdram] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + additionalProperties: false additionalProperties: false @@ -75,7 +262,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,rt305x-pinctrl"; From 844bca60927f3aae6baafafb1edd218b624254a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sat, 31 Dec 2022 19:08:49 +0300 Subject: [PATCH 069/118] dt-bindings: pinctrl: rt3883: add proper function muxing binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not every function can be muxed to a group. Add proper binding which documents which function can be muxed to a group or set of groups. Signed-off-by: Arınç ÜNAL Acked-by: Krzysztof Kozlowski Acked-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20221231160849.40544-7-arinc.unal@arinc9.com Signed-off-by: Linus Walleij --- .../pinctrl/ralink,rt3883-pinctrl.yaml | 205 +++++++++++++++++- 1 file changed, 198 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml index feb6e66dcb613..008d93181aea6 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -29,21 +29,213 @@ patternProperties: $ref: pinmux-node.yaml# properties: - groups: - description: The pin group to select. - enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf, - uartlite] - function: - description: The mux function to select. + description: + A string containing the name of the function to mux to the group. enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2, pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite] + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + required: - groups - function + allOf: + - if: + properties: + function: + const: ge1 + then: + properties: + groups: + enum: [ge1] + + - if: + properties: + function: + const: ge2 + then: + properties: + groups: + enum: [ge2] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: lna a + then: + properties: + groups: + enum: [lna a] + + - if: + properties: + function: + const: lna g + then: + properties: + groups: + enum: [lna g] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pci-dev + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-fnc + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-host1 + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-host2 + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + additionalProperties: false additionalProperties: false @@ -57,7 +249,6 @@ required: additionalProperties: false examples: - # Pinmux controller node - | pinctrl { compatible = "ralink,rt3883-pinctrl"; From 03a13546c74d8b3df9baceef1a747d9585ac77a7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 12 Jan 2023 15:48:49 +0200 Subject: [PATCH 070/118] pinctrl: samsung: Do not mention legacy API in the code Replace mentioning of legacy API by the latest one. Signed-off-by: Andy Shevchenko Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230112134849.59534-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 5736761927cbd..05f79868ef397 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -649,7 +649,7 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset, } /* - * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin + * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin * and a virtual IRQ, if not already present. */ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) From 0da58037aefcdc024a2bdad7d94cdf28f044a816 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 12 Jan 2023 20:43:40 +0200 Subject: [PATCH 071/118] pinctrl: mediatek: Remove duplicate assignment of of_gpio_n_cells The of_gpio_n_cells default is 2 when ->of_xlate() callback is not defined. No need to assign it explicitly in the driver. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230112184340.79606-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-moore.c | 1 - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 1 - drivers/pinctrl/mediatek/pinctrl-paris.c | 1 - 3 files changed, 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 1ec0413959e15..007b98ce56315 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -574,7 +574,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->set_config = mtk_gpio_set_config; chip->base = -1; chip->ngpio = hw->soc->npins; - chip->of_gpio_n_cells = 2; ret = gpiochip_add_data(chip, hw); if (ret < 0) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 553d16703475b..665dec419e7cb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -906,7 +906,6 @@ static const struct gpio_chip mtk_gpio_chip = { .set = mtk_gpio_set, .to_irq = mtk_gpio_to_irq, .set_config = mtk_gpio_set_config, - .of_gpio_n_cells = 2, }; static int mtk_eint_suspend(struct device *device) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 475f4172d5085..17eead44b6757 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -987,7 +987,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->set_config = mtk_gpio_set_config; chip->base = -1; chip->ngpio = hw->soc->npins; - chip->of_gpio_n_cells = 2; ret = gpiochip_add_data(chip, hw); if (ret < 0) From a3fc976a2d68cb74ae4234314002e4e398e4c337 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 12 Jan 2023 20:49:23 +0200 Subject: [PATCH 072/118] pinctrl: qcom: lpass-lpi: Remove duplicate assignment of of_gpio_n_cells The of_gpio_n_cells default is 2 when ->of_xlate() callback is not defined. No need to assign it explicitly in the driver. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230112184923.80442-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 3dc670faa59ec..87920257bb732 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -430,7 +430,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->chip.base = -1; pctrl->chip.ngpio = data->npins; pctrl->chip.label = dev_name(dev); - pctrl->chip.of_gpio_n_cells = 2; pctrl->chip.can_sleep = false; mutex_init(&pctrl->slew_access_lock); From ef4290e6bd99149d21c99bb4905c61f8c94a05ca Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 12 Jan 2023 20:51:22 +0200 Subject: [PATCH 073/118] pinctrl: sunplus: sppctl: Remove duplicate assignment of of_gpio_n_cells The of_gpio_n_cells default is 2 when ->of_xlate() callback is not defined. No need to assign it explicitly in the driver. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230112185122.45216-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sunplus/sppctl.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c index 2b3335ab56c66..392625a2723e4 100644 --- a/drivers/pinctrl/sunplus/sppctl.c +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -556,7 +556,6 @@ static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pc gchip->base = -1; gchip->ngpio = sppctl_gpio_list_sz; gchip->names = sppctl_gpio_list_s; - gchip->of_gpio_n_cells = 2; pctl->pctl_grange.npins = gchip->ngpio; pctl->pctl_grange.name = gchip->label; From aeb3c200db418207ae9aa426bd128527cb688b66 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 13 Jan 2023 16:36:39 +0200 Subject: [PATCH 074/118] pinctrl: digicolor: Remove duplicate assignment of of_gpio_n_cells The of_gpio_n_cells default is 2 when ->of_xlate() callback is not defined. No need to assign it explicitly in the driver. Signed-off-by: Andy Shevchenko Acked-by: Baruch Siach Link: https://lore.kernel.org/r/20230113143640.24302-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-digicolor.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c index cc3546fc46102..05213261b8a4b 100644 --- a/drivers/pinctrl/pinctrl-digicolor.c +++ b/drivers/pinctrl/pinctrl-digicolor.c @@ -248,7 +248,6 @@ static int dc_gpiochip_add(struct dc_pinmap *pmap) chip->set = dc_gpio_set; chip->base = -1; chip->ngpio = PINS_COUNT; - chip->of_gpio_n_cells = 2; spin_lock_init(&pmap->lock); From 083b0230e040c5857f8c0a76119e5997e449a35c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 13 Jan 2023 16:36:40 +0200 Subject: [PATCH 075/118] pinctrl: digicolor: Use proper headers and drop OF dependency The driver doesn't depend on the OF to be complied. Hence the proper header to use is mod_devicetable.h. Replace of*.h with the above mentioned and drop redundant dependency. Signed-off-by: Andy Shevchenko Acked-by: Baruch Siach Link: https://lore.kernel.org/r/20230113143640.24302-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl-digicolor.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7d5f5458c72ed..dcb53c4a9584b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -172,7 +172,7 @@ config PINCTRL_DA9062 config PINCTRL_DIGICOLOR bool - depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST) + depends on ARCH_DIGICOLOR || COMPILE_TEST select PINMUX select GENERIC_PINCONF diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c index 05213261b8a4b..a0423172bdd6d 100644 --- a/drivers/pinctrl/pinctrl-digicolor.c +++ b/drivers/pinctrl/pinctrl-digicolor.c @@ -11,18 +11,19 @@ * - Pin pad configuration (pull up/down, strength) */ +#include #include -#include -#include -#include #include -#include +#include +#include #include + #include #include #include #include #include + #include "pinctrl-utils.h" #define DRIVER_NAME "pinctrl-digicolor" From 6eea5a80d2ae9bc1df5664bcf7851306df96e9dc Mon Sep 17 00:00:00 2001 From: ye xingchen Date: Mon, 16 Jan 2023 15:45:23 +0800 Subject: [PATCH 076/118] pinctrl: nomadik: remove duplicate included header files linux/seq_file.h is included more than once. Signed-off-by: ye xingchen Link: https://lore.kernel.org/r/202301161545238948580@zte.com.cn Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 7aa534576a459..8fcaa3c25b2aa 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -442,8 +442,6 @@ static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, return ret; } -#include - static void abx500_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, struct gpio_chip *chip, From af6f64c68b9d961add00270f37ac291f151a029b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 12 Dec 2022 15:52:54 +0200 Subject: [PATCH 077/118] pinctrl: Proofreading and updating the documentation accordingly Proofreading and updating the documentation accordingly, i.e. fixed: - ambiguity of foo_set_mux() implementation and explanations - semantics in some of the examples, e.g. _probe() --> _init() - references to the callbacks to make them start with dot - references to the legacy API by replacing them with newer one - indentation in some of the examples - double words or phrases updated: - unsigned --> unsigned int in some of the examples - use struct pingroup and PINCTRL_PINGROUP() in some of the examples - use struct pinfunction and PINCTRL_PINFUNCTION() in some of the examples and enabled: - syntax highlighting for the examples in the programming languages - chapter references Yet to clarify: - "gpioN" menton for the default function when requesting GPIO Co-developed-by: Bagas Sanjaya Signed-off-by: Bagas Sanjaya Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- Documentation/driver-api/pin-control.rst | 414 +++++++++++------------ 1 file changed, 202 insertions(+), 212 deletions(-) diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index 0022e930e93e5..22a82ee23a415 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -11,7 +11,7 @@ This subsystem deals with: - Multiplexing of pins, pads, fingers (etc) see below for details - Configuration of pins, pads, fingers (etc), such as software-controlled - biasing and driving mode specific pins, such as pull-up/down, open drain, + biasing and driving mode specific pins, such as pull-up, pull-down, open drain, load capacitance etc. Top-level interface @@ -57,7 +57,9 @@ Here is an example of a PGA (Pin Grid Array) chip seen from underneath:: 1 o o o o o o o o To register a pin controller and name all the pins on this package we can do -this in our driver:: +this in our driver: + +.. code-block:: c #include @@ -78,14 +80,13 @@ this in our driver:: .owner = THIS_MODULE, }; - int __init foo_probe(void) + int __init foo_init(void) { int error; struct pinctrl_dev *pctl; - error = pinctrl_register_and_init(&foo_desc, , - NULL, &pctl); + error = pinctrl_register_and_init(&foo_desc, , NULL, &pctl); if (error) return error; @@ -95,7 +96,7 @@ this in our driver:: To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and selected drivers, you need to select them from your machine's Kconfig entry, since these are so tightly integrated with the machines they are used on. -See for example arch/arm/mach-ux500/Kconfig for an example. +See arch/arm/mach-ux500/Kconfig for an example. Pins usually have fancier names than this. You can find these in the datasheet for your chip. Notice that the core pinctrl.h file provides a fancy macro @@ -132,50 +133,38 @@ on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins on { 24, 25 }. These two groups are presented to the pin control subsystem by implementing -some generic pinctrl_ops like this:: +some generic pinctrl_ops like this: - #include +.. code-block:: c - struct foo_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; - }; + #include static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; static const unsigned int i2c0_pins[] = { 24, 25 }; - static const struct foo_group foo_groups[] = { - { - .name = "spi0_grp", - .pins = spi0_pins, - .num_pins = ARRAY_SIZE(spi0_pins), - }, - { - .name = "i2c0_grp", - .pins = i2c0_pins, - .num_pins = ARRAY_SIZE(i2c0_pins), - }, + static const struct pingroup foo_groups[] = { + PINCTRL_PINGROUP("spi0_grp", spi0_pins, ARRAY_SIZE(spi0_pins)), + PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)), }; - static int foo_get_groups_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(foo_groups); } static const char *foo_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned int selector) { return foo_groups[selector].name; } - static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) + static int foo_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) { - *pins = (unsigned *) foo_groups[selector].pins; - *num_pins = foo_groups[selector].num_pins; + *pins = foo_groups[selector].pins; + *npins = foo_groups[selector].npins; return 0; } @@ -185,10 +174,9 @@ some generic pinctrl_ops like this:: .get_group_pins = foo_get_group_pins, }; - static struct pinctrl_desc foo_desc = { - ... - .pctlops = &foo_pctrl_ops, + ... + .pctlops = &foo_pctrl_ops, }; The pin control subsystem will call the .get_groups_count() function to @@ -204,59 +192,62 @@ Pin configuration Pins can sometimes be software-configured in various ways, mostly related to their electronic properties when used as inputs or outputs. For example you -may be able to make an output pin high impedance, or "tristate" meaning it is +may be able to make an output pin high impedance (Hi-Z), or "tristate" meaning it is effectively disconnected. You may be able to connect an input pin to VDD or GND using a certain resistor value - pull up and pull down - so that the pin has a stable value when nothing is driving the rail it is connected to, or when it's unconnected. Pin configuration can be programmed by adding configuration entries into the -mapping table; see section "Board/machine configuration" below. +mapping table; see section `Board/machine configuration`_ below. The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP above, is entirely defined by the pin controller driver. The pin configuration driver implements callbacks for changing pin -configuration in the pin controller ops like this:: +configuration in the pin controller ops like this: + +.. code-block:: c - #include #include + #include + #include "platform_x_pindefs.h" static int foo_pin_config_get(struct pinctrl_dev *pctldev, - unsigned offset, - unsigned long *config) + unsigned int offset, + unsigned long *config) { struct my_conftype conf; - ... Find setting for pin @ offset ... + /* ... Find setting for pin @ offset ... */ *config = (unsigned long) conf; } static int foo_pin_config_set(struct pinctrl_dev *pctldev, - unsigned offset, - unsigned long config) + unsigned int offset, + unsigned long config) { struct my_conftype *conf = (struct my_conftype *) config; switch (conf) { case PLATFORM_X_PULL_UP: ... - } + break; } } - static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, - unsigned selector, - unsigned long *config) + static int foo_pin_config_group_get(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long *config) { ... } - static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, - unsigned selector, - unsigned long config) + static int foo_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long config) { ... } @@ -281,8 +272,8 @@ The GPIO drivers may want to perform operations of various types on the same physical pins that are also registered as pin controller pins. First and foremost, the two subsystems can be used as completely orthogonal, -see the section named "pin control requests from drivers" and -"drivers needing both pin control and GPIOs" below for details. But in some +see the section named `Pin control requests from drivers`_ and +`Drivers needing both pin control and GPIOs`_ below for details. But in some situations a cross-subsystem mapping between pins and GPIOs is needed. Since the pin controller subsystem has its pinspace local to the pin controller @@ -291,7 +282,13 @@ controller handles control of a certain GPIO pin. Since a single pin controller may be muxing several GPIO ranges (typically SoCs that have one set of pins, but internally several GPIO silicon blocks, each modelled as a struct gpio_chip) any number of GPIO ranges can be added to a pin controller instance -like this:: +like this: + +.. code-block:: c + + #include + + #include struct gpio_chip chip_a; struct gpio_chip chip_b; @@ -302,7 +299,7 @@ like this:: .base = 32, .pin_base = 32, .npins = 16, - .gc = &chip_a; + .gc = &chip_a, }; static struct pinctrl_gpio_range gpio_range_b = { @@ -314,11 +311,13 @@ like this:: .gc = &chip_b; }; + int __init foo_init(void) { struct pinctrl_dev *pctl; ... pinctrl_add_gpio_range(pctl, &gpio_range_a); pinctrl_add_gpio_range(pctl, &gpio_range_b); + ... } So this complex system has one pin controller handling two different @@ -343,9 +342,11 @@ chip b: The above examples assume the mapping between the GPIOs and pins is linear. If the mapping is sparse or haphazard, an array of arbitrary pin -numbers can be encoded in the range like this:: +numbers can be encoded in the range like this: - static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 }; +.. code-block:: c + + static const unsigned int range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 }; static struct pinctrl_gpio_range gpio_range = { .name = "chip", @@ -353,16 +354,17 @@ numbers can be encoded in the range like this:: .base = 32, .pins = &range_pins, .npins = ARRAY_SIZE(range_pins), - .gc = &chip; + .gc = &chip, }; In this case the pin_base property will be ignored. If the name of a pin group is known, the pins and npins elements of the above structure can be initialised using the function pinctrl_get_group_pins(), e.g. for pin -group "foo":: +group "foo": + +.. code-block:: c - pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, - &gpio_range.npins); + pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins); When GPIO-specific functions in the pin control subsystem are called, these ranges will be used to look up the appropriate pin controller by inspecting @@ -378,7 +380,7 @@ will get a pin number into its handled number range. Further it is also passed the range ID value, so that the pin controller knows which range it should deal with. -Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see +Calling pinctrl_add_gpio_range() from pinctrl driver is DEPRECATED. Please see section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind pinctrl and gpio drivers. @@ -515,11 +517,13 @@ Definitions: In the example case we can define that this particular machine shall use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function fi2c0 group gi2c0, on the primary pin controller, we get mappings - like these:: + like these: + + .. code-block:: c { {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, - {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} + {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}, } Every map must be assigned a state name, pin controller, device and @@ -569,80 +573,51 @@ is possible to perform the requested mux setting, poke the hardware so that this happens. Pinmux drivers are required to supply a few callback functions, some are -optional. Usually the set_mux() function is implemented, writing values into +optional. Usually the .set_mux() function is implemented, writing values into some certain registers to activate a certain mux setting for a certain pin. -A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 +A simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5 into some register named MUX to select a certain function with a certain -group of pins would work something like this:: +group of pins would work something like this: + +.. code-block:: c #include #include - struct foo_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; - }; - - static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; - static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; - static const unsigned i2c0_pins[] = { 24, 25 }; - static const unsigned mmc0_1_pins[] = { 56, 57 }; - static const unsigned mmc0_2_pins[] = { 58, 59 }; - static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; - - static const struct foo_group foo_groups[] = { - { - .name = "spi0_0_grp", - .pins = spi0_0_pins, - .num_pins = ARRAY_SIZE(spi0_0_pins), - }, - { - .name = "spi0_1_grp", - .pins = spi0_1_pins, - .num_pins = ARRAY_SIZE(spi0_1_pins), - }, - { - .name = "i2c0_grp", - .pins = i2c0_pins, - .num_pins = ARRAY_SIZE(i2c0_pins), - }, - { - .name = "mmc0_1_grp", - .pins = mmc0_1_pins, - .num_pins = ARRAY_SIZE(mmc0_1_pins), - }, - { - .name = "mmc0_2_grp", - .pins = mmc0_2_pins, - .num_pins = ARRAY_SIZE(mmc0_2_pins), - }, - { - .name = "mmc0_3_grp", - .pins = mmc0_3_pins, - .num_pins = ARRAY_SIZE(mmc0_3_pins), - }, + static const unsigned int spi0_0_pins[] = { 0, 8, 16, 24 }; + static const unsigned int spi0_1_pins[] = { 38, 46, 54, 62 }; + static const unsigned int i2c0_pins[] = { 24, 25 }; + static const unsigned int mmc0_1_pins[] = { 56, 57 }; + static const unsigned int mmc0_2_pins[] = { 58, 59 }; + static const unsigned int mmc0_3_pins[] = { 60, 61, 62, 63 }; + + static const struct pingroup foo_groups[] = { + PINCTRL_PINGROUP("spi0_0_grp", spi0_0_pins, ARRAY_SIZE(spi0_0_pins)), + PINCTRL_PINGROUP("spi0_1_grp", spi0_1_pins, ARRAY_SIZE(spi0_1_pins)), + PINCTRL_PINGROUP("i2c0_grp", i2c0_pins, ARRAY_SIZE(i2c0_pins)), + PINCTRL_PINGROUP("mmc0_1_grp", mmc0_1_pins, ARRAY_SIZE(mmc0_1_pins)), + PINCTRL_PINGROUP("mmc0_2_grp", mmc0_2_pins, ARRAY_SIZE(mmc0_2_pins)), + PINCTRL_PINGROUP("mmc0_3_grp", mmc0_3_pins, ARRAY_SIZE(mmc0_3_pins)), }; - static int foo_get_groups_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(foo_groups); } static const char *foo_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned int selector) { return foo_groups[selector].name; } - static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned ** pins, - unsigned * num_pins) + static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, + unsigned int *npins) { - *pins = (unsigned *) foo_groups[selector].pins; - *num_pins = foo_groups[selector].num_pins; + *pins = foo_groups[selector].pins; + *npins = foo_groups[selector].npins; return 0; } @@ -652,33 +627,14 @@ group of pins would work something like this:: .get_group_pins = foo_get_group_pins, }; - struct foo_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; - }; - static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; static const char * const i2c0_groups[] = { "i2c0_grp" }; - static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", - "mmc0_3_grp" }; + static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" }; - static const struct foo_pmx_func foo_functions[] = { - { - .name = "spi0", - .groups = spi0_groups, - .num_groups = ARRAY_SIZE(spi0_groups), - }, - { - .name = "i2c0", - .groups = i2c0_groups, - .num_groups = ARRAY_SIZE(i2c0_groups), - }, - { - .name = "mmc0", - .groups = mmc0_groups, - .num_groups = ARRAY_SIZE(mmc0_groups), - }, + static const struct pinfunction foo_functions[] = { + PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)), + PINCTRL_PINFUNCTION("i2c0", i2c0_groups, ARRAY_SIZE(i2c0_groups)), + PINCTRL_PINFUNCTION("mmc0", mmc0_groups, ARRAY_SIZE(mmc0_groups)), }; static int foo_get_functions_count(struct pinctrl_dev *pctldev) @@ -686,26 +642,26 @@ group of pins would work something like this:: return ARRAY_SIZE(foo_functions); } - static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) + static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned int selector) { return foo_functions[selector].name; } - static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) + static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, + unsigned int * const ngroups) { *groups = foo_functions[selector].groups; - *num_groups = foo_functions[selector].num_groups; + *ngroups = foo_functions[selector].ngroups; return 0; } - static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) + static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) { - u8 regbit = (1 << selector + group); + u8 regbit = BIT(group); - writeb((readb(MUX)|regbit), MUX); + writeb((readb(MUX) | regbit), MUX); return 0; } @@ -724,16 +680,17 @@ group of pins would work something like this:: .pmxops = &foo_pmxops, }; -In the example activating muxing 0 and 1 at the same time setting bits -0 and 1, uses one pin in common so they would collide. +In the example activating muxing 0 and 2 at the same time setting bits +0 and 2, uses pin 24 in common so they would collide. All the same for +the muxes 1 and 5, which have pin 62 in common. The beauty of the pinmux subsystem is that since it keeps track of all pins and who is using them, it will already have denied an impossible request like that, so the driver does not need to worry about such things - when it gets a selector passed in, the pinmux subsystem makes sure no other device or GPIO assignment is already using the selected -pins. Thus bits 0 and 1 in the control register will never be set at the -same time. +pins. Thus bits 0 and 2, or 1 and 5 in the control register will never +be set at the same time. All the above functions are mandatory to implement for a pinmux driver. @@ -742,18 +699,18 @@ Pin control interaction with the GPIO subsystem =============================================== Note that the following implies that the use case is to use a certain pin -from the Linux kernel using the API in with gpio_request() +from the Linux kernel using the API in with gpiod_get() and similar functions. There are cases where you may be using something that your datasheet calls "GPIO mode", but actually is just an electrical configuration for a certain device. See the section below named -"GPIO mode pitfalls" for more details on this scenario. +`GPIO mode pitfalls`_ for more details on this scenario. The public pinmux API contains two functions named pinctrl_gpio_request() and pinctrl_gpio_free(). These two functions shall *ONLY* be called from -gpiolib-based drivers as part of their gpio_request() and -gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output] -shall only be called from within respective gpio_direction_[input|output] -gpiolib implementation. +gpiolib-based drivers as part of their .request() and .free() semantics. +Likewise the pinctrl_gpio_direction_input()/pinctrl_gpio_direction_output() +shall only be called from within respective .direction_input() / +.direction_output() gpiolib implementation. NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have @@ -794,7 +751,7 @@ is taken to mean different things than what the kernel does, the developer may be confused by a datasheet talking about a pin being possible to set into "GPIO mode". It appears that what hardware engineers mean with "GPIO mode" is not necessarily the use case that is implied in the kernel -interface : a pin that you grab from kernel code and then +interface : a pin that you grab from kernel code and then either listen for input or drive high/low to assert/deassert some external line. @@ -805,9 +762,10 @@ for a device. The GPIO portions of a pin and its relation to a certain pin controller configuration and muxing logic can be constructed in several ways. Here -are two examples:: +are two examples. + +Example **(A)**:: - (A) pin config logic regs | +- SPI @@ -836,9 +794,7 @@ simultaneous access to the same pin from GPIO and pin multiplexing consumers on hardware of this type. The pinctrl driver should set this flag accordingly. -:: - - (B) +Example **(B)**:: pin config logic regs @@ -899,13 +855,13 @@ If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start to think that you need to come up with something really complex, that the pin shall be used for UART TX and GPIO at the same time, that you will grab a pin control handle and set it to a certain state to enable UART TX to be -muxed in, then twist it over to GPIO mode and use gpio_direction_output() +muxed in, then twist it over to GPIO mode and use gpiod_direction_output() to drive it low during sleep, then mux it over to UART TX again when you -wake up and maybe even gpio_request/gpio_free as part of this cycle. This +wake up and maybe even gpiod_get()/gpiod_put() as part of this cycle. This all gets very complicated. The solution is to not think that what the datasheet calls "GPIO mode" -has to be handled by the interface. Instead view this as +has to be handled by the interface. Instead view this as a certain pin config setting. Look in e.g. and you find this in the documentation: @@ -915,7 +871,9 @@ and you find this in the documentation: So it is perfectly possible to push a pin into "GPIO mode" and drive the line low as part of the usual pin control map. So for example your UART -driver may look like this:: +driver may look like this: + +.. code-block:: c #include @@ -928,13 +886,13 @@ driver may look like this:: /* Normal mode */ retval = pinctrl_select_state(pinctrl, pins_default); + /* Sleep mode */ retval = pinctrl_select_state(pinctrl, pins_sleep); And your machine configuration may look like this: --------------------------------------------------- -:: +.. code-block:: c static unsigned long uart_default_mode[] = { PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0), @@ -946,16 +904,17 @@ And your machine configuration may look like this: static struct pinctrl_map pinmap[] __initdata = { PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", - "u0_group", "u0"), + "u0_group", "u0"), PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", - "UART_TX_PIN", uart_default_mode), + "UART_TX_PIN", uart_default_mode), PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", - "u0_group", "gpio-mode"), + "u0_group", "gpio-mode"), PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", - "UART_TX_PIN", uart_sleep_mode), + "UART_TX_PIN", uart_sleep_mode), }; - foo_init(void) { + foo_init(void) + { pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap)); } @@ -995,7 +954,9 @@ part of this. A pin controller configuration for a machine looks pretty much like a simple regulator configuration, so for the example array above we want to enable i2c -and spi on the second function mapping:: +and spi on the second function mapping: + +.. code-block:: c #include @@ -1030,13 +991,17 @@ must match a function provided by the pinmux driver handling this pin range. As you can see we may have several pin controllers on the system and thus we need to specify which one of them contains the functions we wish to map. -You register this pinmux mapping to the pinmux subsystem by simply:: +You register this pinmux mapping to the pinmux subsystem by simply: + +.. code-block:: c ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping)); Since the above construct is pretty common there is a helper macro to make it even more compact which assumes you want to use pinctrl-foo and position -0 for mapping, for example:: +0 for mapping, for example: + +.. code-block:: c static struct pinctrl_map mapping[] __initdata = { PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, @@ -1046,7 +1011,9 @@ it even more compact which assumes you want to use pinctrl-foo and position The mapping table may also contain pin configuration entries. It's common for each pin/group to have a number of configuration entries that affect it, so the table entries for configuration reference an array of config parameters -and values. An example using the convenience macros is shown below:: +and values. An example using the convenience macros is shown below: + +.. code-block:: c static unsigned long i2c_grp_configs[] = { FOO_PIN_DRIVEN, @@ -1074,7 +1041,9 @@ named states. When running on hardware that doesn't need any pin controller configuration, the mapping table must still contain those named states, in order to explicitly indicate that the states were provided and intended to be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining -a named state without causing any pin controller to be programmed:: +a named state without causing any pin controller to be programmed: + +.. code-block:: c static struct pinctrl_map mapping[] __initdata = { PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT), @@ -1085,7 +1054,9 @@ Complex mappings ================ As it is possible to map a function to different groups of pins an optional -.group can be specified like this:: +.group can be specified like this: + +.. code-block:: c ... { @@ -1107,13 +1078,15 @@ As it is possible to map a function to different groups of pins an optional ... This example mapping is used to switch between two positions for spi0 at -runtime, as described further below under the heading "Runtime pinmuxing". +runtime, as described further below under the heading `Runtime pinmuxing`_. Further it is possible for one named state to affect the muxing of several groups of pins, say for example in the mmc0 example above, where you can additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all -three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the -case), we define a mapping like this:: +three groups for a total of 2 + 2 + 4 = 8 pins (for an 8-bit MMC bus as is the +case), we define a mapping like this: + +.. code-block:: c ... { @@ -1167,13 +1140,17 @@ case), we define a mapping like this:: ... The result of grabbing this mapping from the device with something like -this (see next paragraph):: +this (see next paragraph): + +.. code-block:: c p = devm_pinctrl_get(dev); s = pinctrl_lookup_state(p, "8bit"); ret = pinctrl_select_state(p, s); -or more simply:: +or more simply: + +.. code-block:: c p = devm_pinctrl_get_select(dev, "8bit"); @@ -1211,7 +1188,9 @@ PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save current in sleep mode. A driver may request a certain control state to be activated, usually just the -default state like this:: +default state like this: + +.. code-block:: c #include @@ -1285,7 +1264,7 @@ The semantics of the pinctrl APIs are: Usually the pin control core handled the get/put pair and call out to the device drivers bookkeeping operations, like checking available functions and -the associated pins, whereas select_state pass on to the pin controller +the associated pins, whereas pinctrl_select_state() pass on to the pin controller driver which takes care of activating and/or deactivating the mux setting by quickly poking some registers. @@ -1305,18 +1284,20 @@ Drivers needing both pin control and GPIOs Again, it is discouraged to let drivers lookup and select pin control states themselves, but again sometimes this is unavoidable. -So say that your driver is fetching its resources like this:: +So say that your driver is fetching its resources like this: + +.. code-block:: c #include - #include + #include struct pinctrl *pinctrl; - int gpio; + struct gpio_desc *gpio; pinctrl = devm_pinctrl_get_select_default(&dev); - gpio = devm_gpio_request(&dev, 14, "foo"); + gpio = devm_gpiod_get(&dev, "foo"); -Here we first request a certain pin state and then request GPIO 14 to be +Here we first request a certain pin state and then request GPIO "foo" to be used. If you're using the subsystems orthogonally like this, you should nominally always get your pinctrl handle and select the desired pinctrl state BEFORE requesting the GPIO. This is a semantic convention to avoid @@ -1331,9 +1312,9 @@ probing, nevertheless orthogonal to the GPIO subsystem. But there are also situations where it makes sense for the GPIO subsystem to communicate directly with the pinctrl subsystem, using the latter as a back-end. This is when the GPIO driver may call out to the functions -described in the section "Pin control interaction with the GPIO subsystem" +described in the section `Pin control interaction with the GPIO subsystem`_ above. This only involves per-pin multiplexing, and will be completely -hidden behind the gpio_*() function namespace. In this case, the driver +hidden behind the gpiod_*() function namespace. In this case, the driver need not interact with the pin control subsystem at all. If a pin control driver and a GPIO driver is dealing with the same pins @@ -1349,11 +1330,13 @@ System pin control hogging Pin control map entries can be hogged by the core when the pin controller is registered. This means that the core will attempt to call pinctrl_get(), -lookup_state() and select_state() on it immediately after the pin control -device has been registered. +pinctrl_lookup_state() and pinctrl_select_state() on it immediately after +the pin control device has been registered. This occurs for mapping table entries where the client device name is equal -to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT:: +to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT: + +.. code-block:: c { .dev_name = "pinctrl-foo", @@ -1365,7 +1348,9 @@ to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT:: Since it may be common to request the core to hog a few always-applicable mux settings on the primary pin controller, there is a convenience macro for -this:: +this: + +.. code-block:: c PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func") @@ -1385,7 +1370,9 @@ function, but with different named in the mapping as described under This snippet first initializes a state object for both groups (in foo_probe()), then muxes the function in the pins defined by group A, and finally muxes it in -on the pins defined by group B:: +on the pins defined by group B: + +.. code-block:: c #include @@ -1413,14 +1400,14 @@ on the pins defined by group B:: /* Enable on position A */ ret = pinctrl_select_state(p, s1); if (ret < 0) - ... + ... ... /* Enable on position B */ ret = pinctrl_select_state(p, s2); if (ret < 0) - ... + ... ... } @@ -1432,6 +1419,7 @@ can be used by different functions at different times on a running system. Debugfs files ============= + These files are created in ``/sys/kernel/debug/pinctrl``: - ``pinctrl-devices``: prints each pin controller device along with columns to @@ -1440,7 +1428,7 @@ These files are created in ``/sys/kernel/debug/pinctrl``: - ``pinctrl-handles``: prints each configured pin controller handle and the corresponding pinmux maps -- ``pinctrl-maps``: print all pinctrl maps +- ``pinctrl-maps``: prints all pinctrl maps A sub-directory is created inside of ``/sys/kernel/debug/pinctrl`` for each pin controller device containing these files: @@ -1448,20 +1436,22 @@ controller device containing these files: - ``pins``: prints a line for each pin registered on the pin controller. The pinctrl driver may add additional information such as register contents. -- ``gpio-ranges``: print ranges that map gpio lines to pins on the controller +- ``gpio-ranges``: prints ranges that map gpio lines to pins on the controller -- ``pingroups``: print all pin groups registered on the pin controller +- ``pingroups``: prints all pin groups registered on the pin controller -- ``pinconf-pins``: print pin config settings for each pin +- ``pinconf-pins``: prints pin config settings for each pin -- ``pinconf-groups``: print pin config settings per pin group +- ``pinconf-groups``: prints pin config settings per pin group -- ``pinmux-functions``: print each pin function along with the pin groups that +- ``pinmux-functions``: prints each pin function along with the pin groups that map to the pin function -- ``pinmux-pins``: iterate through all pins and print mux owner, gpio owner +- ``pinmux-pins``: iterates through all pins and prints mux owner, gpio owner and if the pin is a hog -- ``pinmux-select``: write to this file to activate a pin function for a group:: +- ``pinmux-select``: write to this file to activate a pin function for a group: + + .. code-block:: sh echo "" > pinmux-select From 88f8ac47bddc1674b2840c733f1120a548037199 Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Mon, 16 Jan 2023 16:55:38 +0200 Subject: [PATCH 078/118] pinctrl: Proofreading and updating the documentation (part 2) Do the following: - update the "Definitions" style in two sections - don't use "I" for technical documentation - inline the remaining (variables, function names, file paths) Signed-off-by: Bagas Sanjaya Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- Documentation/driver-api/pin-control.rst | 114 +++++++++++------------ 1 file changed, 56 insertions(+), 58 deletions(-) diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index 22a82ee23a415..bf5a78783861f 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -17,14 +17,12 @@ This subsystem deals with: Top-level interface =================== -Definition of PIN CONTROLLER: +Definitions: -- A pin controller is a piece of hardware, usually a set of registers, that +- A PIN CONTROLLER is a piece of hardware, usually a set of registers, that can control PINs. It may be able to multiplex, bias, set load capacitance, set drive strength, etc. for individual pins or groups of pins. -Definition of PIN: - - PINS are equal to pads, fingers, balls or whatever packaging input or output line you want to control and these are denoted by unsigned integers in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so @@ -96,20 +94,20 @@ this in our driver: To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and selected drivers, you need to select them from your machine's Kconfig entry, since these are so tightly integrated with the machines they are used on. -See arch/arm/mach-ux500/Kconfig for an example. +See ``arch/arm/mach-ux500/Kconfig`` for an example. Pins usually have fancier names than this. You can find these in the datasheet for your chip. Notice that the core pinctrl.h file provides a fancy macro -called PINCTRL_PIN() to create the struct entries. As you can see I enumerated -the pins from 0 in the upper left corner to 63 in the lower right corner. +called ``PINCTRL_PIN()`` to create the struct entries. As you can see the pins are +enumerated from 0 in the upper left corner to 63 in the lower right corner. This enumeration was arbitrarily chosen, in practice you need to think through your numbering system so that it matches the layout of registers and such things in your driver, or the code may become complicated. You must also consider matching of offsets to the GPIO ranges that may be handled by the pin controller. -For a padring with 467 pads, as opposed to actual pins, I used an enumeration -like this, walking around the edge of the chip, which seems to be industry +For a padding with 467 pads, as opposed to actual pins, the enumeration will +be like this, walking around the edge of the chip, which seems to be industry standard too (all these pads had names, too):: @@ -133,7 +131,7 @@ on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins on { 24, 25 }. These two groups are presented to the pin control subsystem by implementing -some generic pinctrl_ops like this: +some generic ``pinctrl_ops`` like this: .. code-block:: c @@ -179,7 +177,7 @@ some generic pinctrl_ops like this: .pctlops = &foo_pctrl_ops, }; -The pin control subsystem will call the .get_groups_count() function to +The pin control subsystem will call the ``.get_groups_count()`` function to determine the total number of legal selectors, then it will call the other functions to retrieve the name and pins of the group. Maintaining the data structure of the groups is up to the driver, this is just a simple example - in practice you @@ -322,7 +320,7 @@ like this: So this complex system has one pin controller handling two different GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and -"chip b" have different .pin_base, which means a start pin number of the +"chip b" have different ``pin_base``, which means a start pin number of the GPIO range. The GPIO range of "chip a" starts from the GPIO base of 32 and actual @@ -330,7 +328,7 @@ pin range also starts from 32. However "chip b" has different starting offset for the GPIO range and pin range. The GPIO range of "chip b" starts from GPIO number 48, while the pin range of "chip b" starts from 64. -We can convert a gpio number to actual pin number using this "pin_base". +We can convert a gpio number to actual pin number using this ``pin_base``. They are mapped in the global GPIO pin space at: chip a: @@ -357,9 +355,9 @@ numbers can be encoded in the range like this: .gc = &chip, }; -In this case the pin_base property will be ignored. If the name of a pin +In this case the ``pin_base`` property will be ignored. If the name of a pin group is known, the pins and npins elements of the above structure can be -initialised using the function pinctrl_get_group_pins(), e.g. for pin +initialised using the function ``pinctrl_get_group_pins()``, e.g. for pin group "foo": .. code-block:: c @@ -380,8 +378,8 @@ will get a pin number into its handled number range. Further it is also passed the range ID value, so that the pin controller knows which range it should deal with. -Calling pinctrl_add_gpio_range() from pinctrl driver is DEPRECATED. Please see -section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind +Calling ``pinctrl_add_gpio_range()`` from pinctrl driver is DEPRECATED. Please see +section 2.1 of ``Documentation/devicetree/bindings/gpio/gpio.txt`` on how to bind pinctrl and gpio drivers. @@ -468,10 +466,10 @@ in your machine configuration. It is inspired by the clk, GPIO and regulator subsystems, so devices will request their mux setting, but it's also possible to request a single pin for e.g. GPIO. -Definitions: +The conventions are: - FUNCTIONS can be switched in and out by a driver residing with the pin - control subsystem in the drivers/pinctrl/* directory of the kernel. The + control subsystem in the ``drivers/pinctrl`` directory of the kernel. The pin control driver knows the possible functions. In the example above you can identify three pinmux functions, one for spi, one for i2c and one for mmc. @@ -573,7 +571,7 @@ is possible to perform the requested mux setting, poke the hardware so that this happens. Pinmux drivers are required to supply a few callback functions, some are -optional. Usually the .set_mux() function is implemented, writing values into +optional. Usually the ``.set_mux()`` function is implemented, writing values into some certain registers to activate a certain mux setting for a certain pin. A simple driver for the above example will work by setting bits 0, 1, 2, 3, 4, or 5 @@ -699,18 +697,18 @@ Pin control interaction with the GPIO subsystem =============================================== Note that the following implies that the use case is to use a certain pin -from the Linux kernel using the API in with gpiod_get() +from the Linux kernel using the API in ```` with gpiod_get() and similar functions. There are cases where you may be using something that your datasheet calls "GPIO mode", but actually is just an electrical configuration for a certain device. See the section below named `GPIO mode pitfalls`_ for more details on this scenario. -The public pinmux API contains two functions named pinctrl_gpio_request() -and pinctrl_gpio_free(). These two functions shall *ONLY* be called from -gpiolib-based drivers as part of their .request() and .free() semantics. -Likewise the pinctrl_gpio_direction_input()/pinctrl_gpio_direction_output() -shall only be called from within respective .direction_input() / -.direction_output() gpiolib implementation. +The public pinmux API contains two functions named ``pinctrl_gpio_request()`` +and ``pinctrl_gpio_free()``. These two functions shall *ONLY* be called from +gpiolib-based drivers as part of their ``.request()`` and ``.free()`` semantics. +Likewise the ``pinctrl_gpio_direction_input()`` / ``pinctrl_gpio_direction_output()`` +shall only be called from within respective ``.direction_input()`` / +``.direction_output()`` gpiolib implementation. NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have @@ -724,8 +722,8 @@ In this case, the function array would become 64 entries for each GPIO setting and then the device functions. For this reason there are two functions a pin control driver can implement -to enable only GPIO on an individual pin: .gpio_request_enable() and -.gpio_disable_free(). +to enable only GPIO on an individual pin: ``.gpio_request_enable()`` and +``.gpio_disable_free()``. This function will pass in the affected GPIO range identified by the pin controller core, so you know which GPIO pins are being affected by the request @@ -733,12 +731,12 @@ operation. If your driver needs to have an indication from the framework of whether the GPIO pin shall be used for input or output you can implement the -.gpio_set_direction() function. As described this shall be called from the +``.gpio_set_direction()`` function. As described this shall be called from the gpiolib driver and the affected GPIO range, pin offset and desired direction will be passed along to this function. Alternatively to using these special functions, it is fully allowed to use -named functions for each GPIO pin, the pinctrl_gpio_request() will attempt to +named functions for each GPIO pin, the ``pinctrl_gpio_request()`` will attempt to obtain the function "gpioN" where "N" is the global GPIO pin number if no special GPIO-handler is registered. @@ -751,7 +749,7 @@ is taken to mean different things than what the kernel does, the developer may be confused by a datasheet talking about a pin being possible to set into "GPIO mode". It appears that what hardware engineers mean with "GPIO mode" is not necessarily the use case that is implied in the kernel -interface : a pin that you grab from kernel code and then +interface ````: a pin that you grab from kernel code and then either listen for input or drive high/low to assert/deassert some external line. @@ -857,12 +855,12 @@ pin shall be used for UART TX and GPIO at the same time, that you will grab a pin control handle and set it to a certain state to enable UART TX to be muxed in, then twist it over to GPIO mode and use gpiod_direction_output() to drive it low during sleep, then mux it over to UART TX again when you -wake up and maybe even gpiod_get()/gpiod_put() as part of this cycle. This +wake up and maybe even gpiod_get() / gpiod_put() as part of this cycle. This all gets very complicated. The solution is to not think that what the datasheet calls "GPIO mode" -has to be handled by the interface. Instead view this as -a certain pin config setting. Look in e.g. +has to be handled by the ```` interface. Instead view this as +a certain pin config setting. Look in e.g. ```` and you find this in the documentation: PIN_CONFIG_OUTPUT: @@ -1040,7 +1038,7 @@ Finally, some devices expect the mapping table to contain certain specific named states. When running on hardware that doesn't need any pin controller configuration, the mapping table must still contain those named states, in order to explicitly indicate that the states were provided and intended to -be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining +be empty. Table entry macro ``PIN_MAP_DUMMY_STATE()`` serves the purpose of defining a named state without causing any pin controller to be programmed: .. code-block:: c @@ -1165,7 +1163,7 @@ Pin control requests from drivers ================================= When a device driver is about to probe the device core will automatically -attempt to issue pinctrl_get_select_default() on these devices. +attempt to issue ``pinctrl_get_select_default()`` on these devices. This way driver writers do not need to add any of the boilerplate code of the type found below. However when doing fine-grained state selection and not using the "default" state, you may have to do some device driver @@ -1183,8 +1181,8 @@ some cases where a driver needs to e.g. switch between different mux mappings at runtime this is not possible. A typical case is if a driver needs to switch bias of pins from normal -operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to -PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save +operation and going to sleep, moving from the ``PINCTRL_STATE_DEFAULT`` to +``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save current in sleep mode. A driver may request a certain control state to be activated, usually just the @@ -1230,49 +1228,49 @@ arrangement on your bus. The semantics of the pinctrl APIs are: -- pinctrl_get() is called in process context to obtain a handle to all pinctrl +- ``pinctrl_get()`` is called in process context to obtain a handle to all pinctrl information for a given client device. It will allocate a struct from the kernel memory to hold the pinmux state. All mapping table parsing or similar slow operations take place within this API. -- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put() +- ``devm_pinctrl_get()`` is a variant of pinctrl_get() that causes ``pinctrl_put()`` to be called automatically on the retrieved pointer when the associated device is removed. It is recommended to use this function over plain - pinctrl_get(). + ``pinctrl_get()``. -- pinctrl_lookup_state() is called in process context to obtain a handle to a +- ``pinctrl_lookup_state()`` is called in process context to obtain a handle to a specific state for a client device. This operation may be slow, too. -- pinctrl_select_state() programs pin controller hardware according to the +- ``pinctrl_select_state()`` programs pin controller hardware according to the definition of the state as given by the mapping table. In theory, this is a fast-path operation, since it only involved blasting some register settings into hardware. However, note that some pin controllers may have their registers on a slow/IRQ-based bus, so client devices should not assume they - can call pinctrl_select_state() from non-blocking contexts. + can call ``pinctrl_select_state()`` from non-blocking contexts. -- pinctrl_put() frees all information associated with a pinctrl handle. +- ``pinctrl_put()`` frees all information associated with a pinctrl handle. -- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to - explicitly destroy a pinctrl object returned by devm_pinctrl_get(). +- ``devm_pinctrl_put()`` is a variant of ``pinctrl_put()`` that may be used to + explicitly destroy a pinctrl object returned by ``devm_pinctrl_get()``. However, use of this function will be rare, due to the automatic cleanup that will occur even without calling it. - pinctrl_get() must be paired with a plain pinctrl_put(). - pinctrl_get() may not be paired with devm_pinctrl_put(). - devm_pinctrl_get() can optionally be paired with devm_pinctrl_put(). - devm_pinctrl_get() may not be paired with plain pinctrl_put(). + ``pinctrl_get()`` must be paired with a plain ``pinctrl_put()``. + ``pinctrl_get()`` may not be paired with ``devm_pinctrl_put()``. + ``devm_pinctrl_get()`` can optionally be paired with ``devm_pinctrl_put()``. + ``devm_pinctrl_get()`` may not be paired with plain ``pinctrl_put()``. Usually the pin control core handled the get/put pair and call out to the device drivers bookkeeping operations, like checking available functions and -the associated pins, whereas pinctrl_select_state() pass on to the pin controller +the associated pins, whereas ``pinctrl_select_state()`` pass on to the pin controller driver which takes care of activating and/or deactivating the mux setting by quickly poking some registers. -The pins are allocated for your device when you issue the devm_pinctrl_get() +The pins are allocated for your device when you issue the ``devm_pinctrl_get()`` call, after this you should be able to see this in the debugfs listing of all pins. -NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the +NOTE: the pinctrl system will return ``-EPROBE_DEFER`` if it cannot find the requested pinctrl handles, for example if the pinctrl driver has not yet registered. Thus make sure that the error path in your driver gracefully cleans up and is ready to retry the probing later in the startup process. @@ -1329,12 +1327,12 @@ System pin control hogging ========================== Pin control map entries can be hogged by the core when the pin controller -is registered. This means that the core will attempt to call pinctrl_get(), -pinctrl_lookup_state() and pinctrl_select_state() on it immediately after +is registered. This means that the core will attempt to call ``pinctrl_get()``, +``pinctrl_lookup_state()`` and ``pinctrl_select_state()`` on it immediately after the pin control device has been registered. This occurs for mapping table entries where the client device name is equal -to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT: +to the pin controller device name, and the state name is ``PINCTRL_STATE_DEFAULT``: .. code-block:: c From 5b8c304c94d79f44aea8ee273ce70ca380804156 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 20 Jan 2023 10:51:03 -0600 Subject: [PATCH 079/118] dt-bindings: pinctrl: qcom,pmic-mpp: Rename "mpp" child node names to "-pins$" Just 'mpp' is a bit ambiguous for a pattern as it allows any prefix or suffix. Change the node name pattern to "-pins$" to align with other Qualcomm pinctrl bindings. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230120165103.1278852-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 72cce38bc1ce6..9412b9362328d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -74,7 +74,7 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-pmic-mpp-state" - patternProperties: - "mpp": + '-pins$': $ref: "#/$defs/qcom-pmic-mpp-state" additionalProperties: false @@ -179,7 +179,7 @@ examples: }; default-state { - gpio-mpp { + gpio-pins { pins = "mpp1", "mpp2", "mpp3", "mpp4"; function = "digital"; input-enable; From c40aa80dd4569848ac89454321fa035a6ca26976 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 13 Jan 2023 23:53:49 +0200 Subject: [PATCH 080/118] gpiolib: Check "gpio-ranges" before calling ->add_pin_ranges() The ->add_pin_ranges() is supposed to be called for the backward compatiblity on Device Tree platforms or non-DT ones. Ensure that by checking presense of the "gpio-ranges" property. This allows to clean up a few existing drivers to avoid duplication of the check. Signed-off-by: Andy Shevchenko Tested-by: Stefan Wahren Tested-by: Florian Fainelli Reviewed-by: Florian Fainelli Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20230113215352.44272-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/gpio/gpiolib.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 5a66d9616d7cc..8a8551af80636 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -531,6 +531,14 @@ static void gpiochip_free_valid_mask(struct gpio_chip *gc) static int gpiochip_add_pin_ranges(struct gpio_chip *gc) { + /* + * Device Tree platforms are supposed to use "gpio-ranges" + * property. This check ensures that the ->add_pin_ranges() + * won't be called for them. + */ + if (device_property_present(&gc->gpiodev->dev, "gpio-ranges")) + return 0; + if (gc->add_pin_ranges) return gc->add_pin_ranges(gc); From 2d578dd27871372f7159dd3206149ec616700d87 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 13 Jan 2023 23:53:50 +0200 Subject: [PATCH 081/118] pinctrl: bcm2835: Remove of_node_put() in bcm2835_of_gpio_ranges_fallback() Remove wrong of_node_put() in bcm2835_of_gpio_ranges_fallback(), there is no counterpart of_node_get() for it. Fixes: d2b67744fd99 ("pinctrl: bcm2835: implement hook for missing gpio-ranges") Signed-off-by: Andy Shevchenko Reviewed-by: Stefan Wahren Tested-by: Stefan Wahren Tested-by: Florian Fainelli Reviewed-by: Florian Fainelli Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20230113215352.44272-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 7857e612a1008..c7cdccdb4332a 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -363,8 +363,6 @@ static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc, { struct pinctrl_dev *pctldev = of_pinctrl_get(np); - of_node_put(np); - if (!pctldev) return 0; From bc96299707d925286d67212704dca45d73031c53 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 13 Jan 2023 23:53:51 +0200 Subject: [PATCH 082/118] pinctrl: bcm2835: Switch to use ->add_pin_ranges() Yeah, while the ->add_pin_ranges() shouldn't be used by DT drivers, this one requires it to support quite old firmware descriptions that do not have gpio-ranges property. The change allows to clean up GPIO library from OF specifics. There is no functional change intended. Signed-off-by: Andy Shevchenko Tested-by: Stefan Wahren Tested-by: Florian Fainelli Reviewed-by: Florian Fainelli Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20230113215352.44272-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index c7cdccdb4332a..8e2551a08c372 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -358,9 +358,9 @@ static int bcm2835_gpio_direction_output(struct gpio_chip *chip, return 0; } -static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc, - struct device_node *np) +static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc) { + struct device_node *np = dev_of_node(gc->parent); struct pinctrl_dev *pctldev = of_pinctrl_get(np); if (!pctldev) @@ -386,7 +386,7 @@ static const struct gpio_chip bcm2835_gpio_chip = { .base = -1, .ngpio = BCM2835_NUM_GPIOS, .can_sleep = false, - .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback, + .add_pin_ranges = bcm2835_add_pin_ranges_fallback, }; static const struct gpio_chip bcm2711_gpio_chip = { @@ -403,7 +403,7 @@ static const struct gpio_chip bcm2711_gpio_chip = { .base = -1, .ngpio = BCM2711_NUM_GPIOS, .can_sleep = false, - .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback, + .add_pin_ranges = bcm2835_add_pin_ranges_fallback, }; static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, From b8f9301c91bff54570181db9dffa9b5716c3c75d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 13 Jan 2023 23:53:52 +0200 Subject: [PATCH 083/118] Revert "gpiolib: of: Introduce hook for missing gpio-ranges" This reverts commit 3550bba25d5587a701e6edf20e20984d2ee72c78. No users for this one, revert it for good. The ->add_pin_ranges() can be used instead. Signed-off-by: Andy Shevchenko Tested-by: Stefan Wahren Tested-by: Florian Fainelli Reviewed-by: Florian Fainelli Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20230113215352.44272-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/gpio/gpiolib-of.c | 5 ----- include/linux/gpio/driver.h | 12 ------------ 2 files changed, 17 deletions(-) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 4fff7258ee41a..1ffac6f9e092e 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -981,11 +981,6 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!np) return 0; - if (!of_property_read_bool(np, "gpio-ranges") && - chip->of_gpio_ranges_fallback) { - return chip->of_gpio_ranges_fallback(chip, np); - } - group_names = of_find_property(np, group_names_propname, NULL); for (;; index++) { diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 44783fc161254..9adbdb1657db8 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -525,18 +525,6 @@ struct gpio_chip { */ int (*of_xlate)(struct gpio_chip *gc, const struct of_phandle_args *gpiospec, u32 *flags); - - /** - * @of_gpio_ranges_fallback: - * - * Optional hook for the case that no gpio-ranges property is defined - * within the device tree node "np" (usually DT before introduction - * of gpio-ranges). So this callback is helpful to provide the - * necessary backward compatibility for the pin ranges. - */ - int (*of_gpio_ranges_fallback)(struct gpio_chip *gc, - struct device_node *np); - #endif /* CONFIG_OF_GPIO */ }; From 9bd73ce087354628983bc4392ba6894d6b6c15a7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Sat, 14 Jan 2023 00:07:03 +0200 Subject: [PATCH 084/118] pinctrl: qcom: Unify accessing to device fwnode The device fwnode can be get via dev_fwnode() getter. Use it where it makes sense. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230113220703.45686-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 2 +- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 +- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 2 +- drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 2 +- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 47e9a8b0d4744..5142c363480a0 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1350,7 +1350,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) girq = &chip->irq; gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip); girq->parent_handler = msm_gpio_irq_handler; - girq->fwnode = pctrl->dev->fwnode; + girq->fwnode = dev_fwnode(pctrl->dev); girq->num_parents = 1; girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), GFP_KERNEL); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 66d6d7ffbd432..ea3485344f069 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1146,7 +1146,7 @@ static int pmic_gpio_probe(struct platform_device *pdev) gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip); girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->fwnode = dev_fwnode(state->dev); girq->parent_domain = parent_domain; girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec; diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 063177b79927f..644fb4a0e72ac 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -927,7 +927,7 @@ static int pmic_mpp_probe(struct platform_device *pdev) girq->chip = &state->irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->fwnode = dev_fwnode(state->dev); girq->parent_domain = parent_domain; girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq; girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 99314925bb133..e973001e5c888 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -791,7 +791,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) girq->chip = &pm8xxx_irq_chip; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); + girq->fwnode = dev_fwnode(pctrl->dev); girq->parent_domain = parent_domain; girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index a46650db678a8..86f66cb8bf30a 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -881,7 +881,7 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) girq->chip = &pctrl->irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; - girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); + girq->fwnode = dev_fwnode(pctrl->dev); girq->parent_domain = parent_domain; if (of_device_is_compatible(pdev->dev.of_node, "qcom,pm8821-mpp")) girq->child_to_parent_hwirq = pm8821_mpp_child_to_parent_hwirq; From a298c70a10c604a6b3df5a0aa56597b705ba0f6b Mon Sep 17 00:00:00 2001 From: Guodong Liu Date: Wed, 18 Jan 2023 14:20:35 +0800 Subject: [PATCH 085/118] pinctrl: mediatek: Initialize variable pullen and pullup to zero Coverity spotted that pullen and pullup is not initialized to zero in mtk_pctrl_show_one_pin. The uninitialized variable pullen is used in assignment statement "rsel = pullen;" in mtk_pctrl_show_one_pin, and Uninitialized variable pullup is used when calling scnprintf. Fix this coverity by initializing pullen and pullup as zero. Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.") Signed-off-by: Guodong Liu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230118062036.26258-2-Guodong.Liu@mediatek.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 17eead44b6757..bc0bf5aedc549 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -640,7 +640,7 @@ static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, unsigned int gpio, char *buf, unsigned int buf_len) { - int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1, rsel = -1; + int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1; const struct mtk_pin_desc *desc; u32 try_all_type = 0; From 2e34f82ba214134ecf590fbe0cdbd87401645a8a Mon Sep 17 00:00:00 2001 From: Guodong Liu Date: Wed, 18 Jan 2023 14:20:36 +0800 Subject: [PATCH 086/118] pinctrl: mediatek: Initialize variable *buf to zero Coverity spotted that *buf is not initialized to zero in mtk_pctrl_dbg_show. Using uninitialized variable *buf as argument to %s when calling seq_printf. Fix this coverity by initializing *buf as zero. Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.") Signed-off-by: Guodong Liu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230118062036.26258-3-Guodong.Liu@mediatek.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index bc0bf5aedc549..33d6c3fb79080 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -717,7 +717,7 @@ static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int gpio) { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); - char buf[PIN_DBG_BUF_SZ]; + char buf[PIN_DBG_BUF_SZ] = { 0 }; (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ); From b2ea28b885a44a5bedc73fc2ba7adbe648eb18e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= Date: Wed, 25 Jan 2023 15:34:58 +0100 Subject: [PATCH 087/118] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230125143503.1015424-5-bero@baylibre.com Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 0000000000000..4b96884a1afc7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkränzer + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + pio-pins { + pins { + pinmux = , ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + }; + }; From 34cf9a859f14dab836eaf984bc9a778afb409b6f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Nov 2022 14:18:36 +0100 Subject: [PATCH 088/118] pinctrl: renesas: r8a779g0: Fix alignment in GPSR[678]_* macros The alignment of the second column in the definitions of the GPSR[678]_* macros does not match the alignment used in other definitions. Fix this to improve uniformity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9424a0e7f6d66a94d333df9fdc5cdf3b7defb8f5.1669036423.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a779g0.c | 112 ++++++++++++------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 5dd1c2c7708a8..bf7fcce2d9c6b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -206,66 +206,66 @@ #define GPSR5_0 FM(AVB2_AVTP_PPS) /* GPSR 6 */ -#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) -#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12) -#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8) -#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4) -#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0) -#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28) -#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24) -#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20) -#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16) -#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12) -#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8) -#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4) -#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0) -#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28) -#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24) -#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20) -#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16) -#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12) -#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8) -#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4) -#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0) +#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) +#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12) +#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8) +#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4) +#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0) +#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28) +#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24) +#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20) +#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16) +#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12) +#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8) +#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4) +#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0) +#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28) +#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24) +#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20) +#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16) +#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12) +#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8) +#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4) +#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0) /* GPSR7 */ -#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16) -#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12) -#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8) -#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4) -#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0) -#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28) -#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24) -#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20) -#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16) -#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12) -#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8) -#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4) -#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0) -#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28) -#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24) -#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20) -#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16) -#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12) -#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8) -#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) -#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) +#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16) +#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12) +#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8) +#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4) +#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0) +#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28) +#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24) +#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20) +#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16) +#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12) +#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8) +#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4) +#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0) +#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28) +#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24) +#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20) +#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16) +#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12) +#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8) +#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) +#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) /* GPSR8 */ -#define GPSR8_13 F_(GP8_13, IP1SR8_23_20) -#define GPSR8_12 F_(GP8_12, IP1SR8_19_16) -#define GPSR8_11 F_(SDA5, IP1SR8_15_12) -#define GPSR8_10 F_(SCL5, IP1SR8_11_8) -#define GPSR8_9 F_(SDA4, IP1SR8_7_4) -#define GPSR8_8 F_(SCL4, IP1SR8_3_0) -#define GPSR8_7 F_(SDA3, IP0SR8_31_28) -#define GPSR8_6 F_(SCL3, IP0SR8_27_24) -#define GPSR8_5 F_(SDA2, IP0SR8_23_20) -#define GPSR8_4 F_(SCL2, IP0SR8_19_16) -#define GPSR8_3 F_(SDA1, IP0SR8_15_12) -#define GPSR8_2 F_(SCL1, IP0SR8_11_8) -#define GPSR8_1 F_(SDA0, IP0SR8_7_4) -#define GPSR8_0 F_(SCL0, IP0SR8_3_0) +#define GPSR8_13 F_(GP8_13, IP1SR8_23_20) +#define GPSR8_12 F_(GP8_12, IP1SR8_19_16) +#define GPSR8_11 F_(SDA5, IP1SR8_15_12) +#define GPSR8_10 F_(SCL5, IP1SR8_11_8) +#define GPSR8_9 F_(SDA4, IP1SR8_7_4) +#define GPSR8_8 F_(SCL4, IP1SR8_3_0) +#define GPSR8_7 F_(SDA3, IP0SR8_31_28) +#define GPSR8_6 F_(SCL3, IP0SR8_27_24) +#define GPSR8_5 F_(SDA2, IP0SR8_23_20) +#define GPSR8_4 F_(SCL2, IP0SR8_19_16) +#define GPSR8_3 F_(SDA1, IP0SR8_15_12) +#define GPSR8_2 F_(SCL1, IP0SR8_11_8) +#define GPSR8_1 F_(SDA0, IP0SR8_7_4) +#define GPSR8_0 F_(SCL0, IP0SR8_3_0) /* SR0 */ /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ From 00dfe29887761405ccd23cc0aa07cb86623bb2b7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 2 Jan 2023 22:18:11 +0000 Subject: [PATCH 089/118] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also the pin configs are completely different. This patch makes sure we use the appropriate pin configs for each SoC (which is passed as part of the OF data) while configuring the GPIO pin as interrupts instead of using rzg2l_gpio_configs[] for all the SoCs. Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230102221815.273719-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 5aa3836dbc226..6f762097557af 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -130,6 +130,7 @@ struct rzg2l_dedicated_configs { struct rzg2l_pinctrl_data { const char * const *port_pins; const u32 *port_pin_configs; + unsigned int n_ports; struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; @@ -1124,7 +1125,7 @@ static struct { } }; -static int rzg2l_gpio_get_gpioint(unsigned int virq) +static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) { unsigned int gpioint; unsigned int i; @@ -1133,13 +1134,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq) port = virq / 8; bit = virq % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); + gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); return gpioint; } @@ -1239,7 +1240,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); if (gpioint < 0) return gpioint; @@ -1313,8 +1314,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, port = offset / 8; bit = offset % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= pctrl->data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) clear_bit(offset, valid_mask); } } @@ -1519,6 +1520,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), @@ -1527,6 +1529,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = rzg2l_gpio_configs, + .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + From 2d4a628cade2fe9cf7aa5629cffe768afe0e7ae1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 2 Jan 2023 22:18:12 +0000 Subject: [PATCH 090/118] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each supported SoC. While at it, for readability set n_port_pins based on the GPIO pin configs and not on GPIO names for r9a07g044_data as done for r9a07g043_data. Suggested-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230102221815.273719-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 6f762097557af..04b31f0c6b34a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1468,6 +1468,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) struct rzg2l_pinctrl *pctrl; int ret; + BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + + BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1531,7 +1537,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pin_configs = rzg2l_gpio_configs, .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), + .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), }; From 698485cd875be1109b2130e0ff6c927010a6b56b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 11 Jan 2023 09:21:38 +0100 Subject: [PATCH 091/118] pinctrl: renesas: r8a77950: Add VIN[45] pins, groups, and functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pins, groups, and functions for channels 4 and 5 of the Video Input Module (VIN) on the Renesas R-Car H3 ES1.x (R8A77950) SoC, based on the version for the R-Car H3 ES2.0+ (R8A77951) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/92c9b3b535d27ea7fcc0aa73d298783d710c214a.1673425207.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77950.c | 244 +++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index 4c543ec3a8639..cc66c6de045c5 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -3820,6 +3820,186 @@ static const unsigned int usb31_mux[] = { USB31_PWEN_MARK, USB31_OVC_MARK, }; +/* - VIN4 ------------------------------------------------------------------- */ +static const unsigned int vin4_data18_a_pins[] = { + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data18_a_mux[] = { + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data18_b_pins[] = { + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data18_b_mux[] = { + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), +}; +static const unsigned int vin4_sync_mux[] = { + VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, +}; +static const unsigned int vin4_field_pins[] = { + /* FIELD */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int vin4_field_mux[] = { + VI4_FIELD_MARK, +}; +static const unsigned int vin4_clkenb_pins[] = { + /* CLKENB */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int vin4_clkenb_mux[] = { + VI4_CLKENB_MARK, +}; +static const unsigned int vin4_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int vin4_clk_mux[] = { + VI4_CLK_MARK, +}; + +/* - VIN5 ------------------------------------------------------------------- */ +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, +}; +static const unsigned int vin5_sync_pins[] = { + /* HSYNC#, VSYNC# */ + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), +}; +static const unsigned int vin5_sync_mux[] = { + VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, +}; +static const unsigned int vin5_field_pins[] = { + RCAR_GP_PIN(1, 11), +}; +static const unsigned int vin5_field_mux[] = { + /* FIELD */ + VI5_FIELD_MARK, +}; +static const unsigned int vin5_clkenb_pins[] = { + RCAR_GP_PIN(1, 20), +}; +static const unsigned int vin5_clkenb_mux[] = { + /* CLKENB */ + VI5_CLKENB_MARK, +}; +static const unsigned int vin5_clk_pins[] = { + RCAR_GP_PIN(1, 21), +}; +static const unsigned int vin5_clk_mux[] = { + /* CLK */ + VI5_CLK_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -4141,6 +4321,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb31), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), + SH_PFC_PIN_GROUP(vin4_data18_a), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), + SH_PFC_PIN_GROUP(vin4_data18_b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), }; static const char * const audio_clk_groups[] = { @@ -4637,6 +4845,40 @@ static const char * const usb31_groups[] = { "usb31", }; +static const char * const vin4_groups[] = { + "vin4_data8_a", + "vin4_data10_a", + "vin4_data12_a", + "vin4_data16_a", + "vin4_data18_a", + "vin4_data20_a", + "vin4_data24_a", + "vin4_data8_b", + "vin4_data10_b", + "vin4_data12_b", + "vin4_data16_b", + "vin4_data18_b", + "vin4_data20_b", + "vin4_data24_b", + "vin4_g8", + "vin4_sync", + "vin4_field", + "vin4_clkenb", + "vin4_clk", +}; + +static const char * const vin5_groups[] = { + "vin5_data8", + "vin5_data10", + "vin5_data12", + "vin5_data16", + "vin5_high8", + "vin5_sync", + "vin5_field", + "vin5_clkenb", + "vin5_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), @@ -4696,6 +4938,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb2), SH_PFC_FUNCTION(usb30), SH_PFC_FUNCTION(usb31), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From a08cbeb1d10f2f091d4169a0ca0f4b719a53446a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 27 Jan 2023 13:28:26 +0100 Subject: [PATCH 092/118] pinctrl: at91: Tag suspend/resume __maybe_unused Tag the suspend/resume callbacks as __maybe_unused to silence complaints from the build robots. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index cf2423855a80a..2b91816ca286e 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1649,7 +1649,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) return 0; } -static int at91_gpio_suspend(struct device *dev) +static int __maybe_unused at91_gpio_suspend(struct device *dev) { struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); void __iomem *pio = at91_chip->regbase; @@ -1667,7 +1667,7 @@ static int at91_gpio_suspend(struct device *dev) return 0; } -static int at91_gpio_resume(struct device *dev) +static int __maybe_unused at91_gpio_resume(struct device *dev) { struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); void __iomem *pio = at91_chip->regbase; From 6c488fbb1de2bf3821307f4a81449d7b2f300b34 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 19 Jan 2023 20:05:36 -0600 Subject: [PATCH 093/118] dt-bindings: pinctrl: mediatek: Fix child node name patterns The child node name patterns in Mediatek pinctrl bindings don't match reality. I don't know where '-[0-9]+$' came from, but I don't see any nodes with a matching pattern. Also, patterns such as 'pins' or 'mux' are ambiguous because any prefix or suffix is allowed. If that's desired, it should be explicit. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230120020536.3229300-1-robh@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 12 ++++++------ .../bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 8 ++++---- .../bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 8 ++++---- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 1b44335b1e947..a55c8e4ff26ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -70,11 +70,11 @@ allOf: - $ref: "pinctrl.yaml#" patternProperties: - '-[0-9]+$': + 'pins$': type: object additionalProperties: false patternProperties: - 'pins': + '(^pins|pins?$)': type: object additionalProperties: false description: | @@ -158,7 +158,7 @@ examples: , ; - i2c0_pins_a: i2c0-0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = , ; @@ -166,7 +166,7 @@ examples: }; }; - i2c1_pins_a: i2c1-0 { + i2c1_pins_a: i2c1-pins { pins { pinmux = , ; @@ -174,7 +174,7 @@ examples: }; }; - i2c2_pins_a: i2c2-0 { + i2c2_pins_a: i2c2-pins { pins1 { pinmux = ; bias-pull-down; @@ -186,7 +186,7 @@ examples: }; }; - i2c3_pins_a: i2c3-0 { + i2c3_pins_a: i2c3-pins { pins1 { pinmux = , ; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index c9ea0cad489b7..ac93eb8f01a6e 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -61,11 +61,11 @@ then: - "#interrupt-cells" patternProperties: - '-[0-9]+$': + '-pins(-[a-z]+)?$': type: object additionalProperties: false patternProperties: - 'mux': + '^mux(-|$)': type: object additionalProperties: false description: | @@ -244,7 +244,7 @@ patternProperties: groups: enum: [wf0_2g, wf0_5g] - 'conf': + '^conf(-|$)': type: object additionalProperties: false description: | @@ -348,7 +348,7 @@ examples: gpio-controller; #gpio-cells = <2>; - pinctrl_eth_default: eth-0 { + pinctrl_eth_default: eth-pins { mux-mdio { groups = "mdc_mdio"; function = "eth"; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 0d2484056a0fe..c30cd0d010ddb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -67,11 +67,11 @@ required: - gpio-ranges patternProperties: - '-[0-9]+$': + '-pins(-[a-z]+)?$': type: object additionalProperties: false patternProperties: - 'pins': + '^pins': type: object additionalProperties: false description: | @@ -210,7 +210,7 @@ examples: interrupts = ; #interrupt-cells = <2>; - i2c0_pins_a: i2c-0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = , ; @@ -219,7 +219,7 @@ examples: }; }; - i2c1_pins_a: i2c-1 { + i2c1_pins_a: i2c1-pins { pins { pinmux = , ; From 91da7032d86a2aa2ae4b43d82008282bb672f9f2 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 12 Jul 2018 13:22:22 -0600 Subject: [PATCH 094/118] pinctrl: at91: fix deferred probing support AT91 pinctrl deferred probing support is broken if the GPIO devices haven't probed first and set gpio_banks to non-zero. The later condition that only some GPIO devices haven't probed can't actually happen as either all the GPIO devices have probed first or none of them have. Plus the pinctrl driver has already returned -EINVAL, so it's not on the deferred list to retry probing. Fix this by consolidating the checking that all GPIO devices are probed. Cc: Jean-Christophe Plagniol-Villard Cc: Linus Walleij Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Rob Herring Acked-by: Ludovic Desroches Tested-by: Nicolas Ferre # on sama5d3 xplained Acked-by: Nicolas Ferre Link: https://lore.kernel.org/r/20180712192222.32481-1-robh@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 36 ++++++++++++---------------------- 1 file changed, 13 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 2b91816ca286e..9a066355fd279 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1294,7 +1294,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, struct at91_pinctrl *info) { int ret = 0; - int i, j; + int i, j, ngpio_chips_enabled = 0; uint32_t *tmp; struct device_node *np = pdev->dev.of_node; struct device_node *child; @@ -1307,10 +1307,17 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; at91_pinctrl_child_count(info, np); - if (gpio_banks < 1) { - dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); - return -EINVAL; - } + /* + * We need all the GPIO drivers to probe FIRST, or we will not be able + * to obtain references to the struct gpio_chip * for them, and we + * need this to proceed. + */ + for (i = 0; i < MAX_GPIO_BANKS; i++) + if (gpio_chips[i]) + ngpio_chips_enabled++; + + if (ngpio_chips_enabled < info->nactive_banks) + return -EPROBE_DEFER; ret = at91_pinctrl_mux_mask(info, np); if (ret) @@ -1366,7 +1373,7 @@ static int at91_pinctrl_probe(struct platform_device *pdev) { struct at91_pinctrl *info; struct pinctrl_pin_desc *pdesc; - int ret, i, j, k, ngpio_chips_enabled = 0; + int ret, i, j, k; info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -1376,23 +1383,6 @@ static int at91_pinctrl_probe(struct platform_device *pdev) if (ret) return ret; - /* - * We need all the GPIO drivers to probe FIRST, or we will not be able - * to obtain references to the struct gpio_chip * for them, and we - * need this to proceed. - */ - for (i = 0; i < gpio_banks; i++) - if (gpio_chips[i]) - ngpio_chips_enabled++; - - if (ngpio_chips_enabled < info->nactive_banks) { - dev_warn(&pdev->dev, - "All GPIO chips are not registered yet (%d/%d)\n", - ngpio_chips_enabled, info->nactive_banks); - devm_kfree(&pdev->dev, info); - return -EPROBE_DEFER; - } - at91_pinctrl_desc.name = dev_name(&pdev->dev); at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; at91_pinctrl_desc.pins = pdesc = From 9a2aaee23c7965dc53210bca2a0af161f232368f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 1 Feb 2023 16:00:10 +0100 Subject: [PATCH 095/118] dt-bindings: pinctrl: describe sa8775p-tlmm Add DT bindings for the TLMM controller on sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230201150011.200613-2-brgl@bgdev.pl Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml new file mode 100644 index 0000000000000..70d9106ad83df --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA8775P TLMM block + +maintainers: + - Bartosz Golaszewski + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sa8775p-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 74 + + gpio-line-names: + maxItems: 148 + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sa8775p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sa8775p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sa8775p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, + edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, + edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, + emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, + emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, + jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3, + mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, + mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, + mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1, + pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, + qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, + qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0, + sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2, + tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8775p-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 148>; + + qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + }; +... From 4b6b185599273ecf980e3892006a7a29c5ad653b Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 1 Feb 2023 16:00:11 +0100 Subject: [PATCH 096/118] pinctrl: qcom: add the tlmm driver sa8775p platforms Add support for Lemans TLMM configuration and control via the pinctrl framework. Signed-off-by: Yadu MG Signed-off-by: Prasad Sodagudi [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230201150011.200613-3-brgl@bgdev.pl Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1537 ++++++++++++++++++++++++ 3 files changed, 1547 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2a517775a61ec..8d4f871e07cf8 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -258,6 +258,15 @@ config PINCTRL_QDU1000 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc QDU1000 and QRU1000 platforms. +config PINCTRL_SA8775P + tristate "Qualcomm Technologies Inc SA8775P pin controller driver" + depends on OF + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux and pinconf driver for the Qualcomm + TLMM block found on the Qualcomm SA8775P platforms. + config PINCTRL_SC7180 tristate "Qualcomm Technologies Inc SC7180 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 952f784d08881..6763aa8d319c6 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o +obj-$(CONFIG_PINCTRL_SA8775P) += pinctrl-sa8775p.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c new file mode 100644 index 0000000000000..2ae7cdca65d3e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -0,0 +1,1537 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define QUP_I3C(qup_mode, qup_offset) \ + { \ + .mode = qup_mode, \ + .offset = qup_offset, \ + } + +#define QUP_I3C_6_MODE_OFFSET 0xAF000 +#define QUP_I3C_7_MODE_OFFSET 0xB0000 +#define QUP_I3C_13_MODE_OFFSET 0xB1000 +#define QUP_I3C_14_MODE_OFFSET 0xB2000 + +static const struct pinctrl_pin_desc sa8775p_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "UFS_RESET"), + PINCTRL_PIN(150, "SDC1_RCLK"), + PINCTRL_PIN(151, "SDC1_CLK"), + PINCTRL_PIN(152, "SDC1_CMD"), + PINCTRL_PIN(153, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); + +static const unsigned int ufs_reset_pins[] = { 149 }; +static const unsigned int sdc1_rclk_pins[] = { 150 }; +static const unsigned int sdc1_clk_pins[] = { 151 }; +static const unsigned int sdc1_cmd_pins[] = { 152 }; +static const unsigned int sdc1_data_pins[] = { 153 }; + +enum sa8775p_functions { + msm_mux_gpio, + msm_mux_atest_char, + msm_mux_atest_usb2, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_hot, + msm_mux_edp1_lcd, + msm_mux_edp2_hot, + msm_mux_edp2_lcd, + msm_mux_edp3_hot, + msm_mux_edp3_lcd, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp_aux, + msm_mux_emac0_ptp_pps, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_mdc, + msm_mux_emac1_mdio, + msm_mux_emac1_ptp_aux, + msm_mux_emac1_ptp_pps, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_hs0_mi2s, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp0_vsync0, + msm_mux_mdp0_vsync1, + msm_mux_mdp0_vsync2, + msm_mux_mdp0_vsync3, + msm_mux_mdp0_vsync4, + msm_mux_mdp0_vsync5, + msm_mux_mdp0_vsync6, + msm_mux_mdp0_vsync7, + msm_mux_mdp0_vsync8, + msm_mux_mdp1_vsync0, + msm_mux_mdp1_vsync1, + msm_mux_mdp1_vsync2, + msm_mux_mdp1_vsync3, + msm_mux_mdp1_vsync4, + msm_mux_mdp1_vsync5, + msm_mux_mdp1_vsync6, + msm_mux_mdp1_vsync7, + msm_mux_mdp1_vsync8, + msm_mux_mdp_vsync, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mi2s_mclk0, + msm_mux_mi2s_mclk1, + msm_mux_pcie0_clkreq, + msm_mux_pcie1_clkreq, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup3_se0, + msm_mux_sail_top, + msm_mux_sailss_emac0, + msm_mux_sailss_ospi, + msm_mux_sgmii_phy, + msm_mux_tb_trig, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tgu_ch4, + msm_mux_tgu_ch5, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", +}; + +static const char * const atest_char_groups[] = { + "gpio27", "gpio58", "gpio59", "gpio89", "gpio90", +}; + +static const char * const atest_usb2_groups[] = { + "gpio58", "gpio59", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio105", +}; + +static const char * const audio_ref_groups[] = { + "gpio113", +}; + +static const char * const cam_mclk_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", +}; + +static const char * const cci_async_groups[] = { + "gpio50", "gpio66", "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char * const cci_i2c_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", +}; + +static const char * const cci_timer0_groups[] = { + "gpio68", +}; + +static const char * const cci_timer1_groups[] = { + "gpio69", +}; + +static const char * const cci_timer2_groups[] = { + "gpio70", +}; + +static const char * const cci_timer3_groups[] = { + "gpio71", +}; + +static const char * const cci_timer4_groups[] = { + "gpio52", +}; + +static const char * const cci_timer5_groups[] = { + "gpio53", +}; + +static const char * const cci_timer6_groups[] = { + "gpio54", +}; + +static const char * const cci_timer7_groups[] = { + "gpio55", +}; + +static const char * const cci_timer8_groups[] = { + "gpio56", +}; + +static const char * const cci_timer9_groups[] = { + "gpio57", +}; + +static const char * const cri_trng_groups[] = { + "gpio99", +}; + +static const char * const cri_trng0_groups[] = { + "gpio97", +}; + +static const char * const cri_trng1_groups[] = { + "gpio98", +}; + +static const char * const dbg_out_groups[] = { + "gpio144", +}; + +static const char * const ddr_bist_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio52", "gpio53", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio55", "gpio86", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio87", "gpio88", +}; + +static const char * const ddr_pxi4_groups[] = { + "gpio89", "gpio90", +}; + +static const char * const ddr_pxi5_groups[] = { + "gpio118", "gpio119", +}; + +static const char * const edp0_hot_groups[] = { + "gpio101", +}; + +static const char * const edp0_lcd_groups[] = { + "gpio44", +}; + +static const char * const edp1_hot_groups[] = { + "gpio102", +}; + +static const char * const edp1_lcd_groups[] = { + "gpio45", +}; + +static const char * const edp2_hot_groups[] = { + "gpio104", +}; + +static const char * const edp2_lcd_groups[] = { + "gpio48", +}; + +static const char * const edp3_hot_groups[] = { + "gpio103", +}; + +static const char * const edp3_lcd_groups[] = { + "gpio49", +}; + +static const char * const emac0_mcg0_groups[] = { + "gpio12", +}; + +static const char * const emac0_mcg1_groups[] = { + "gpio13", +}; + +static const char * const emac0_mcg2_groups[] = { + "gpio14", +}; + +static const char * const emac0_mcg3_groups[] = { + "gpio15", +}; + +static const char * const emac0_mdc_groups[] = { + "gpio8", +}; + +static const char * const emac0_mdio_groups[] = { + "gpio9", +}; + +static const char * const emac0_ptp_aux_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const emac0_ptp_pps_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const emac1_mcg0_groups[] = { + "gpio16", + +}; + +static const char * const emac1_mcg1_groups[] = { + "gpio17", +}; + +static const char * const emac1_mcg2_groups[] = { + "gpio18", +}; + +static const char * const emac1_mcg3_groups[] = { + "gpio19", +}; + +static const char * const emac1_mdc_groups[] = { + "gpio20", +}; + +static const char * const emac1_mdio_groups[] = { + "gpio21", +}; + +static const char * const emac1_ptp_aux_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const emac1_ptp_pps_groups[] = { + "gpio6", "gpio10", "gpio11", "gpio12", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio51", "gpio82", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio52", "gpio83", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio53", "gpio84", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio33", "gpio55", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio34", "gpio42", +}; + +static const char * const hs0_mi2s_groups[] = { + "gpio114", "gpio115", "gpio116", "gpio117", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio118", "gpio119", "gpio120", "gpio121", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio80", "gpio81", "gpio84", + "gpio85", +}; + +static const char * const jitter_bist_groups[] = { + "gpio86", +}; + +static const char * const mdp0_vsync0_groups[] = { + "gpio57", +}; + +static const char * const mdp0_vsync1_groups[] = { + "gpio58", +}; + +static const char * const mdp0_vsync2_groups[] = { + "gpio59", +}; + +static const char * const mdp0_vsync3_groups[] = { + "gpio80", +}; + +static const char * const mdp0_vsync4_groups[] = { + "gpio81", +}; + +static const char * const mdp0_vsync5_groups[] = { + "gpio91", +}; + +static const char * const mdp0_vsync6_groups[] = { + "gpio92", +}; + +static const char * const mdp0_vsync7_groups[] = { + "gpio93", +}; + +static const char * const mdp0_vsync8_groups[] = { + "gpio94", +}; + +static const char * const mdp1_vsync0_groups[] = { + "gpio40", +}; + +static const char * const mdp1_vsync1_groups[] = { + "gpio41", +}; + +static const char * const mdp1_vsync2_groups[] = { + "gpio42", +}; + +static const char * const mdp1_vsync3_groups[] = { + "gpio43", +}; + +static const char * const mdp1_vsync4_groups[] = { + "gpio46", +}; + +static const char * const mdp1_vsync5_groups[] = { + "gpio47", +}; + +static const char * const mdp1_vsync6_groups[] = { + "gpio51", +}; + +static const char * const mdp1_vsync7_groups[] = { + "gpio52", +}; + +static const char * const mdp1_vsync8_groups[] = { + "gpio50", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio82", "gpio83", "gpio84", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio108", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio109", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio106", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio107", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio112", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio113", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio110", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio111", +}; + +static const char * const mi2s_mclk0_groups[] = { + "gpio105", +}; + +static const char * const mi2s_mclk1_groups[] = { + "gpio117", +}; + +static const char * const pcie0_clkreq_groups[] = { + "gpio1", +}; + +static const char * const pcie1_clkreq_groups[] = { + "gpio3", +}; + +static const char * const phase_flag_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio56", + "gpio57", "gpio98", "gpio99", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char * const pll_bist_groups[] = { + "gpio114", +}; + +static const char * const pll_clk_groups[] = { + "gpio87", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio101", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio102", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio103", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio104", +}; + +static const char * const qdss_cti_groups[] = { + "gpio26", "gpio27", "gpio38", "gpio39", "gpio48", "gpio49", "gpio50", + "gpio51", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", +}; + +static const char * const qup0_se0_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qup0_se1_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char * const qup0_se2_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup0_se3_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char * const qup0_se4_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char * const qup0_se5_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup1_se0_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup1_se1_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char * const qup1_se2_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const qup1_se4_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char * const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char * const qup1_se6_groups[] = { + "gpio56", "gpio56", "gpio57", "gpio57", +}; + +static const char * const qup2_se0_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char * const qup2_se1_groups[] = { + "gpio84", "gpio85", "gpio99", "gpio100", +}; + +static const char * const qup2_se2_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", +}; + +static const char * const qup2_se3_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", +}; + +static const char * const qup2_se4_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", +}; + +static const char * const qup2_se5_groups[] = { + "gpio84", "gpio85", "gpio99", "gpio100", +}; + +static const char * const qup2_se6_groups[] = { + "gpio95", "gpio96", "gpio97", "gpio98", +}; + +static const char * const qup3_se0_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const sail_top_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; + +static const char * const sailss_emac0_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const sailss_ospi_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const sgmii_phy_groups[] = { + "gpio7", "gpio26", +}; + +static const char * const tb_trig_groups[] = { + "gpio17", "gpio17", +}; + +static const char * const tgu_ch0_groups[] = { + "gpio46", +}; + +static const char * const tgu_ch1_groups[] = { + "gpio47", +}; + +static const char * const tgu_ch2_groups[] = { + "gpio36", +}; + +static const char * const tgu_ch3_groups[] = { + "gpio37", +}; + +static const char * const tgu_ch4_groups[] = { + "gpio38", +}; + +static const char * const tgu_ch5_groups[] = { + "gpio39", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio104", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio103", +}; + +static const char * const tsense_pwm3_groups[] = { + "gpio102", +}; + +static const char * const tsense_pwm4_groups[] = { + "gpio101", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio10", "gpio11", "gpio12", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio111", +}; + +static const struct msm_function sa8775p_functions[] = { + FUNCTION(gpio), + FUNCTION(atest_char), + FUNCTION(atest_usb2), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_timer5), + FUNCTION(cci_timer6), + FUNCTION(cci_timer7), + FUNCTION(cci_timer8), + FUNCTION(cci_timer9), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(ddr_pxi4), + FUNCTION(ddr_pxi5), + FUNCTION(edp0_hot), + FUNCTION(edp0_lcd), + FUNCTION(edp1_hot), + FUNCTION(edp1_lcd), + FUNCTION(edp2_hot), + FUNCTION(edp2_lcd), + FUNCTION(edp3_hot), + FUNCTION(edp3_lcd), + FUNCTION(emac0_mcg0), + FUNCTION(emac0_mcg1), + FUNCTION(emac0_mcg2), + FUNCTION(emac0_mcg3), + FUNCTION(emac0_mdc), + FUNCTION(emac0_mdio), + FUNCTION(emac0_ptp_aux), + FUNCTION(emac0_ptp_pps), + FUNCTION(emac1_mcg0), + FUNCTION(emac1_mcg1), + FUNCTION(emac1_mcg2), + FUNCTION(emac1_mcg3), + FUNCTION(emac1_mdc), + FUNCTION(emac1_mdio), + FUNCTION(emac1_ptp_aux), + FUNCTION(emac1_ptp_pps), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_gp4), + FUNCTION(gcc_gp5), + FUNCTION(hs0_mi2s), + FUNCTION(hs1_mi2s), + FUNCTION(hs2_mi2s), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(mdp0_vsync0), + FUNCTION(mdp0_vsync1), + FUNCTION(mdp0_vsync2), + FUNCTION(mdp0_vsync3), + FUNCTION(mdp0_vsync4), + FUNCTION(mdp0_vsync5), + FUNCTION(mdp0_vsync6), + FUNCTION(mdp0_vsync7), + FUNCTION(mdp0_vsync8), + FUNCTION(mdp1_vsync0), + FUNCTION(mdp1_vsync1), + FUNCTION(mdp1_vsync2), + FUNCTION(mdp1_vsync3), + FUNCTION(mdp1_vsync4), + FUNCTION(mdp1_vsync5), + FUNCTION(mdp1_vsync6), + FUNCTION(mdp1_vsync7), + FUNCTION(mdp1_vsync8), + FUNCTION(mdp_vsync), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(mi2s_mclk0), + FUNCTION(mi2s_mclk1), + FUNCTION(pcie0_clkreq), + FUNCTION(pcie1_clkreq), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_clk), + FUNCTION(prng_rosc0), + FUNCTION(prng_rosc1), + FUNCTION(prng_rosc2), + FUNCTION(prng_rosc3), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qup0_se0), + FUNCTION(qup0_se1), + FUNCTION(qup0_se2), + FUNCTION(qup0_se3), + FUNCTION(qup0_se4), + FUNCTION(qup0_se5), + FUNCTION(qup1_se0), + FUNCTION(qup1_se1), + FUNCTION(qup1_se2), + FUNCTION(qup1_se3), + FUNCTION(qup1_se4), + FUNCTION(qup1_se5), + FUNCTION(qup1_se6), + FUNCTION(qup2_se0), + FUNCTION(qup2_se1), + FUNCTION(qup2_se2), + FUNCTION(qup2_se3), + FUNCTION(qup2_se4), + FUNCTION(qup2_se5), + FUNCTION(qup2_se6), + FUNCTION(qup3_se0), + FUNCTION(sail_top), + FUNCTION(sailss_emac0), + FUNCTION(sailss_ospi), + FUNCTION(sgmii_phy), + FUNCTION(tb_trig), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tgu_ch4), + FUNCTION(tgu_ch5), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsense_pwm3), + FUNCTION(tsense_pwm4), + FUNCTION(usb2phy_ac), + FUNCTION(vsense_trigger), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sa8775p_groups[] = { + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, pcie1_clkreq, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + _, _, _, _, _), + [7] = PINGROUP(7, sgmii_phy, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, emac0_mdc, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, emac0_mdio, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + _, _, _, _), + [11] = PINGROUP(11, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + _, _, _, _), + [12] = PINGROUP(12, usb2phy_ac, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, emac1_ptp_pps, + emac0_mcg0, _, _, _), + [13] = PINGROUP(13, qup3_se0, emac0_mcg1, _, _, sail_top, _, _, _, _), + [14] = PINGROUP(14, qup3_se0, emac0_mcg2, _, _, sail_top, _, _, _, _), + [15] = PINGROUP(15, qup3_se0, emac0_mcg3, _, _, sail_top, _, _, _, _), + [16] = PINGROUP(16, qup3_se0, emac1_mcg0, _, _, sail_top, _, _, _, _), + [17] = PINGROUP(17, qup3_se0, tb_trig, tb_trig, emac1_mcg1, _, _, _, _, _), + [18] = PINGROUP(18, qup3_se0, emac1_mcg2, _, _, sailss_ospi, sailss_emac0, _, _, _), + [19] = PINGROUP(19, qup3_se0, emac1_mcg3, _, _, sailss_ospi, sailss_emac0, _, _, _), + [20] = PINGROUP(20, qup0_se0, emac1_mdc, qdss_gpio, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se0, emac1_mdio, qdss_gpio, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se0, qdss_gpio, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se1, qdss_gpio, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup0_se1, phase_flag, _, qdss_gpio, _, _, _, _, _), + [26] = PINGROUP(26, sgmii_phy, qup0_se1, qdss_cti, phase_flag, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se1, qdss_cti, phase_flag, _, atest_char, _, _, _, _), + [28] = PINGROUP(28, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [29] = PINGROUP(29, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se3, phase_flag, _, qdss_gpio, _, _, _, _, _), + [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), + [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), + [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _), + [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _), + [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _), + [39] = PINGROUP(39, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch5, _, _, _, _), + [40] = PINGROUP(40, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync0, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se0, qup1_se1, ibi_i3c, mdp1_vsync1, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync2, gcc_gp5, _, _, _, _), + [43] = PINGROUP(43, qup1_se1, qup1_se0, ibi_i3c, mdp1_vsync3, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se2, qup1_se3, edp0_lcd, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se2, qup1_se3, edp1_lcd, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, qup1_se2, mdp1_vsync4, tgu_ch0, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, qup1_se2, mdp1_vsync5, tgu_ch1, _, _, _, _, _), + [48] = PINGROUP(48, qup1_se4, qdss_cti, edp2_lcd, _, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se4, qdss_cti, edp3_lcd, _, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se4, cci_async, qdss_cti, mdp1_vsync8, _, _, _, _, _), + [51] = PINGROUP(51, qup1_se4, qdss_cti, mdp1_vsync6, gcc_gp1, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se5, cci_timer4, cci_i2c, mdp1_vsync7, gcc_gp2, _, ddr_pxi1, _, _), + [53] = PINGROUP(53, qup1_se5, cci_timer5, cci_i2c, gcc_gp3, _, ddr_pxi1, _, _, _), + [54] = PINGROUP(54, qup1_se5, cci_timer6, cci_i2c, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, cci_timer7, cci_i2c, gcc_gp4, _, ddr_pxi2, _, _, _), + [56] = PINGROUP(56, qup1_se6, qup1_se6, cci_timer8, cci_i2c, phase_flag, + ddr_bist, _, _, _), + [57] = PINGROUP(57, qup1_se6, qup1_se6, cci_timer9, cci_i2c, mdp0_vsync0, + phase_flag, ddr_bist, _, _), + [58] = PINGROUP(58, cci_i2c, mdp0_vsync1, ddr_bist, _, atest_usb2, atest_char, _, _, _), + [59] = PINGROUP(59, cci_i2c, mdp0_vsync2, ddr_bist, _, atest_usb2, atest_char, _, _, _), + [60] = PINGROUP(60, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [61] = PINGROUP(61, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [62] = PINGROUP(62, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [63] = PINGROUP(63, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [64] = PINGROUP(64, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [65] = PINGROUP(65, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [66] = PINGROUP(66, cci_i2c, cci_async, qdss_gpio, _, _, _, _, _, _), + [67] = PINGROUP(67, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cci_timer0, cci_async, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cci_timer1, cci_async, _, _, _, _, _, _, _), + [70] = PINGROUP(70, cci_timer2, cci_async, _, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_timer3, cci_async, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cam_mclk, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, cam_mclk, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cam_mclk, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cam_mclk, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup2_se0, ibi_i3c, mdp0_vsync3, _, _, _, _, _, _), + [81] = PINGROUP(81, qup2_se0, ibi_i3c, mdp0_vsync4, _, _, _, _, _, _), + [82] = PINGROUP(82, qup2_se0, mdp_vsync, gcc_gp1, _, _, _, _, _, _), + [83] = PINGROUP(83, qup2_se0, mdp_vsync, gcc_gp2, _, _, _, _, _, _), + [84] = PINGROUP(84, qup2_se1, qup2_se5, ibi_i3c, mdp_vsync, gcc_gp3, _, _, _, _), + [85] = PINGROUP(85, qup2_se1, qup2_se5, ibi_i3c, _, _, _, _, _, _), + [86] = PINGROUP(86, qup2_se2, jitter_bist, atest_usb2, ddr_pxi2, _, _, _, _, _), + [87] = PINGROUP(87, qup2_se2, pll_clk, atest_usb2, ddr_pxi3, _, _, _, _, _), + [88] = PINGROUP(88, qup2_se2, _, atest_usb2, ddr_pxi3, _, _, _, _, _), + [89] = PINGROUP(89, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), + [90] = PINGROUP(90, qup2_se2, _, atest_usb2, ddr_pxi4, atest_char, _, _, _, _), + [91] = PINGROUP(91, qup2_se3, mdp0_vsync5, _, atest_usb2, _, _, _, _, _), + [92] = PINGROUP(92, qup2_se3, mdp0_vsync6, _, atest_usb2, _, _, _, _, _), + [93] = PINGROUP(93, qup2_se3, mdp0_vsync7, _, atest_usb2, _, _, _, _, _), + [94] = PINGROUP(94, qup2_se3, mdp0_vsync8, _, atest_usb2, _, _, _, _, _), + [95] = PINGROUP(95, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), + [96] = PINGROUP(96, qup2_se4, qup2_se6, _, atest_usb2, _, _, _, _, _), + [97] = PINGROUP(97, qup2_se6, qup2_se4, cri_trng0, _, atest_usb2, _, _, _, _), + [98] = PINGROUP(98, qup2_se6, qup2_se4, phase_flag, cri_trng1, _, _, _, _, _), + [99] = PINGROUP(99, qup2_se5, qup2_se1, phase_flag, cri_trng, _, _, _, _, _), + [100] = PINGROUP(100, qup2_se5, qup2_se1, _, _, _, _, _, _, _), + [101] = PINGROUP(101, edp0_hot, prng_rosc0, tsense_pwm4, _, _, _, _, _, _), + [102] = PINGROUP(102, edp1_hot, prng_rosc1, tsense_pwm3, _, _, _, _, _, _), + [103] = PINGROUP(103, edp3_hot, prng_rosc2, tsense_pwm2, _, _, _, _, _, _), + [104] = PINGROUP(104, edp2_hot, prng_rosc3, tsense_pwm1, _, _, _, _, _, _), + [105] = PINGROUP(105, mi2s_mclk0, _, qdss_gpio, atest_usb2, _, _, _, _, _), + [106] = PINGROUP(106, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), + [107] = PINGROUP(107, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _), + [108] = PINGROUP(108, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), + [109] = PINGROUP(109, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _), + [110] = PINGROUP(110, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _), + [111] = PINGROUP(111, mi2s2_ws, phase_flag, _, qdss_gpio, vsense_trigger, _, _, _, _), + [112] = PINGROUP(112, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _), + [113] = PINGROUP(113, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _), + [114] = PINGROUP(114, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _), + [115] = PINGROUP(115, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), + [116] = PINGROUP(116, hs0_mi2s, _, qdss_gpio, _, _, _, _, _, _), + [117] = PINGROUP(117, hs0_mi2s, mi2s_mclk1, _, qdss_gpio, _, _, _, _, _), + [118] = PINGROUP(118, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), + [119] = PINGROUP(119, hs1_mi2s, _, qdss_gpio, ddr_pxi5, _, _, _, _, _), + [120] = PINGROUP(120, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), + [121] = PINGROUP(121, hs1_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), + [122] = PINGROUP(122, hs2_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _), + [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), + [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), + [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [149] = UFS_RESET(ufs_reset, 0x1a2000), + [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), + [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), + [152] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x199000, 11, 3), + [153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { + .pins = sa8775p_pins, + .npins = ARRAY_SIZE(sa8775p_pins), + .functions = sa8775p_functions, + .nfunctions = ARRAY_SIZE(sa8775p_functions), + .groups = sa8775p_groups, + .ngroups = ARRAY_SIZE(sa8775p_groups), + .ngpios = 150, +}; + +static int sa8775p_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sa8775p_pinctrl); +} + +static const struct of_device_id sa8775p_pinctrl_of_match[] = { + { .compatible = "qcom,sa8775p-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sa8775p_pinctrl_of_match); + +static struct platform_driver sa8775p_pinctrl_driver = { + .driver = { + .name = "sa8775p-tlmm", + .of_match_table = sa8775p_pinctrl_of_match, + }, + .probe = sa8775p_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sa8775p_pinctrl_init(void) +{ + return platform_driver_register(&sa8775p_pinctrl_driver); +} +arch_initcall(sa8775p_pinctrl_init); + +static void __exit sa8775p_pinctrl_exit(void) +{ + platform_driver_unregister(&sa8775p_pinctrl_driver); +} +module_exit(sa8775p_pinctrl_exit); + +MODULE_DESCRIPTION("QTI SA8775P pinctrl driver"); +MODULE_LICENSE("GPL"); From 91d04c759c85f1fc2d3ed7d1b5bc1a7dbab87f92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 1 Feb 2023 16:43:21 +0100 Subject: [PATCH 097/118] dt-bindings: pinctrl: qcom,sm8350: add input-disable The SM8350 HDK8350 board uses input-disable property, so allow it: sm8350-hdk.dtb: pinctrl@f100000: lt9611-state: 'oneOf' conditional failed, one must be fixed: ... 'input-disable' does not match any of the regexes: 'pinctrl-[0-9]+' Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230201154321.276419-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index 49a74f351e996..e13d50d6d3888 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -109,6 +109,7 @@ $defs: bias-pull-down: true bias-pull-up: true drive-strength: true + input-disable: true input-enable: true output-high: true output-low: true From 792349083a7307bf34de26516bc047cfd5c6296b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:43 +0100 Subject: [PATCH 098/118] dt-bindings: pinctrl: qcom,msm8226: correct GPIO name pattern The MSM8226 TLMM pin controller has GPIOs 0-116, so correct the pattern to bring back missing 107-109. Acked-by: Rob Herring Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20230202104452.299048-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml index ab6672a4c8c12..59759a5742c44 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -56,7 +56,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 From 87b93dd1fbb23b9bbae461bb2c01f6d93c7524d9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:44 +0100 Subject: [PATCH 099/118] dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example The MSM8909 TLMM pin controller has GPIOs 0-112, so narrow the pattern and gpio-ranges in the example. Fixes: c249ec7ba1b1 ("dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmm") Reviewed-by: Stephan Gerhold Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml index 449e6e34be616..85082adc1811f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml @@ -63,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, qdsd_data3 ] @@ -127,7 +127,7 @@ examples: interrupts = ; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 117>; + gpio-ranges = <&tlmm 0 0 113>; interrupt-controller; #interrupt-cells = <2>; From a51c1f0244c84e482f1ceb4701c38aaa4b224baf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:45 +0100 Subject: [PATCH 100/118] dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example The SM6375 TLMM pin controller has GPIOs 0-155, so narrow the pattern and gpio-ranges in the example. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml index e4231d10d76f5..66cef48ed59b4 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml @@ -63,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 @@ -134,7 +134,7 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 157>; + gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */ gpio-wo-subnode-state { pins = "gpio1"; From 913137a1cd1e792587e8ae2a43d31389fdbaddf6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:46 +0100 Subject: [PATCH 101/118] dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern The MSM8953 TLMM pin controller has GPIOs 0-141, so narrow the pattern. Acked-by: Rob Herring Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20230202104452.299048-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index 6bcd520808016..ce219827ccc83 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -53,7 +53,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, qdsd_data3 ] From 5c7069712c9be01d1bf9061a7ef5ce78df0af0a5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:47 +0100 Subject: [PATCH 102/118] dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern The SDX55 TLMM pin controller has GPIOs 0-107, so narrow the pattern. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml index add3c7e64520b..a40175258495a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -55,7 +55,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 From 174668bf5f6c2dd03441a4660e249cc5e2c78b95 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:48 +0100 Subject: [PATCH 103/118] dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs The MSM8994 TLMM pin controller has GPIOs 0-145, so narrow the pattern and reduce sizes of arrays with pins. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml index f4a8180f59590..0c4936fc35ef4 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -34,10 +34,10 @@ properties: gpio-reserved-ranges: minItems: 1 - maxItems: 75 + maxItems: 73 gpio-line-names: - maxItems: 150 + maxItems: 146 patternProperties: "-state$": @@ -63,7 +63,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] minItems: 1 From 6f4e10ffa8fbccf220f7c5c869e8373065b9ef7d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 2 Feb 2023 11:44:49 +0100 Subject: [PATCH 104/118] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples Correct the number of GPIOs in gpio-ranges to match reality. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230202104452.299048-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 2 +- Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index 56e058c315f75..cf561dff8893d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -131,6 +131,6 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 180>; + gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */ wakeup-parent = <&pdc>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml index e13d50d6d3888..797242f68b1c9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -130,7 +130,7 @@ examples: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 203>; + gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */ gpio-wo-subnode-state { pins = "gpio1"; From 1c4e5c470a56f7f7c649c0c70e603abc1eab15c4 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 3 Feb 2023 15:27:14 +0200 Subject: [PATCH 105/118] pinctrl: at91: use devm_kasprintf() to avoid potential leaks Use devm_kasprintf() instead of kasprintf() to avoid any potential leaks. At the moment drivers have no remove functionality thus there is no need for fixes tag. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230203132714.1931596-1-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 4 ++-- drivers/pinctrl/pinctrl-at91.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 39b233f73e132..373eed8bc4be9 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1149,8 +1149,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) pin_desc[i].number = i; /* Pin naming convention: P(bank_name)(bank_pin_number). */ - pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", - bank + 'A', line); + pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%d", + bank + 'A', line); group->name = group_names[i] = pin_desc[i].name; group->pin = pin_desc[i].number; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 9a066355fd279..735c501e7a06c 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1875,7 +1875,7 @@ static int at91_gpio_probe(struct platform_device *pdev) } for (i = 0; i < chip->ngpio; i++) - names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); + names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); chip->names = (const char *const *)names; From 268e97ccc311492707f3bc4b761e77605effcfb2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Feb 2023 18:46:44 +0100 Subject: [PATCH 106/118] dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS Add bidings for pin controller in Low Power Audio SubSystem (LPASS). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230203174645.597053-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- .../qcom,sm8550-lpass-lpi-pinctrl.yaml | 148 ++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000000000..5e90051ed314a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski + - Srinivas Kandagatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC. + +properties: + compatible: + const: qcom,sm8550-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI pins SLEW registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + "#gpio-cells": + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8550-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8550-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8550-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, + i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0x06e80000 0x20000>, + <0x0725a000 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; From 5a6ca1f240d6a268e1f63387a676b2cf9669fe21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Feb 2023 18:46:45 +0100 Subject: [PATCH 107/118] pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS Add druver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8450 LPASS pin controller, with differences in few pin groups (qua_mi2s -> i2s0). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230203174645.597053-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 11 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 240 ++++++++++++++++++ 3 files changed, 252 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 8d4f871e07cf8..6e306992fad99 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -486,6 +486,17 @@ config PINCTRL_SM8550 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8550 platform. +config PINCTRL_SM8550_LPASS_LPI + tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM8550 + platform. + config PINCTRL_LPASS_LPI tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" select PINMUX diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 6763aa8d319c6..37bfbcf8234b0 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -50,5 +50,6 @@ obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o +obj-$(CONFIG_PINCTRL_SM8550_LPASS_LPI) += pinctrl-sm8550-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c new file mode 100644 index 0000000000000..c2bdd936d27f0 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_i2s4_clk, + LPI_MUX_i2s4_data, + LPI_MUX_i2s4_ws, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] = { 0 }; +static int gpio1_pins[] = { 1 }; +static int gpio2_pins[] = { 2 }; +static int gpio3_pins[] = { 3 }; +static int gpio4_pins[] = { 4 }; +static int gpio5_pins[] = { 5 }; +static int gpio6_pins[] = { 6 }; +static int gpio7_pins[] = { 7 }; +static int gpio8_pins[] = { 8 }; +static int gpio9_pins[] = { 9 }; +static int gpio10_pins[] = { 10 }; +static int gpio11_pins[] = { 11 }; +static int gpio12_pins[] = { 12 }; +static int gpio13_pins[] = { 13 }; +static int gpio14_pins[] = { 14 }; +static int gpio15_pins[] = { 15 }; +static int gpio16_pins[] = { 16 }; +static int gpio17_pins[] = { 17 }; +static int gpio18_pins[] = { 18 }; +static int gpio19_pins[] = { 19 }; +static int gpio20_pins[] = { 20 }; +static int gpio21_pins[] = { 21 }; +static int gpio22_pins[] = { 22 }; + +static const struct pinctrl_pin_desc sm8550_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const dmic4_clk_groups[] = { "gpio17" }; +static const char * const dmic4_data_groups[] = { "gpio18" }; +static const char * const i2s0_clk_groups[] = { "gpio0" }; +static const char * const i2s0_ws_groups[] = { "gpio1" }; +static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" }; +static const char * const i2s3_clk_groups[] = { "gpio12" }; +static const char * const i2s3_ws_groups[] = { "gpio13" }; +static const char * const i2s3_data_groups[] = { "gpio17", "gpio18" }; +static const char * const i2s4_clk_groups[] = { "gpio19"}; +static const char * const i2s4_ws_groups[] = { "gpio20"}; +static const char * const i2s4_data_groups[] = { "gpio21", "gpio22"}; +static const char * const slimbus_clk_groups[] = { "gpio19"}; +static const char * const slimbus_data_groups[] = { "gpio20"}; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const wsa2_swr_clk_groups[] = { "gpio15" }; +static const char * const wsa2_swr_data_groups[] = { "gpio16" }; +static const char * const ext_mclk1_c_groups[] = { "gpio5" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const ext_mclk1_a_groups[] = { "gpio13" }; +static const char * const ext_mclk1_d_groups[] = { "gpio14" }; +static const char * const ext_mclk1_e_groups[] = { "gpio22" }; + +static const struct lpi_pingroup sm8550_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _), + LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s4_clk, slimbus_clk, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s4_ws, slimbus_data, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s4_data, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s4_data, ext_mclk1_e, _, _), +}; + +static const struct lpi_function sm8550_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(i2s4_clk), + LPI_FUNCTION(i2s4_data), + LPI_FUNCTION(i2s4_ws), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), +}; + +static const struct lpi_pinctrl_variant_data sm8550_lpi_data = { + .pins = sm8550_lpi_pins, + .npins = ARRAY_SIZE(sm8550_lpi_pins), + .groups = sm8550_groups, + .ngroups = ARRAY_SIZE(sm8550_groups), + .functions = sm8550_functions, + .nfunctions = ARRAY_SIZE(sm8550_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm8550-lpass-lpi-pinctrl", + .data = &sm8550_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm SM8550 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From 315dffb843f75cec4458714f4d151d5775e797de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 3 Feb 2023 17:48:50 +0100 Subject: [PATCH 108/118] dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern Narrow the pattern of possible GPIO names for pin controllers: - SC7280 LPASS: GPIOs 0-14 - SM8250 LPASS: GPIOs 0-13 - SM8450 LPASS: GPIOs 0-22 - SC8280XP LPASS: GPIOs 0-18 Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230203164854.390080-1-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230203164854.390080-2-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230203164854.390080-3-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230203164854.390080-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 2 +- .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index f7ec8a4f664fe..e51feb4c07005 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -59,7 +59,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" + - pattern: "^gpio([0-9]|1[0-4])$" minItems: 1 maxItems: 15 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml index 9a3f1fb8c2f73..200b3b6ccd87f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -134,7 +134,7 @@ examples: clock-names = "core", "audio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&lpi_tlmm 0 0 18>; + gpio-ranges = <&lpi_tlmm 0 0 19>; dmic01-state { dmic01-clk-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml index bd45faa3f0789..de9d8854c6901 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -64,7 +64,7 @@ $defs: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9])$" + - pattern: "^gpio([0-9]|1[0-3])$" minItems: 1 maxItems: 14 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index 01a0a4a40ba57..6acaa42a3c1b9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -65,7 +65,7 @@ $defs: List of gpio pins affected by the properties specified in this subnode. items: - pattern: "^gpio([0-9]|[1-2][0-9])$" + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" function: enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, From 2e7851437731cf51010568118efccfd13ee97de0 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 6 Feb 2023 12:42:09 +0530 Subject: [PATCH 109/118] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Add device tree bindings for IPQ5332 TLMM block. Signed-off-by: Kathiravan T Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230206071217.29313-2-quic_kathirav@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,ipq5332-tlmm.yaml | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml new file mode 100644 index 0000000000000..300747252a7b5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5332 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5332-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 53 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5332-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5332-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5332-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0, + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, + blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, + gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1, + mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, + pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0, + rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd, + wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ] + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <0x2>; + + serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; From 75dc7e600ef53ddf6994a753b13385da174e72d4 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 6 Feb 2023 12:42:10 +0530 Subject: [PATCH 110/118] pinctrl: qcom: Introduce IPQ5332 TLMM driver The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm platforms, so add a driver for it. Signed-off-by: Kathiravan T Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206071217.29313-3-quic_kathirav@quicinc.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5332.c | 861 +++++++++++++++++++++++++ 3 files changed, 872 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 6e306992fad99..62d4810cfee11 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -48,6 +48,16 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. +config PINCTRL_IPQ5332 + tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" + depends on OF + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc IPQ5332 platform. + config PINCTRL_IPQ8074 tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 37bfbcf8234b0..bea53b52275ba 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c new file mode 100644 index 0000000000000..e78d11292f424 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq5332_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); + +enum ipq5332_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tic, + msm_mux_audio_pri, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_sec, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart0, + msm_mux_blsp0_uart1, + msm_mux_blsp1_i2c0, + msm_mux_blsp1_i2c1, + msm_mux_blsp1_spi0, + msm_mux_blsp1_spi1, + msm_mux_blsp1_uart0, + msm_mux_blsp1_uart1, + msm_mux_blsp1_uart2, + msm_mux_blsp2_i2c0, + msm_mux_blsp2_i2c1, + msm_mux_blsp2_spi, + msm_mux_blsp2_spi0, + msm_mux_blsp2_spi1, + msm_mux_core_voltage, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_cxc_clk, + msm_mux_cxc_data, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_lock_det, + msm_mux_mac0, + msm_mux_mac1, + msm_mux_mdc0, + msm_mux_mdc1, + msm_mux_mdio0, + msm_mux_mdio1, + msm_mux_pc, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pll_test, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_pta, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_resout, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_sdc_data, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_tsens_max, + msm_mux_wci_txd, + msm_mux_wci_rxd, + msm_mux_wsi_clk, + msm_mux_wsi_clk3, + msm_mux_wsi_data, + msm_mux_wsi_data3, + msm_mux_wsis_reset, + msm_mux_xfem, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", +}; + +static const char * const atest_char_groups[] = { + "gpio46", +}; + +static const char * const atest_char0_groups[] = { + "gpio0", +}; + +static const char * const atest_char1_groups[] = { + "gpio1", +}; + +static const char * const atest_char2_groups[] = { + "gpio2", +}; + +static const char * const atest_char3_groups[] = { + "gpio3", +}; + +static const char * const atest_tic_groups[] = { + "gpio9", +}; + +static const char * const audio_pri_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const audio_pri0_groups[] = { + "gpio34", "gpio34", +}; + +static const char * const audio_pri1_groups[] = { + "gpio43", "gpio43", +}; + +static const char * const audio_sec_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const audio_sec0_groups[] = { + "gpio30", "gpio30", +}; + +static const char * const audio_sec1_groups[] = { + "gpio45", "gpio45", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio16", "gpio17", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const blsp0_uart0_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const blsp0_uart1_groups[] = { + "gpio27", "gpio28", +}; + +static const char * const blsp1_i2c0_groups[] = { + "gpio29", "gpio30", +}; + +static const char * const blsp1_i2c1_groups[] = { + "gpio40", "gpio41", +}; + +static const char * const blsp1_spi0_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const blsp1_spi1_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const blsp1_uart0_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const blsp1_uart1_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const blsp1_uart2_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const blsp2_i2c0_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const blsp2_i2c1_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio37", +}; + +static const char * const blsp2_spi0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const blsp2_spi1_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio52", +}; + +static const char * const core_voltage_groups[] = { + "gpio21", "gpio23", +}; + +static const char * const cri_trng0_groups[] = { + "gpio17", +}; + +static const char * const cri_trng1_groups[] = { + "gpio18", +}; + +static const char * const cri_trng2_groups[] = { + "gpio19", +}; + +static const char * const cri_trng3_groups[] = { + "gpio20", +}; + +static const char * const cxc_clk_groups[] = { + "gpio49", +}; + +static const char * const cxc_data_groups[] = { + "gpio50", +}; + +static const char * const dbg_out_groups[] = { + "gpio48", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio44", +}; + +static const char * const lock_det_groups[] = { + "gpio51", +}; + +static const char * const mac0_groups[] = { + "gpio18", +}; + +static const char * const mac1_groups[] = { + "gpio19", +}; + +static const char * const mdc0_groups[] = { + "gpio25", +}; + +static const char * const mdc1_groups[] = { + "gpio27", +}; + +static const char * const mdio0_groups[] = { + "gpio26", +}; + +static const char * const mdio1_groups[] = { + "gpio28", +}; + +static const char * const pc_groups[] = { + "gpio35", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio37", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio39", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio46", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio48", +}; + +static const char * const pcie2_clk_groups[] = { + "gpio43", +}; + +static const char * const pcie2_wake_groups[] = { + "gpio45", +}; + +static const char * const pll_test_groups[] = { + "gpio49", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio22", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio24", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio25", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio26", +}; + +static const char * const pta_groups[] = { + "gpio49", "gpio50", "gpio51", +}; + +static const char * const pwm0_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const pwm1_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const pwm2_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const pwm3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio5", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio7", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio47", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio49", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio4", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio6", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio46", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio48", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio8", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio45", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio9", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio44", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio18", "gpio19", "gpio20", "gpio22", "gpio24", "gpio25", + "gpio26", "gpio27", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio52", +}; + +static const char * const qspi_clk_groups[] = { + "gpio13", +}; + +static const char * const qspi_cs_groups[] = { + "gpio12", +}; + +static const char * const qspi_data_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const resout_groups[] = { + "gpio20", +}; + +static const char * const rx0_groups[] = { + "gpio48", +}; + +static const char * const rx1_groups[] = { + "gpio45", +}; + +static const char * const sdc_clk_groups[] = { + "gpio13", +}; + +static const char * const sdc_cmd_groups[] = { + "gpio12", +}; + +static const char * const sdc_data_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const tsens_max_groups[] = { + "gpio28", +}; + +static const char * const wci_txd_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio36", "gpio43", "gpio45", +}; + +static const char * const wci_rxd_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio35", "gpio36", "gpio43", "gpio45", +}; + +static const char * const wsi_clk_groups[] = { + "gpio40", "gpio42", +}; + +static const char * const wsi_clk3_groups[] = { + "gpio43", +}; + +static const char * const wsi_data_groups[] = { + "gpio41", "gpio52", +}; + +static const char * const wsi_data3_groups[] = { + "gpio44", +}; + +static const char * const wsis_reset_groups[] = { + "gpio41", +}; + +static const char * const xfem_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const struct msm_function ipq5332_functions[] = { + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_tic), + FUNCTION(audio_pri), + FUNCTION(audio_pri0), + FUNCTION(audio_pri1), + FUNCTION(audio_sec), + FUNCTION(audio_sec0), + FUNCTION(audio_sec1), + FUNCTION(blsp0_i2c), + FUNCTION(blsp0_spi), + FUNCTION(blsp0_uart0), + FUNCTION(blsp0_uart1), + FUNCTION(blsp1_i2c0), + FUNCTION(blsp1_i2c1), + FUNCTION(blsp1_spi0), + FUNCTION(blsp1_spi1), + FUNCTION(blsp1_uart0), + FUNCTION(blsp1_uart1), + FUNCTION(blsp1_uart2), + FUNCTION(blsp2_i2c0), + FUNCTION(blsp2_i2c1), + FUNCTION(blsp2_spi), + FUNCTION(blsp2_spi0), + FUNCTION(blsp2_spi1), + FUNCTION(core_voltage), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(cri_trng2), + FUNCTION(cri_trng3), + FUNCTION(cxc_clk), + FUNCTION(cxc_data), + FUNCTION(dbg_out), + FUNCTION(gcc_plltest), + FUNCTION(gcc_tlmm), + FUNCTION(gpio), + FUNCTION(lock_det), + FUNCTION(mac0), + FUNCTION(mac1), + FUNCTION(mdc0), + FUNCTION(mdc1), + FUNCTION(mdio0), + FUNCTION(mdio1), + FUNCTION(pc), + FUNCTION(pcie0_clk), + FUNCTION(pcie0_wake), + FUNCTION(pcie1_clk), + FUNCTION(pcie1_wake), + FUNCTION(pcie2_clk), + FUNCTION(pcie2_wake), + FUNCTION(pll_test), + FUNCTION(prng_rosc0), + FUNCTION(prng_rosc1), + FUNCTION(prng_rosc2), + FUNCTION(prng_rosc3), + FUNCTION(pta), + FUNCTION(pwm0), + FUNCTION(pwm1), + FUNCTION(pwm2), + FUNCTION(pwm3), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(qspi_data), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(resout), + FUNCTION(rx0), + FUNCTION(rx1), + FUNCTION(sdc_data), + FUNCTION(sdc_clk), + FUNCTION(sdc_cmd), + FUNCTION(tsens_max), + FUNCTION(wci_txd), + FUNCTION(wci_rxd), + FUNCTION(wsi_clk), + FUNCTION(wsi_clk3), + FUNCTION(wsi_data), + FUNCTION(wsi_data3), + FUNCTION(wsis_reset), + FUNCTION(xfem), +}; + +static const struct msm_pingroup ipq5332_groups[] = { + PINGROUP(0, atest_char0, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(1, atest_char1, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(2, atest_char2, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(3, atest_char3, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(4, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(5, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(6, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(7, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _), + PINGROUP(8, sdc_data, qspi_data, pwm3, qdss_traceclk_a, _, _, _, _, _), + PINGROUP(9, sdc_data, qspi_data, pwm3, qdss_tracectl_a, _, atest_tic, _, _, _), + PINGROUP(10, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(11, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(12, sdc_cmd, qspi_cs, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(13, sdc_clk, qspi_clk, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(14, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(15, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(16, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _), + PINGROUP(17, blsp0_spi, blsp0_i2c, blsp1_uart0, _, cri_trng0, qdss_tracedata_a, _, _, _), + PINGROUP(18, blsp0_uart0, mac0, _, cri_trng1, qdss_tracedata_a, _, _, _, _), + PINGROUP(19, blsp0_uart0, mac1, _, cri_trng2, qdss_tracedata_a, _, _, _, _), + PINGROUP(20, resout, _, cri_trng3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(21, core_voltage, _, _, _, _, _, _, _, _), + PINGROUP(22, _, prng_rosc0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(23, core_voltage, _, _, _, _, _, _, _, _), + PINGROUP(24, _, prng_rosc1, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(25, mdc0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc2, qdss_tracedata_a, _), + PINGROUP(26, mdio0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc3, qdss_tracedata_a, _), + PINGROUP(27, mdc1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, _, qdss_tracedata_a, _), + PINGROUP(28, mdio1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, tsens_max, _, _), + PINGROUP(29, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, _, qdss_tracedata_b, _, _, _), + PINGROUP(30, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, audio_sec0, audio_sec0, _, qdss_tracedata_b, _), + PINGROUP(31, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(32, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _), + PINGROUP(33, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, _, qdss_tracedata_b, _, _, _), + PINGROUP(34, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, audio_pri0, audio_pri0, _, qdss_tracedata_b, _), + PINGROUP(35, audio_sec, blsp1_uart2, pc, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _), + PINGROUP(36, audio_sec, blsp1_uart2, wci_txd, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _), + PINGROUP(37, pcie0_clk, blsp2_spi, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(38, _, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(39, pcie0_wake, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(40, wsi_clk, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, _, _), + PINGROUP(41, wsi_data, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, wsis_reset, _), + PINGROUP(42, wsi_clk, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _), + PINGROUP(43, pcie2_clk, wci_txd, wci_rxd, blsp2_i2c0, pwm0, audio_pri1, audio_pri1, _, gcc_plltest), + PINGROUP(44, pwm0, _, gcc_tlmm, qdss_tracectl_b, _, wsi_data3, _, _, _), + PINGROUP(45, pcie2_wake, wci_txd, wci_rxd, blsp2_i2c0, rx1, pwm0, audio_sec1, audio_sec1, _), + PINGROUP(46, pcie1_clk, atest_char, pwm0, _, qdss_cti_trig_out_b0, _, _, _, _), + PINGROUP(47, _, qdss_cti_trig_in_b0, _, _, _, _, _, _, _), + PINGROUP(48, pcie1_wake, rx0, dbg_out, qdss_cti_trig_out_b1, _, _, _, _, _), + PINGROUP(49, pta, cxc_clk, pll_test, _, qdss_cti_trig_in_b1, _, _, _, _), + PINGROUP(50, pta, cxc_data, _, _, _, _, _, _, _), + PINGROUP(51, pta, lock_det, _, _, _, _, _, _, _), + PINGROUP(52, wsi_data, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5332_pinctrl = { + .pins = ipq5332_pins, + .npins = ARRAY_SIZE(ipq5332_pins), + .functions = ipq5332_functions, + .nfunctions = ARRAY_SIZE(ipq5332_functions), + .groups = ipq5332_groups, + .ngroups = ARRAY_SIZE(ipq5332_groups), + .ngpios = 53, +}; + +static int ipq5332_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5332_pinctrl); +} + +static const struct of_device_id ipq5332_pinctrl_of_match[] = { + { .compatible = "qcom,ipq5332-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq5332_pinctrl_of_match); + +static struct platform_driver ipq5332_pinctrl_driver = { + .driver = { + .name = "ipq5332-tlmm", + .of_match_table = ipq5332_pinctrl_of_match, + }, + .probe = ipq5332_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq5332_pinctrl_init(void) +{ + return platform_driver_register(&ipq5332_pinctrl_driver); +} +arch_initcall(ipq5332_pinctrl_init); + +static void __exit ipq5332_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq5332_pinctrl_driver); +} +module_exit(ipq5332_pinctrl_exit); + +MODULE_DESCRIPTION("QTI IPQ5332 TLMM driver"); +MODULE_LICENSE("GPL"); From 9421655de886bc89843412001a7cdd9423b3418f Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 21 Jan 2023 12:08:20 +0100 Subject: [PATCH 111/118] dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated Mark gpio sub nodes of pinctrl as deprecated. Gpio nodes are now placed in the root of the device tree. The relation to pinctrl is now described with the "gpio-ranges" property. Signed-off-by: Johan Jonker Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/137b56f0-8e86-f705-4ba7-d5dfe3c0b477@gmail.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index d6539723f354b..45b767986a878 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -76,15 +76,13 @@ allOf: required: - compatible - rockchip,grf - - "#address-cells" - - "#size-cells" - - ranges patternProperties: "gpio@[0-9a-f]+$": type: object $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#" + deprecated: true unevaluatedProperties: false From d4059de433287ee7b44e1790c7c1460eb5d3d674 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 26 Jan 2023 00:34:15 +0000 Subject: [PATCH 112/118] dt-bindings: pinctrl: add bindings for MT7981 SoC Add bindings for the MT7981 pinctrl driver. As MT7981 has most features in common with MT7986 (but has a different layout in terms on pinctrl and clocks), the existing mediatek,mt7986-pinctrl.yaml was used as an example to create a similar document covering MT7981. Signed-off-by: Daniel Golle Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/3f0fd0becc338eef66caeb7244c3c432b8d1ef7a.1674693008.git.daniel@makrotopia.org Signed-off-by: Linus Walleij --- .../pinctrl/mediatek,mt7981-pinctrl.yaml | 475 ++++++++++++++++++ 1 file changed, 475 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml new file mode 100644 index 0000000000000..74c66fbcb2ae6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -0,0 +1,475 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT7981 Pin Controller + +maintainers: + - Daniel Golle + +description: + The MediaTek's MT7981 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7981-pinctrl + + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: gpio + - const: iocfg_rt + - const: iocfg_rm + - const: iocfg_rb + - const: iocfg_lb + - const: iocfg_bl + - const: iocfg_tm + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: > + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^.*mux.*$': + type: object + additionalProperties: false + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "wa_aice1" "wa_aice" 0, 1 + "wa_aice2" "wa_aice" 0, 1 + "wm_uart_0" "uart" 0, 1 + "dfd" "dfd" 0, 1, 4, 5 + "watchdog" "watchdog" 2 + "pcie_pereset" "pcie" 3 + "jtag" "jtag" 4, 5, 6, 7, 8 + "wm_jtag_0" "jtag" 4, 5, 6, 7, 8 + "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13 + "uart2_0" "uart" 4, 5, 6, 7 + "gbe_led0" "led" 8 + "pta_ext_0" "pta" 4, 5, 6 + "pwm2" "pwm" 7 + "net_wo0_uart_txd_0" "uart" 8 + "spi1_0" "spi" 4, 5, 6, 7 + "i2c0_0" "i2c" 6, 7 + "dfd_ntrst" "dfd" 8 + "wm_aice1" "wa_aice" 9, 10 + "pwm0_0" "pwm" 13 + "pwm0_1" "pwm" 15 + "pwm1_0" "pwm" 14 + "pwm1_1" "pwm" 15 + "net_wo0_uart_txd_1" "uart" 14 + "net_wo0_uart_txd_2" "uart" 15 + "gbe_led1" "led" 13 + "pcm" "pcm" 9, 10, 11, 12, 13, 25 + "watchdog1" "watchdog" 13 + "udi" "udi" 9, 10, 11, 12, 13 + "drv_vbus" "usb" 14 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 + "snfi" "flash" 16, 17, 18, 19, 20, 21 + "spi0" "spi" 16, 17, 18, 19 + "spi0_wp_hold" "spi" 20, 21 + "spi1_1" "spi" 22, 23, 24, 25 + "spi2" "spi" 26, 27, 28, 29 + "spi2_wp_hold" "spi" 30, 31 + "uart1_0" "uart" 16, 17, 18, 19 + "uart1_1" "uart" 26, 27, 28, 29 + "uart2_1" "uart" 22, 23, 24, 25 + "pta_ext_1" "pta" 22, 23, 24 + "wm_aurt_1" "uart" 20, 21 + "wm_aurt_2" "uart" 30, 31 + "wm_jtag_1" "jtag" 20, 21, 22, 23, 24 + "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29 + "wa_aice3" "wa_aice" 28, 20 + "wm_aice2" "wa_aice" 30, 31 + "i2c0_1" "i2c" 30, 31 + "u2_phy_i2c" "i2c" 30, 31 + "uart0" "uart" 32, 33 + "sgmii1_phy_i2c" "i2c" 32, 33 + "u3_phy_i2c" "i2c" 32, 33 + "sgmii0_phy_i2c" "i2c" 32, 33 + "pcie_clk" "pcie" 34 + "pcie_wake" "pcie" 35 + "i2c0_2" "i2c" 36, 37 + "smi_mdc_mdio" "eth" 36, 37 + "gbe_ext_mdc_mdio" "eth" 36, 37 + "wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56 + + "wf0_mode3" "eth" 45, 46, 47, 48, 49, 51 + "wf2g_led0" "led" 30 + "wf2g_led1" "led" 34 + "wf5g_led0" "led" 31 + "wf5g_led1" "led" 35 + "mt7531_int" "eth" 38 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22 + 23, 24, 25, 34, 35 + + $ref: /schemas/pinctrl/pinmux-node.yaml + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led, + pwm, spi, uart, watchdog, flash, pcie] + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: wa_aice + then: + properties: + groups: + enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2] + - if: + properties: + function: + const: dfd + then: + properties: + groups: + enum: [dfd, dfd_ntrst] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1] + - if: + properties: + function: + const: pta + then: + properties: + groups: + enum: [pta_ext_0, pta_ext_1] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm] + - if: + properties: + function: + const: udi + then: + properties: + groups: + enum: [udi] + - if: + properties: + function: + const: usb + then: + properties: + groups: + enum: [drv_vbus] + - if: + properties: + function: + const: ant + then: + properties: + groups: + enum: [ant_sel] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3, + mt7531_int] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c, + sgmii0_phy_i2c, i2c0_2] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1] + maxItems: 3 + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold] + maxItems: 4 + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0, + net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0, + uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0] + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + enum: [watchdog] + - if: + properties: + function: + const: flash + then: + properties: + groups: + items: + enum: [emmc_45, snfi] + maxItems: 1 + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie_clk, pcie_wake, pcie_pereset] + maxItems: 3 + + '^.*conf.*$': + type: object + additionalProperties: false + description: pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N, + JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N, + WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK, + WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, + SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, + SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ, + PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, + WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, + WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, + WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10] + maxItems: 57 + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: > + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: > + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up setings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down setings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 56>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio_pins: mdio-pins { + mux { + function = "eth"; + groups = "smi_mdc_mdio"; + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = ; + bias-pull-up = ; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = ; + bias-pull-down = ; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + }; + }; From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 26 Jan 2023 00:34:56 +0000 Subject: [PATCH 113/118] pinctrl: add mt7981 pinctrl driver Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver which can also be found the SDK. Signed-off-by: Daniel Golle Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 5 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++ 3 files changed, 1054 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index fed02c6fea062..f20c28334bcbf 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -127,6 +127,11 @@ config PINCTRL_MT7622 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT7981 + bool "Mediatek MT7981 pin control" + depends on OF + select PINCTRL_MTK_MOORE + config PINCTRL_MT7986 bool "Mediatek MT7986 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 53265404a39d8..44d197af516a9 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c new file mode 100644 index 0000000000000..18abc57800111 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -0,0 +1,1048 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7981 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2020 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +#define MT7981_PIN(_number, _name) \ + MTK_PIN(_number, _name, 0, _number, DRV_GRP4) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { + PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { + PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { + PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { + PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), + + PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), + + PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { + PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { + PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), + + PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), + + PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), + + PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), + PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), + + PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), + + PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), + + PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), + + PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), + + PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), + + PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), + + PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), + + PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), + + PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), +}; + +static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), + + PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), + + PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), + + PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), + + PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), + + PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), + + PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), + + PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), +}; + +static const unsigned int mt7981_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ +}; + +static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7981_pins[] = { + MT7981_PIN(0, "GPIO_WPS"), + MT7981_PIN(1, "GPIO_RESET"), + MT7981_PIN(2, "SYS_WATCHDOG"), + MT7981_PIN(3, "PCIE_PERESET_N"), + MT7981_PIN(4, "JTAG_JTDO"), + MT7981_PIN(5, "JTAG_JTDI"), + MT7981_PIN(6, "JTAG_JTMS"), + MT7981_PIN(7, "JTAG_JTCLK"), + MT7981_PIN(8, "JTAG_JTRST_N"), + MT7981_PIN(9, "WO_JTAG_JTDO"), + MT7981_PIN(10, "WO_JTAG_JTDI"), + MT7981_PIN(11, "WO_JTAG_JTMS"), + MT7981_PIN(12, "WO_JTAG_JTCLK"), + MT7981_PIN(13, "WO_JTAG_JTRST_N"), + MT7981_PIN(14, "USB_VBUS"), + MT7981_PIN(15, "PWM0"), + MT7981_PIN(16, "SPI0_CLK"), + MT7981_PIN(17, "SPI0_MOSI"), + MT7981_PIN(18, "SPI0_MISO"), + MT7981_PIN(19, "SPI0_CS"), + MT7981_PIN(20, "SPI0_HOLD"), + MT7981_PIN(21, "SPI0_WP"), + MT7981_PIN(22, "SPI1_CLK"), + MT7981_PIN(23, "SPI1_MOSI"), + MT7981_PIN(24, "SPI1_MISO"), + MT7981_PIN(25, "SPI1_CS"), + MT7981_PIN(26, "SPI2_CLK"), + MT7981_PIN(27, "SPI2_MOSI"), + MT7981_PIN(28, "SPI2_MISO"), + MT7981_PIN(29, "SPI2_CS"), + MT7981_PIN(30, "SPI2_HOLD"), + MT7981_PIN(31, "SPI2_WP"), + MT7981_PIN(32, "UART0_RXD"), + MT7981_PIN(33, "UART0_TXD"), + MT7981_PIN(34, "PCIE_CLK_REQ"), + MT7981_PIN(35, "PCIE_WAKE_N"), + MT7981_PIN(36, "SMI_MDC"), + MT7981_PIN(37, "SMI_MDIO"), + MT7981_PIN(38, "GBE_INT"), + MT7981_PIN(39, "GBE_RESET"), + MT7981_PIN(40, "WF_DIG_RESETB"), + MT7981_PIN(41, "WF_CBA_RESETB"), + MT7981_PIN(42, "WF_XO_REQ"), + MT7981_PIN(43, "WF_TOP_CLK"), + MT7981_PIN(44, "WF_TOP_DATA"), + MT7981_PIN(45, "WF_HB1"), + MT7981_PIN(46, "WF_HB2"), + MT7981_PIN(47, "WF_HB3"), + MT7981_PIN(48, "WF_HB4"), + MT7981_PIN(49, "WF_HB0"), + MT7981_PIN(50, "WF_HB0_B"), + MT7981_PIN(51, "WF_HB5"), + MT7981_PIN(52, "WF_HB6"), + MT7981_PIN(53, "WF_HB7"), + MT7981_PIN(54, "WF_HB8"), + MT7981_PIN(55, "WF_HB9"), + MT7981_PIN(56, "WF_HB10"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* WA_AICE */ +static int mt7981_wa_aice1_pins[] = { 0, 1, }; +static int mt7981_wa_aice1_funcs[] = { 2, 2, }; + +static int mt7981_wa_aice2_pins[] = { 0, 1, }; +static int mt7981_wa_aice2_funcs[] = { 3, 3, }; + +static int mt7981_wa_aice3_pins[] = { 28, 29, }; +static int mt7981_wa_aice3_funcs[] = { 3, 3, }; + +static int mt7981_wm_aice1_pins[] = { 9, 10, }; +static int mt7981_wm_aice1_funcs[] = { 2, 2, }; + +static int mt7981_wm_aice2_pins[] = { 30, 31, }; +static int mt7981_wm_aice2_funcs[] = { 5, 5, }; + +/* WM_UART */ +static int mt7981_wm_uart_0_pins[] = { 0, 1, }; +static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; + +static int mt7981_wm_uart_1_pins[] = { 20, 21, }; +static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; + +static int mt7981_wm_uart_2_pins[] = { 30, 31, }; +static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; + +/* DFD */ +static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; +static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; + +/* SYS_WATCHDOG */ +static int mt7981_watchdog_pins[] = { 2, }; +static int mt7981_watchdog_funcs[] = { 1, }; + +static int mt7981_watchdog1_pins[] = { 13, }; +static int mt7981_watchdog1_funcs[] = { 5, }; + +/* PCIE_PERESET_N */ +static int mt7981_pcie_pereset_pins[] = { 3, }; +static int mt7981_pcie_pereset_funcs[] = { 1, }; + +/* JTAG */ +static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; +static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; + +/* WM_JTAG */ +static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; +static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; + +static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; +static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; + +/* WO0_JTAG */ +static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; +static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; + +static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; +static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; + +/* UART2 */ +static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; +static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; + +/* GBE_LED0 */ +static int mt7981_gbe_led0_pins[] = { 8, }; +static int mt7981_gbe_led0_funcs[] = { 3, }; + +/* PTA_EXT */ +static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; +static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; + +static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; +static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; + +/* PWM2 */ +static int mt7981_pwm2_pins[] = { 7, }; +static int mt7981_pwm2_funcs[] = { 4, }; + +/* NET_WO0_UART_TXD */ +static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; +static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; + +static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; +static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; + +static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; +static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; + +/* SPI1 */ +static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; +static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; + +/* I2C */ +static int mt7981_i2c0_0_pins[] = { 6, 7, }; +static int mt7981_i2c0_0_funcs[] = { 6, 6, }; + +static int mt7981_i2c0_1_pins[] = { 30, 31, }; +static int mt7981_i2c0_1_funcs[] = { 4, 4, }; + +static int mt7981_i2c0_2_pins[] = { 36, 37, }; +static int mt7981_i2c0_2_funcs[] = { 2, 2, }; + +static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; +static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; + +static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; +static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; + +static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; +static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; + +static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; +static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; + +/* DFD_NTRST */ +static int mt7981_dfd_ntrst_pins[] = { 8, }; +static int mt7981_dfd_ntrst_funcs[] = { 6, }; + +/* PWM0 */ +static int mt7981_pwm0_0_pins[] = { 13, }; +static int mt7981_pwm0_0_funcs[] = { 2, }; + +static int mt7981_pwm0_1_pins[] = { 15, }; +static int mt7981_pwm0_1_funcs[] = { 1, }; + +/* PWM1 */ +static int mt7981_pwm1_0_pins[] = { 14, }; +static int mt7981_pwm1_0_funcs[] = { 2, }; + +static int mt7981_pwm1_1_pins[] = { 15, }; +static int mt7981_pwm1_1_funcs[] = { 3, }; + +/* GBE_LED1 */ +static int mt7981_gbe_led1_pins[] = { 13, }; +static int mt7981_gbe_led1_funcs[] = { 3, }; + +/* PCM */ +static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; +static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; + +/* UDI */ +static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; +static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; + +/* DRV_VBUS */ +static int mt7981_drv_vbus_pins[] = { 14, }; +static int mt7981_drv_vbus_funcs[] = { 1, }; + +/* EMMC */ +static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; +static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +/* SNFI */ +static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; +static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + +/* SPI0 */ +static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; +static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; + +/* SPI0 */ +static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; +static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; + +/* SPI1 */ +static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; +static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; + +/* SPI2 */ +static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; +static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; + +/* SPI2 */ +static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; +static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; + +/* UART1 */ +static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; +static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; + +static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; +static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; + +/* UART2 */ +static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; +static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; + +/* UART0 */ +static int mt7981_uart0_pins[] = { 32, 33, }; +static int mt7981_uart0_funcs[] = { 1, 1, }; + +/* PCIE_CLK_REQ */ +static int mt7981_pcie_clk_pins[] = { 34, }; +static int mt7981_pcie_clk_funcs[] = { 2, }; + +/* PCIE_WAKE_N */ +static int mt7981_pcie_wake_pins[] = { 35, }; +static int mt7981_pcie_wake_funcs[] = { 2, }; + +/* MDC_MDIO */ +static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; +static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; + +static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; +static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; + +/* WF0_MODE1 */ +static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; +static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + +/* WF0_MODE3 */ +static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; +static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +/* WF2G_LED */ +static int mt7981_wf2g_led0_pins[] = { 30, }; +static int mt7981_wf2g_led0_funcs[] = { 2, }; + +static int mt7981_wf2g_led1_pins[] = { 34, }; +static int mt7981_wf2g_led1_funcs[] = { 1, }; + +/* WF5G_LED */ +static int mt7981_wf5g_led0_pins[] = { 31, }; +static int mt7981_wf5g_led0_funcs[] = { 2, }; + +static int mt7981_wf5g_led1_pins[] = { 35, }; +static int mt7981_wf5g_led1_funcs[] = { 1, }; + +/* MT7531_INT */ +static int mt7981_mt7531_int_pins[] = { 38, }; +static int mt7981_mt7531_int_funcs[] = { 1, }; + +/* ANT_SEL */ +static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; +static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; + +static const struct group_desc mt7981_groups[] = { + /* @GPIO(0,1): WA_AICE(2) */ + PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), + /* @GPIO(0,1): WA_AICE(3) */ + PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), + /* @GPIO(0,1): WM_UART(5) */ + PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), + /* @GPIO(0,1,4,5): DFD(6) */ + PINCTRL_PIN_GROUP("dfd", mt7981_dfd), + /* @GPIO(2): SYS_WATCHDOG(1) */ + PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), + /* @GPIO(3): PCIE_PERESET_N(1) */ + PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), + /* @GPIO(4,8) JTAG(1) */ + PINCTRL_PIN_GROUP("jtag", mt7981_jtag), + /* @GPIO(4,8) WM_JTAG(2) */ + PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), + /* @GPIO(9,13) WO0_JTAG(1) */ + PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), + /* @GPIO(4,7) WM_JTAG(3) */ + PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), + /* @GPIO(8) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), + /* @GPIO(4,6) PTA_EXT(4) */ + PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), + /* @GPIO(7) PWM2(4) */ + PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), + /* @GPIO(8) NET_WO0_UART_TXD(4) */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), + /* @GPIO(4,7) SPI1(5) */ + PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), + /* @GPIO(6,7) I2C(5) */ + PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), + /* @GPIO(0,1,4,5): DFD_NTRST(6) */ + PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), + /* @GPIO(9,10): WM_AICE(2) */ + PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), + /* @GPIO(13): PWM0(2) */ + PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), + /* @GPIO(15): PWM0(1) */ + PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), + /* @GPIO(14): PWM1(2) */ + PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), + /* @GPIO(15): PWM1(3) */ + PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), + /* @GPIO(14) NET_WO0_UART_TXD(3) */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), + /* @GPIO(15) NET_WO0_UART_TXD(4) */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), + /* @GPIO(13) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), + /* @GPIO(9,13) PCM(4) */ + PINCTRL_PIN_GROUP("pcm", mt7981_pcm), + /* @GPIO(13): SYS_WATCHDOG1(5) */ + PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), + /* @GPIO(9,13) UDI(4) */ + PINCTRL_PIN_GROUP("udi", mt7981_udi), + /* @GPIO(14) DRV_VBUS(1) */ + PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), + /* @GPIO(15,25): EMMC(2) */ + PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), + /* @GPIO(16,21): SNFI(3) */ + PINCTRL_PIN_GROUP("snfi", mt7981_snfi), + /* @GPIO(16,19): SPI0(1) */ + PINCTRL_PIN_GROUP("spi0", mt7981_spi0), + /* @GPIO(20,21): SPI0(1) */ + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), + /* @GPIO(22,25) SPI1(1) */ + PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), + /* @GPIO(26,29): SPI2(1) */ + PINCTRL_PIN_GROUP("spi2", mt7981_spi2), + /* @GPIO(30,31): SPI0(1) */ + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), + /* @GPIO(16,19): UART1(4) */ + PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), + /* @GPIO(26,29): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(22,25): UART1(3) */ + PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), + /* @GPIO(22,24) PTA_EXT(4) */ + PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), + /* @GPIO(20,21): WM_UART(4) */ + PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), + /* @GPIO(30,31): WM_UART(3) */ + PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), + /* @GPIO(20,24) WM_JTAG(5) */ + PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), + /* @GPIO(25,29) WO0_JTAG(5) */ + PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), + /* @GPIO(28,29): WA_AICE(3) */ + PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), + /* @GPIO(30,31): WM_AICE(5) */ + PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), + /* @GPIO(30,31): I2C(4) */ + PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), + /* @GPIO(30,31): I2C(6) */ + PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), + /* @GPIO(32,33): I2C(1) */ + PINCTRL_PIN_GROUP("uart0", mt7981_uart0), + /* @GPIO(32,33): I2C(2) */ + PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), + /* @GPIO(32,33): I2C(3) */ + PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), + /* @GPIO(32,33): I2C(5) */ + PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), + /* @GPIO(34): PCIE_CLK_REQ(2) */ + PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), + /* @GPIO(35): PCIE_WAKE_N(2) */ + PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), + /* @GPIO(36,37): I2C(2) */ + PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), + /* @GPIO(36,37): MDC_MDIO(1) */ + PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), + /* @GPIO(36,37): MDC_MDIO(3) */ + PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), + /* @GPIO(69,85): WF0_MODE1(1) */ + PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), + /* @GPIO(74,80): WF0_MODE3(3) */ + PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), + /* @GPIO(30): WF2G_LED(2) */ + PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), + /* @GPIO(34): WF2G_LED(1) */ + PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), + /* @GPIO(31): WF5G_LED(2) */ + PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), + /* @GPIO(35): WF5G_LED(1) */ + PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), + /* @GPIO(38): MT7531_INT(1) */ + PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), + /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ + PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", + "wa_aice3", "wm_aice1_2", }; +static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", + "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", + "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; +static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; +static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; +static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; +static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", + "wo0_jtag_1", "wm_jtag_1", }; +static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", + "wf2g_led1", "wf5g_led0", "wf5g_led1", }; +static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; +static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", + "pwm1_0", "pwm1_1", }; +static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", + "spi2_wp_hold", }; +static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", + "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; +static const char *mt7981_pcm_groups[] = { "pcm", }; +static const char *mt7981_udi_groups[] = { "udi", }; +static const char *mt7981_usb_groups[] = { "drv_vbus", }; +static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; +static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", + "wf0_mode1", "wf0_mode3", "mt7531_int", }; +static const char *mt7981_ant_groups[] = { "ant_sel", }; + +static const struct function_desc mt7981_functions[] = { + {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, + {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, + {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, + {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, + {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, + {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, + {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, + {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, + {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, + {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, + {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, + {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, + {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, + {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, + {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, + {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, + {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, +}; + +static const struct mtk_eint_hw mt7981_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7981_pins), + .db_cnt = 16, +}; + +static const char * const mt7981_pinctrl_register_base_names[] = { + "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", + "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", +}; + +static struct mtk_pin_soc mt7981_data = { + .reg_cal = mt7981_reg_cals, + .pins = mt7981_pins, + .npins = ARRAY_SIZE(mt7981_pins), + .grps = mt7981_groups, + .ngrps = ARRAY_SIZE(mt7981_groups), + .funcs = mt7981_functions, + .nfuncs = ARRAY_SIZE(mt7981_functions), + .eint_hw = &mt7981_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7981_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .pull_type = mt7981_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7981_pinctrl_of_match[] = { + { .compatible = "mediatek,mt7981-pinctrl", }, + {} +}; + +static int mt7981_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7981_data); +} + +static struct platform_driver mt7981_pinctrl_driver = { + .driver = { + .name = "mt7981-pinctrl", + .of_match_table = mt7981_pinctrl_of_match, + }, + .probe = mt7981_pinctrl_probe, +}; + +static int __init mt7981_pinctrl_init(void) +{ + return platform_driver_register(&mt7981_pinctrl_driver); +} +arch_initcall(mt7981_pinctrl_init); From d6e0a660097dcdb80e7c5c859eb12f776060b02e Mon Sep 17 00:00:00 2001 From: Jianlong Huang Date: Thu, 9 Feb 2023 22:36:59 +0800 Subject: [PATCH 114/118] dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl Add pinctrl bindings for StarFive JH7110 SoC sys pinctrl controller. Reviewed-by: Rob Herring Signed-off-by: Jianlong Huang Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Link: https://lore.kernel.org/r/20230209143702.44408-2-hal.feng@starfivetech.com Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jh7110-sys-pinctrl.yaml | 142 ++++++++++++++++++ MAINTAINERS | 6 +- .../pinctrl/starfive,jh7110-pinctrl.h | 115 ++++++++++++++ 3 files changed, 261 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file mode 100644 index 0000000000000..222b9e240f8af --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SYS Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals have their I/O go through the 64 "GPIOs". This also + includes a number of other UARTs, I2Cs, SPIs, PWMs etc. + All these peripherals are connected to all 64 GPIOs such that + any GPIO can be set up to be controlled by any of the peripherals. + +maintainers: + - Jianlong Huang + +properties: + compatible: + const: starfive,jh7110-sys-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX or PINMUX + macros. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x13040000 0x10000>; + clocks = <&syscrg 112>; + resets = <&syscrg 2>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + uart0-0 { + tx-pins { + pinmux = <0xff140005>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <0x0E000406>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415bd..babd133cdc4b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19890,13 +19890,15 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml F: drivers/clk/starfive/clk-starfive-jh7100* F: include/dt-bindings/clock/starfive-jh7100*.h -STARFIVE JH7100 PINCTRL DRIVER +STARFIVE JH71X0 PINCTRL DRIVERS M: Emil Renner Berthing +M: Jianlong Huang L: linux-gpio@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml F: drivers/pinctrl/starfive/ F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h +F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h STARFIVE JH7100 RESET CONTROLLER DRIVER M: Emil Renner Berthing diff --git a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h new file mode 100644 index 0000000000000..57c1659e4bbf0 --- /dev/null +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ + +/* sys_iomux pins */ +#define PAD_GPIO0 0 +#define PAD_GPIO1 1 +#define PAD_GPIO2 2 +#define PAD_GPIO3 3 +#define PAD_GPIO4 4 +#define PAD_GPIO5 5 +#define PAD_GPIO6 6 +#define PAD_GPIO7 7 +#define PAD_GPIO8 8 +#define PAD_GPIO9 9 +#define PAD_GPIO10 10 +#define PAD_GPIO11 11 +#define PAD_GPIO12 12 +#define PAD_GPIO13 13 +#define PAD_GPIO14 14 +#define PAD_GPIO15 15 +#define PAD_GPIO16 16 +#define PAD_GPIO17 17 +#define PAD_GPIO18 18 +#define PAD_GPIO19 19 +#define PAD_GPIO20 20 +#define PAD_GPIO21 21 +#define PAD_GPIO22 22 +#define PAD_GPIO23 23 +#define PAD_GPIO24 24 +#define PAD_GPIO25 25 +#define PAD_GPIO26 26 +#define PAD_GPIO27 27 +#define PAD_GPIO28 28 +#define PAD_GPIO29 29 +#define PAD_GPIO30 30 +#define PAD_GPIO31 31 +#define PAD_GPIO32 32 +#define PAD_GPIO33 33 +#define PAD_GPIO34 34 +#define PAD_GPIO35 35 +#define PAD_GPIO36 36 +#define PAD_GPIO37 37 +#define PAD_GPIO38 38 +#define PAD_GPIO39 39 +#define PAD_GPIO40 40 +#define PAD_GPIO41 41 +#define PAD_GPIO42 42 +#define PAD_GPIO43 43 +#define PAD_GPIO44 44 +#define PAD_GPIO45 45 +#define PAD_GPIO46 46 +#define PAD_GPIO47 47 +#define PAD_GPIO48 48 +#define PAD_GPIO49 49 +#define PAD_GPIO50 50 +#define PAD_GPIO51 51 +#define PAD_GPIO52 52 +#define PAD_GPIO53 53 +#define PAD_GPIO54 54 +#define PAD_GPIO55 55 +#define PAD_GPIO56 56 +#define PAD_GPIO57 57 +#define PAD_GPIO58 58 +#define PAD_GPIO59 59 +#define PAD_GPIO60 60 +#define PAD_GPIO61 61 +#define PAD_GPIO62 62 +#define PAD_GPIO63 63 +#define PAD_SD0_CLK 64 +#define PAD_SD0_CMD 65 +#define PAD_SD0_DATA0 66 +#define PAD_SD0_DATA1 67 +#define PAD_SD0_DATA2 68 +#define PAD_SD0_DATA3 69 +#define PAD_SD0_DATA4 70 +#define PAD_SD0_DATA5 71 +#define PAD_SD0_DATA6 72 +#define PAD_SD0_DATA7 73 +#define PAD_SD0_STRB 74 +#define PAD_GMAC1_MDC 75 +#define PAD_GMAC1_MDIO 76 +#define PAD_GMAC1_RXD0 77 +#define PAD_GMAC1_RXD1 78 +#define PAD_GMAC1_RXD2 79 +#define PAD_GMAC1_RXD3 80 +#define PAD_GMAC1_RXDV 81 +#define PAD_GMAC1_RXC 82 +#define PAD_GMAC1_TXD0 83 +#define PAD_GMAC1_TXD1 84 +#define PAD_GMAC1_TXD2 85 +#define PAD_GMAC1_TXD3 86 +#define PAD_GMAC1_TXEN 87 +#define PAD_GMAC1_TXC 88 +#define PAD_QSPI_SCLK 89 +#define PAD_QSPI_CS0 90 +#define PAD_QSPI_DATA0 91 +#define PAD_QSPI_DATA1 92 +#define PAD_QSPI_DATA2 93 +#define PAD_QSPI_DATA3 94 + +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 + +#define GPOEN_ENABLE 0 +#define GPOEN_DISABLE 1 + +#define GPI_NONE 255 + +#endif From 716129d3b76d060bdfbdfa6cec7091a9fe7729d2 Mon Sep 17 00:00:00 2001 From: Jianlong Huang Date: Thu, 9 Feb 2023 22:37:00 +0800 Subject: [PATCH 115/118] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller. Reviewed-by: Rob Herring Signed-off-by: Jianlong Huang Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Link: https://lore.kernel.org/r/20230209143702.44408-3-hal.feng@starfivetech.com Signed-off-by: Linus Walleij --- .../pinctrl/starfive,jh7110-aon-pinctrl.yaml | 124 ++++++++++++++++++ .../pinctrl/starfive,jh7110-pinctrl.h | 22 ++++ 2 files changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml new file mode 100644 index 0000000000000..b470901f5f562 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 AON Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals such as PWM have their I/O go through the 4 "GPIOs". + +maintainers: + - Jianlong Huang + +properties: + compatible: + const: starfive,jh7110-aon-pinctrl + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX macro. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x17020000 0x10000>; + resets = <&aoncrg 2>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + pwm-0 { + pwm-pins { + pinmux = <0xff030802>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h index 57c1659e4bbf0..3865f01396395 100644 --- a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h @@ -104,6 +104,28 @@ #define PAD_QSPI_DATA2 93 #define PAD_QSPI_DATA3 94 +/* aon_iomux pins */ +#define PAD_TESTEN 0 +#define PAD_RGPIO0 1 +#define PAD_RGPIO1 2 +#define PAD_RGPIO2 3 +#define PAD_RGPIO3 4 +#define PAD_RSTN 5 +#define PAD_GMAC0_MDC 6 +#define PAD_GMAC0_MDIO 7 +#define PAD_GMAC0_RXD0 8 +#define PAD_GMAC0_RXD1 9 +#define PAD_GMAC0_RXD2 10 +#define PAD_GMAC0_RXD3 11 +#define PAD_GMAC0_RXDV 12 +#define PAD_GMAC0_RXC 13 +#define PAD_GMAC0_TXD0 14 +#define PAD_GMAC0_TXD1 15 +#define PAD_GMAC0_TXD2 16 +#define PAD_GMAC0_TXD3 17 +#define PAD_GMAC0_TXEN 18 +#define PAD_GMAC0_TXC 19 + #define GPOUT_LOW 0 #define GPOUT_HIGH 1 From 447976ab62c5dd6016f06a2f24798407398b5c07 Mon Sep 17 00:00:00 2001 From: Jianlong Huang Date: Thu, 9 Feb 2023 22:37:01 +0800 Subject: [PATCH 116/118] pinctrl: starfive: Add StarFive JH7110 sys controller driver Add pinctrl driver for StarFive JH7110 SoC sys pinctrl controller. Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng Link: https://lore.kernel.org/r/20230209143702.44408-4-hal.feng@starfivetech.com Signed-off-by: Linus Walleij --- MAINTAINERS | 2 +- drivers/pinctrl/starfive/Kconfig | 21 + drivers/pinctrl/starfive/Makefile | 3 + .../starfive/pinctrl-starfive-jh7110-sys.c | 449 ++++++++ .../starfive/pinctrl-starfive-jh7110.c | 982 ++++++++++++++++++ .../starfive/pinctrl-starfive-jh7110.h | 70 ++ 6 files changed, 1526 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h diff --git a/MAINTAINERS b/MAINTAINERS index babd133cdc4b2..8a851eb053ca5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19896,7 +19896,7 @@ M: Jianlong Huang L: linux-gpio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml -F: drivers/pinctrl/starfive/ +F: drivers/pinctrl/starfive/pinctrl-starfive-jh71* F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 55c514e622f91..453c8a0b3118c 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -16,3 +16,24 @@ config PINCTRL_STARFIVE_JH7100 This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH7110 + bool + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + +config PINCTRL_STARFIVE_JH7110_SYS + tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC" + depends on SOC_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH7110 + default SOC_STARFIVE + help + Say yes here to support system pin control on the StarFive JH7110 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 0293f26a0a993..dc2d1e3923148 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o + +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c new file mode 100644 index 0000000000000..bc279a39613fc --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller + * + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" +#include "../pinconf.h" +#include "pinctrl-starfive-jh7110.h" + +#define JH7110_SYS_NGPIO 64 +#define JH7110_SYS_GC_BASE 0 + +/* registers */ +#define JH7110_SYS_DOEN 0x000 +#define JH7110_SYS_DOUT 0x040 +#define JH7110_SYS_GPI 0x080 +#define JH7110_SYS_GPIOIN 0x118 + +#define JH7110_SYS_GPIOEN 0x0dc +#define JH7110_SYS_GPIOIS0 0x0e0 +#define JH7110_SYS_GPIOIS1 0x0e4 +#define JH7110_SYS_GPIOIC0 0x0e8 +#define JH7110_SYS_GPIOIC1 0x0ec +#define JH7110_SYS_GPIOIBE0 0x0f0 +#define JH7110_SYS_GPIOIBE1 0x0f4 +#define JH7110_SYS_GPIOIEV0 0x0f8 +#define JH7110_SYS_GPIOIEV1 0x0fc +#define JH7110_SYS_GPIOIE0 0x100 +#define JH7110_SYS_GPIOIE1 0x104 +#define JH7110_SYS_GPIORIS0 0x108 +#define JH7110_SYS_GPIORIS1 0x10c +#define JH7110_SYS_GPIOMIS0 0x110 +#define JH7110_SYS_GPIOMIS1 0x114 + +#define JH7110_SYS_GPO_PDA_0_74_CFG 0x120 +#define JH7110_SYS_GPO_PDA_89_94_CFG 0x284 + +static const struct pinctrl_pin_desc jh7110_sys_pins[] = { + PINCTRL_PIN(PAD_GPIO0, "GPIO0"), + PINCTRL_PIN(PAD_GPIO1, "GPIO1"), + PINCTRL_PIN(PAD_GPIO2, "GPIO2"), + PINCTRL_PIN(PAD_GPIO3, "GPIO3"), + PINCTRL_PIN(PAD_GPIO4, "GPIO4"), + PINCTRL_PIN(PAD_GPIO5, "GPIO5"), + PINCTRL_PIN(PAD_GPIO6, "GPIO6"), + PINCTRL_PIN(PAD_GPIO7, "GPIO7"), + PINCTRL_PIN(PAD_GPIO8, "GPIO8"), + PINCTRL_PIN(PAD_GPIO9, "GPIO9"), + PINCTRL_PIN(PAD_GPIO10, "GPIO10"), + PINCTRL_PIN(PAD_GPIO11, "GPIO11"), + PINCTRL_PIN(PAD_GPIO12, "GPIO12"), + PINCTRL_PIN(PAD_GPIO13, "GPIO13"), + PINCTRL_PIN(PAD_GPIO14, "GPIO14"), + PINCTRL_PIN(PAD_GPIO15, "GPIO15"), + PINCTRL_PIN(PAD_GPIO16, "GPIO16"), + PINCTRL_PIN(PAD_GPIO17, "GPIO17"), + PINCTRL_PIN(PAD_GPIO18, "GPIO18"), + PINCTRL_PIN(PAD_GPIO19, "GPIO19"), + PINCTRL_PIN(PAD_GPIO20, "GPIO20"), + PINCTRL_PIN(PAD_GPIO21, "GPIO21"), + PINCTRL_PIN(PAD_GPIO22, "GPIO22"), + PINCTRL_PIN(PAD_GPIO23, "GPIO23"), + PINCTRL_PIN(PAD_GPIO24, "GPIO24"), + PINCTRL_PIN(PAD_GPIO25, "GPIO25"), + PINCTRL_PIN(PAD_GPIO26, "GPIO26"), + PINCTRL_PIN(PAD_GPIO27, "GPIO27"), + PINCTRL_PIN(PAD_GPIO28, "GPIO28"), + PINCTRL_PIN(PAD_GPIO29, "GPIO29"), + PINCTRL_PIN(PAD_GPIO30, "GPIO30"), + PINCTRL_PIN(PAD_GPIO31, "GPIO31"), + PINCTRL_PIN(PAD_GPIO32, "GPIO32"), + PINCTRL_PIN(PAD_GPIO33, "GPIO33"), + PINCTRL_PIN(PAD_GPIO34, "GPIO34"), + PINCTRL_PIN(PAD_GPIO35, "GPIO35"), + PINCTRL_PIN(PAD_GPIO36, "GPIO36"), + PINCTRL_PIN(PAD_GPIO37, "GPIO37"), + PINCTRL_PIN(PAD_GPIO38, "GPIO38"), + PINCTRL_PIN(PAD_GPIO39, "GPIO39"), + PINCTRL_PIN(PAD_GPIO40, "GPIO40"), + PINCTRL_PIN(PAD_GPIO41, "GPIO41"), + PINCTRL_PIN(PAD_GPIO42, "GPIO42"), + PINCTRL_PIN(PAD_GPIO43, "GPIO43"), + PINCTRL_PIN(PAD_GPIO44, "GPIO44"), + PINCTRL_PIN(PAD_GPIO45, "GPIO45"), + PINCTRL_PIN(PAD_GPIO46, "GPIO46"), + PINCTRL_PIN(PAD_GPIO47, "GPIO47"), + PINCTRL_PIN(PAD_GPIO48, "GPIO48"), + PINCTRL_PIN(PAD_GPIO49, "GPIO49"), + PINCTRL_PIN(PAD_GPIO50, "GPIO50"), + PINCTRL_PIN(PAD_GPIO51, "GPIO51"), + PINCTRL_PIN(PAD_GPIO52, "GPIO52"), + PINCTRL_PIN(PAD_GPIO53, "GPIO53"), + PINCTRL_PIN(PAD_GPIO54, "GPIO54"), + PINCTRL_PIN(PAD_GPIO55, "GPIO55"), + PINCTRL_PIN(PAD_GPIO56, "GPIO56"), + PINCTRL_PIN(PAD_GPIO57, "GPIO57"), + PINCTRL_PIN(PAD_GPIO58, "GPIO58"), + PINCTRL_PIN(PAD_GPIO59, "GPIO59"), + PINCTRL_PIN(PAD_GPIO60, "GPIO60"), + PINCTRL_PIN(PAD_GPIO61, "GPIO61"), + PINCTRL_PIN(PAD_GPIO62, "GPIO62"), + PINCTRL_PIN(PAD_GPIO63, "GPIO63"), + PINCTRL_PIN(PAD_SD0_CLK, "SD0_CLK"), + PINCTRL_PIN(PAD_SD0_CMD, "SD0_CMD"), + PINCTRL_PIN(PAD_SD0_DATA0, "SD0_DATA0"), + PINCTRL_PIN(PAD_SD0_DATA1, "SD0_DATA1"), + PINCTRL_PIN(PAD_SD0_DATA2, "SD0_DATA2"), + PINCTRL_PIN(PAD_SD0_DATA3, "SD0_DATA3"), + PINCTRL_PIN(PAD_SD0_DATA4, "SD0_DATA4"), + PINCTRL_PIN(PAD_SD0_DATA5, "SD0_DATA5"), + PINCTRL_PIN(PAD_SD0_DATA6, "SD0_DATA6"), + PINCTRL_PIN(PAD_SD0_DATA7, "SD0_DATA7"), + PINCTRL_PIN(PAD_SD0_STRB, "SD0_STRB"), + PINCTRL_PIN(PAD_GMAC1_MDC, "GMAC1_MDC"), + PINCTRL_PIN(PAD_GMAC1_MDIO, "GMAC1_MDIO"), + PINCTRL_PIN(PAD_GMAC1_RXD0, "GMAC1_RXD0"), + PINCTRL_PIN(PAD_GMAC1_RXD1, "GMAC1_RXD1"), + PINCTRL_PIN(PAD_GMAC1_RXD2, "GMAC1_RXD2"), + PINCTRL_PIN(PAD_GMAC1_RXD3, "GMAC1_RXD3"), + PINCTRL_PIN(PAD_GMAC1_RXDV, "GMAC1_RXDV"), + PINCTRL_PIN(PAD_GMAC1_RXC, "GMAC1_RXC"), + PINCTRL_PIN(PAD_GMAC1_TXD0, "GMAC1_TXD0"), + PINCTRL_PIN(PAD_GMAC1_TXD1, "GMAC1_TXD1"), + PINCTRL_PIN(PAD_GMAC1_TXD2, "GMAC1_TXD2"), + PINCTRL_PIN(PAD_GMAC1_TXD3, "GMAC1_TXD3"), + PINCTRL_PIN(PAD_GMAC1_TXEN, "GMAC1_TXEN"), + PINCTRL_PIN(PAD_GMAC1_TXC, "GMAC1_TXC"), + PINCTRL_PIN(PAD_QSPI_SCLK, "QSPI_SCLK"), + PINCTRL_PIN(PAD_QSPI_CS0, "QSPI_CS0"), + PINCTRL_PIN(PAD_QSPI_DATA0, "QSPI_DATA0"), + PINCTRL_PIN(PAD_QSPI_DATA1, "QSPI_DATA1"), + PINCTRL_PIN(PAD_QSPI_DATA2, "QSPI_DATA2"), + PINCTRL_PIN(PAD_QSPI_DATA3, "QSPI_DATA3"), +}; + +struct jh7110_func_sel { + u16 offset; + u8 shift; + u8 max; +}; + +static const struct jh7110_func_sel + jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = { + [PAD_GMAC1_RXC] = { 0x29c, 0, 1 }, + [PAD_GPIO10] = { 0x29c, 2, 3 }, + [PAD_GPIO11] = { 0x29c, 5, 3 }, + [PAD_GPIO12] = { 0x29c, 8, 3 }, + [PAD_GPIO13] = { 0x29c, 11, 3 }, + [PAD_GPIO14] = { 0x29c, 14, 3 }, + [PAD_GPIO15] = { 0x29c, 17, 3 }, + [PAD_GPIO16] = { 0x29c, 20, 3 }, + [PAD_GPIO17] = { 0x29c, 23, 3 }, + [PAD_GPIO18] = { 0x29c, 26, 3 }, + [PAD_GPIO19] = { 0x29c, 29, 3 }, + + [PAD_GPIO20] = { 0x2a0, 0, 3 }, + [PAD_GPIO21] = { 0x2a0, 3, 3 }, + [PAD_GPIO22] = { 0x2a0, 6, 3 }, + [PAD_GPIO23] = { 0x2a0, 9, 3 }, + [PAD_GPIO24] = { 0x2a0, 12, 3 }, + [PAD_GPIO25] = { 0x2a0, 15, 3 }, + [PAD_GPIO26] = { 0x2a0, 18, 3 }, + [PAD_GPIO27] = { 0x2a0, 21, 3 }, + [PAD_GPIO28] = { 0x2a0, 24, 3 }, + [PAD_GPIO29] = { 0x2a0, 27, 3 }, + + [PAD_GPIO30] = { 0x2a4, 0, 3 }, + [PAD_GPIO31] = { 0x2a4, 3, 3 }, + [PAD_GPIO32] = { 0x2a4, 6, 3 }, + [PAD_GPIO33] = { 0x2a4, 9, 3 }, + [PAD_GPIO34] = { 0x2a4, 12, 3 }, + [PAD_GPIO35] = { 0x2a4, 15, 3 }, + [PAD_GPIO36] = { 0x2a4, 17, 3 }, + [PAD_GPIO37] = { 0x2a4, 20, 3 }, + [PAD_GPIO38] = { 0x2a4, 23, 3 }, + [PAD_GPIO39] = { 0x2a4, 26, 3 }, + [PAD_GPIO40] = { 0x2a4, 29, 3 }, + + [PAD_GPIO41] = { 0x2a8, 0, 3 }, + [PAD_GPIO42] = { 0x2a8, 3, 3 }, + [PAD_GPIO43] = { 0x2a8, 6, 3 }, + [PAD_GPIO44] = { 0x2a8, 9, 3 }, + [PAD_GPIO45] = { 0x2a8, 12, 3 }, + [PAD_GPIO46] = { 0x2a8, 15, 3 }, + [PAD_GPIO47] = { 0x2a8, 18, 3 }, + [PAD_GPIO48] = { 0x2a8, 21, 3 }, + [PAD_GPIO49] = { 0x2a8, 24, 3 }, + [PAD_GPIO50] = { 0x2a8, 27, 3 }, + [PAD_GPIO51] = { 0x2a8, 30, 3 }, + + [PAD_GPIO52] = { 0x2ac, 0, 3 }, + [PAD_GPIO53] = { 0x2ac, 2, 3 }, + [PAD_GPIO54] = { 0x2ac, 4, 3 }, + [PAD_GPIO55] = { 0x2ac, 6, 3 }, + [PAD_GPIO56] = { 0x2ac, 9, 3 }, + [PAD_GPIO57] = { 0x2ac, 12, 3 }, + [PAD_GPIO58] = { 0x2ac, 15, 3 }, + [PAD_GPIO59] = { 0x2ac, 18, 3 }, + [PAD_GPIO60] = { 0x2ac, 21, 3 }, + [PAD_GPIO61] = { 0x2ac, 24, 3 }, + [PAD_GPIO62] = { 0x2ac, 27, 3 }, + [PAD_GPIO63] = { 0x2ac, 30, 3 }, + + [PAD_GPIO6] = { 0x2b0, 0, 3 }, + [PAD_GPIO7] = { 0x2b0, 2, 3 }, + [PAD_GPIO8] = { 0x2b0, 5, 3 }, + [PAD_GPIO9] = { 0x2b0, 8, 3 }, +}; + +struct jh7110_vin_group_sel { + u16 offset; + u8 shift; + u8 group; +}; + +static const struct jh7110_vin_group_sel + jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = { + [PAD_GPIO6] = { 0x2b4, 21, 0 }, + [PAD_GPIO7] = { 0x2b4, 18, 0 }, + [PAD_GPIO8] = { 0x2b4, 15, 0 }, + [PAD_GPIO9] = { 0x2b0, 11, 0 }, + [PAD_GPIO10] = { 0x2b0, 20, 0 }, + [PAD_GPIO11] = { 0x2b0, 23, 0 }, + [PAD_GPIO12] = { 0x2b0, 26, 0 }, + [PAD_GPIO13] = { 0x2b0, 29, 0 }, + [PAD_GPIO14] = { 0x2b4, 0, 0 }, + [PAD_GPIO15] = { 0x2b4, 3, 0 }, + [PAD_GPIO16] = { 0x2b4, 6, 0 }, + [PAD_GPIO17] = { 0x2b4, 9, 0 }, + [PAD_GPIO18] = { 0x2b4, 12, 0 }, + [PAD_GPIO19] = { 0x2b0, 14, 0 }, + [PAD_GPIO20] = { 0x2b0, 17, 0 }, + + [PAD_GPIO21] = { 0x2b4, 21, 1 }, + [PAD_GPIO22] = { 0x2b4, 18, 1 }, + [PAD_GPIO23] = { 0x2b4, 15, 1 }, + [PAD_GPIO24] = { 0x2b0, 11, 1 }, + [PAD_GPIO25] = { 0x2b0, 20, 1 }, + [PAD_GPIO26] = { 0x2b0, 23, 1 }, + [PAD_GPIO27] = { 0x2b0, 26, 1 }, + [PAD_GPIO28] = { 0x2b0, 29, 1 }, + [PAD_GPIO29] = { 0x2b4, 0, 1 }, + [PAD_GPIO30] = { 0x2b4, 3, 1 }, + [PAD_GPIO31] = { 0x2b4, 6, 1 }, + [PAD_GPIO32] = { 0x2b4, 9, 1 }, + [PAD_GPIO33] = { 0x2b4, 12, 1 }, + [PAD_GPIO34] = { 0x2b0, 14, 1 }, + [PAD_GPIO35] = { 0x2b0, 17, 1 }, + + [PAD_GPIO36] = { 0x2b4, 21, 2 }, + [PAD_GPIO37] = { 0x2b4, 18, 2 }, + [PAD_GPIO38] = { 0x2b4, 15, 2 }, + [PAD_GPIO39] = { 0x2b0, 11, 2 }, + [PAD_GPIO40] = { 0x2b0, 20, 2 }, + [PAD_GPIO41] = { 0x2b0, 23, 2 }, + [PAD_GPIO42] = { 0x2b0, 26, 2 }, + [PAD_GPIO43] = { 0x2b0, 29, 2 }, + [PAD_GPIO44] = { 0x2b4, 0, 2 }, + [PAD_GPIO45] = { 0x2b4, 3, 2 }, + [PAD_GPIO46] = { 0x2b4, 6, 2 }, + [PAD_GPIO47] = { 0x2b4, 9, 2 }, + [PAD_GPIO48] = { 0x2b4, 12, 2 }, + [PAD_GPIO49] = { 0x2b0, 14, 2 }, + [PAD_GPIO50] = { 0x2b0, 17, 2 }, +}; + +static void jh7110_set_function(struct jh7110_pinctrl *sfp, + unsigned int pin, u32 func) +{ + const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin]; + unsigned long flags; + void __iomem *reg; + u32 mask; + + if (!fs->offset) + return; + + if (func > fs->max) + return; + + reg = sfp->base + fs->offset; + func = func << fs->shift; + mask = 0x3U << fs->shift; + + raw_spin_lock_irqsave(&sfp->lock, flags); + func |= readl_relaxed(reg) & ~mask; + writel_relaxed(func, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp, + unsigned int pin) +{ + const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin]; + unsigned long flags; + void __iomem *reg; + u32 mask; + u32 grp; + + if (!gs->offset) + return; + + reg = sfp->base + gs->offset; + grp = gs->group << gs->shift; + mask = 0x3U << gs->shift; + + raw_spin_lock_irqsave(&sfp->lock, flags); + grp |= readl_relaxed(reg) & ~mask; + writel_relaxed(grp, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp, + unsigned int pin, + unsigned int din, u32 dout, + u32 doen, u32 func) +{ + if (pin < sfp->gc.ngpio && func == 0) + jh7110_set_gpiomux(sfp, pin, din, dout, doen); + + jh7110_set_function(sfp, pin, func); + + if (pin < sfp->gc.ngpio && func == 2) + jh7110_set_vin_group(sfp, pin); + + return 0; +} + +static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp, + unsigned int pin) +{ + if (pin < PAD_GMAC1_MDC) + return JH7110_SYS_GPO_PDA_0_74_CFG; + else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3) + return JH7110_SYS_GPO_PDA_89_94_CFG; + else + return -1; +} + +static void jh7110_sys_irq_handler(struct irq_desc *desc) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long mis; + unsigned int pin; + + chained_irq_enter(chip, desc); + + mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0); + for_each_set_bit(pin, &mis, 32) + generic_handle_domain_irq(sfp->gc.irq.domain, pin); + + mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1); + for_each_set_bit(pin, &mis, 32) + generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); + + chained_irq_exit(chip, desc); +} + +static int jh7110_sys_init_hw(struct gpio_chip *gc) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + + /* mask all GPIO interrupts */ + writel(0U, sfp->base + JH7110_SYS_GPIOIE0); + writel(0U, sfp->base + JH7110_SYS_GPIOIE1); + /* clear edge interrupt flags */ + writel(~0U, sfp->base + JH7110_SYS_GPIOIC0); + writel(~0U, sfp->base + JH7110_SYS_GPIOIC1); + /* enable GPIO interrupts */ + writel(1U, sfp->base + JH7110_SYS_GPIOEN); + return 0; +} + +static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = { + .is_reg_base = JH7110_SYS_GPIOIS0, + .ic_reg_base = JH7110_SYS_GPIOIC0, + .ibe_reg_base = JH7110_SYS_GPIOIBE0, + .iev_reg_base = JH7110_SYS_GPIOIEV0, + .ie_reg_base = JH7110_SYS_GPIOIE0, + .ris_reg_base = JH7110_SYS_GPIORIS0, + .mis_reg_base = JH7110_SYS_GPIOMIS0, +}; + +static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = { + .pins = jh7110_sys_pins, + .npins = ARRAY_SIZE(jh7110_sys_pins), + .ngpios = JH7110_SYS_NGPIO, + .gc_base = JH7110_SYS_GC_BASE, + .dout_reg_base = JH7110_SYS_DOUT, + .dout_mask = GENMASK(6, 0), + .doen_reg_base = JH7110_SYS_DOEN, + .doen_mask = GENMASK(5, 0), + .gpi_reg_base = JH7110_SYS_GPI, + .gpi_mask = GENMASK(6, 0), + .gpioin_reg_base = JH7110_SYS_GPIOIN, + .irq_reg = &jh7110_sys_irq_reg, + .jh7110_set_one_pin_mux = jh7110_sys_set_one_pin_mux, + .jh7110_get_padcfg_base = jh7110_sys_get_padcfg_base, + .jh7110_gpio_irq_handler = jh7110_sys_irq_handler, + .jh7110_gpio_init_hw = jh7110_sys_init_hw, +}; + +static const struct of_device_id jh7110_sys_pinctrl_of_match[] = { + { + .compatible = "starfive,jh7110-sys-pinctrl", + .data = &jh7110_sys_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match); + +static struct platform_driver jh7110_sys_pinctrl_driver = { + .probe = jh7110_pinctrl_probe, + .driver = { + .name = "starfive-jh7110-sys-pinctrl", + .of_match_table = jh7110_sys_pinctrl_of_match, + }, +}; +module_platform_driver(jh7110_sys_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller"); +MODULE_AUTHOR("Emil Renner Berthing "); +MODULE_AUTHOR("Jianlong Huang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c new file mode 100644 index 0000000000000..5fe729b4a03de --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c @@ -0,0 +1,982 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC + * + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" +#include "../pinconf.h" +#include "pinctrl-starfive-jh7110.h" + +/* pad control bits */ +#define JH7110_PADCFG_POS BIT(7) +#define JH7110_PADCFG_SMT BIT(6) +#define JH7110_PADCFG_SLEW BIT(5) +#define JH7110_PADCFG_PD BIT(4) +#define JH7110_PADCFG_PU BIT(3) +#define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU) +#define JH7110_PADCFG_DS_MASK GENMASK(2, 1) +#define JH7110_PADCFG_DS_2MA (0U << 1) +#define JH7110_PADCFG_DS_4MA BIT(1) +#define JH7110_PADCFG_DS_8MA (2U << 1) +#define JH7110_PADCFG_DS_12MA (3U << 1) +#define JH7110_PADCFG_IE BIT(0) + +/* + * The packed pinmux values from the device tree look like this: + * + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | pin | + */ +static unsigned int jh7110_pinmux_din(u32 v) +{ + return (v & GENMASK(31, 24)) >> 24; +} + +static u32 jh7110_pinmux_dout(u32 v) +{ + return (v & GENMASK(23, 16)) >> 16; +} + +static u32 jh7110_pinmux_doen(u32 v) +{ + return (v & GENMASK(15, 10)) >> 10; +} + +static u32 jh7110_pinmux_function(u32 v) +{ + return (v & GENMASK(9, 8)) >> 8; +} + +static unsigned int jh7110_pinmux_pin(u32 v) +{ + return v & GENMASK(7, 0); +} + +static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + return container_of(gc, struct jh7110_pinctrl, gc); +} + +struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + + return container_of(gc, struct jh7110_pinctrl, gc); +} +EXPORT_SYMBOL_GPL(jh7110_from_irq_desc); + +#ifdef CONFIG_DEBUG_FS +static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + + seq_printf(s, "%s", dev_name(pctldev->dev)); + + if (pin < sfp->gc.ngpio) { + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); + u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset); + + dout = (dout >> shift) & info->dout_mask; + doen = (doen >> shift) & info->doen_mask; + gpi = ((gpi >> shift) - 2) & info->gpi_mask; + + seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi); + } +} +#else +#define jh7110_pin_dbg_show NULL +#endif + +static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = sfp->gc.parent; + struct device_node *child; + struct pinctrl_map *map; + const char **pgnames; + const char *grpname; + int ngroups; + int nmaps; + int ret; + + ngroups = 0; + for_each_child_of_node(np, child) + ngroups += 1; + nmaps = 2 * ngroups; + + pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL); + if (!pgnames) + return -ENOMEM; + + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps = 0; + ngroups = 0; + mutex_lock(&sfp->mutex); + for_each_child_of_node(np, child) { + int npins = of_property_count_u32_elems(child, "pinmux"); + int *pins; + u32 *pinmux; + int i; + + if (npins < 1) { + dev_err(dev, + "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n", + np, child); + ret = -EINVAL; + goto put_child; + } + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child); + if (!grpname) { + ret = -ENOMEM; + goto put_child; + } + + pgnames[ngroups++] = grpname; + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto put_child; + } + + pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL); + if (!pinmux) { + ret = -ENOMEM; + goto put_child; + } + + ret = of_property_read_u32_array(child, "pinmux", pinmux, npins); + if (ret) + goto put_child; + + for (i = 0; i < npins; i++) + pins[i] = jh7110_pinmux_pin(pinmux[i]); + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + + ret = pinctrl_generic_add_group(pctldev, grpname, + pins, npins, pinmux); + if (ret < 0) { + dev_err(dev, "error adding group %s: %d\n", grpname, ret); + goto put_child; + } + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) { + dev_err(dev, "error parsing pin config of group %s: %d\n", + grpname, ret); + goto put_child; + } + + /* don't create a map if there are no pinconf settings */ + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, + pgnames, ngroups, NULL); + if (ret < 0) { + dev_err(dev, "error adding function %s: %d\n", np->name, ret); + goto free_map; + } + mutex_unlock(&sfp->mutex); + + *maps = map; + *num_maps = nmaps; + return 0; + +put_child: + of_node_put(child); +free_map: + pinctrl_utils_free_map(pctldev, map, nmaps); + mutex_unlock(&sfp->mutex); + return ret; +} + +static const struct pinctrl_ops jh7110_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = jh7110_pin_dbg_show, + .dt_node_to_map = jh7110_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, + unsigned int din, u32 dout, u32 doen) +{ + const struct jh7110_pinctrl_soc_info *info = sfp->info; + + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout_mask = info->dout_mask << shift; + u32 done_mask = info->doen_mask << shift; + u32 ival, imask; + void __iomem *reg_dout; + void __iomem *reg_doen; + void __iomem *reg_din; + unsigned long flags; + + reg_dout = sfp->base + info->dout_reg_base + offset; + reg_doen = sfp->base + info->doen_reg_base + offset; + dout <<= shift; + doen <<= shift; + if (din != GPI_NONE) { + unsigned int ioffset = 4 * (din / 4); + unsigned int ishift = 8 * (din % 4); + + reg_din = sfp->base + info->gpi_reg_base + ioffset; + ival = (pin + 2) << ishift; + imask = info->gpi_mask << ishift; + } else { + reg_din = NULL; + } + + raw_spin_lock_irqsave(&sfp->lock, flags); + dout |= readl_relaxed(reg_dout) & ~dout_mask; + writel_relaxed(dout, reg_dout); + doen |= readl_relaxed(reg_doen) & ~done_mask; + writel_relaxed(doen, reg_doen); + if (reg_din) { + ival |= readl_relaxed(reg_din) & ~imask; + writel_relaxed(ival, reg_din); + } + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} +EXPORT_SYMBOL_GPL(jh7110_set_gpiomux); + +static int jh7110_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + const struct group_desc *group; + const u32 *pinmux; + unsigned int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + pinmux = group->data; + for (i = 0; i < group->num_pins; i++) { + u32 v = pinmux[i]; + + if (info->jh7110_set_one_pin_mux) + info->jh7110_set_one_pin_mux(sfp, + jh7110_pinmux_pin(v), + jh7110_pinmux_din(v), + jh7110_pinmux_dout(v), + jh7110_pinmux_doen(v), + jh7110_pinmux_function(v)); + } + + return 0; +} + +static const struct pinmux_ops jh7110_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = jh7110_set_mux, + .strict = true, +}; + +static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 }; + +static u32 jh7110_padcfg_ds_to_mA(u32 padcfg) +{ + return jh7110_drive_strength_mA[(padcfg >> 1) & 3U]; +} + +static u32 jh7110_padcfg_ds_from_mA(u32 v) +{ + int i; + + for (i = 0; i < 3; i++) { + if (v <= jh7110_drive_strength_mA[i]) + break; + } + return i << 1; +} + +static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp, + unsigned int pin, u32 mask, u32 value) +{ + const struct jh7110_pinctrl_soc_info *info = sfp->info; + void __iomem *reg; + unsigned long flags; + int padcfg_base; + + if (!info->jh7110_get_padcfg_base) + return; + + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return; + + reg = sfp->base + padcfg_base + 4 * pin; + value &= mask; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value |= readl_relaxed(reg) & ~mask; + writel_relaxed(value, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh7110_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + int param = pinconf_to_config_param(*config); + u32 padcfg, arg; + bool enabled; + int padcfg_base; + + if (!info->jh7110_get_padcfg_base) + return 0; + + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return 0; + + padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled = !(padcfg & JH7110_PADCFG_BIAS); + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled = padcfg & JH7110_PADCFG_PD; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + enabled = padcfg & JH7110_PADCFG_PU; + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled = true; + arg = jh7110_padcfg_ds_to_mA(padcfg); + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled = padcfg & JH7110_PADCFG_IE; + arg = enabled; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled = padcfg & JH7110_PADCFG_SMT; + arg = enabled; + break; + case PIN_CONFIG_SLEW_RATE: + enabled = true; + arg = !!(padcfg & JH7110_PADCFG_SLEW); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *config) +{ + const struct group_desc *group; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + return jh7110_pinconf_get(pctldev, group->pins[0], config); +} + +static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + u16 mask, value; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + mask = 0; + value = 0; + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= JH7110_PADCFG_BIAS; + value &= ~JH7110_PADCFG_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask |= JH7110_PADCFG_BIAS; + value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask |= JH7110_PADCFG_BIAS; + value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= JH7110_PADCFG_DS_MASK; + value = (value & ~JH7110_PADCFG_DS_MASK) | + jh7110_padcfg_ds_from_mA(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= JH7110_PADCFG_IE; + if (arg) + value |= JH7110_PADCFG_IE; + else + value &= ~JH7110_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= JH7110_PADCFG_SMT; + if (arg) + value |= JH7110_PADCFG_SMT; + else + value &= ~JH7110_PADCFG_SMT; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= JH7110_PADCFG_SLEW; + if (arg) + value |= JH7110_PADCFG_SLEW; + else + value &= ~JH7110_PADCFG_SLEW; + break; + default: + return -ENOTSUPP; + } + } + + for (i = 0; i < group->num_pins; i++) + jh7110_padcfg_rmw(sfp, group->pins[i], mask, value); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + u32 value; + int padcfg_base; + + if (!info->jh7110_get_padcfg_base) + return; + + padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return; + + value = readl_relaxed(sfp->base + padcfg_base + 4 * pin); + seq_printf(s, " (0x%02x)", value); +} +#else +#define jh7110_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops jh7110_pinconf_ops = { + .pin_config_get = jh7110_pinconf_get, + .pin_config_group_get = jh7110_pinconf_group_get, + .pin_config_group_set = jh7110_pinconf_group_set, + .pin_config_dbg_show = jh7110_pinconf_dbg_show, + .is_generic = true, +}; + +static int jh7110_gpio_request(struct gpio_chip *gc, unsigned int gpio) +{ + return pinctrl_gpio_request(gc->base + gpio); +} + +static void jh7110_gpio_free(struct gpio_chip *gc, unsigned int gpio) +{ + pinctrl_gpio_free(gc->base + gpio); +} + +static int jh7110_gpio_get_direction(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + unsigned int offset = 4 * (gpio / 4); + unsigned int shift = 8 * (gpio % 4); + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); + + doen = (doen >> shift) & info->doen_mask; + + return doen == GPOEN_ENABLE ? + GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int jh7110_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + + /* enable input and schmitt trigger */ + jh7110_padcfg_rmw(sfp, gpio, + JH7110_PADCFG_IE | JH7110_PADCFG_SMT, + JH7110_PADCFG_IE | JH7110_PADCFG_SMT); + + if (info->jh7110_set_one_pin_mux) + info->jh7110_set_one_pin_mux(sfp, gpio, + GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0); + + return 0; +} + +static int jh7110_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + + if (info->jh7110_set_one_pin_mux) + info->jh7110_set_one_pin_mux(sfp, gpio, + GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW, + GPOEN_ENABLE, 0); + + /* disable input, schmitt trigger and bias */ + jh7110_padcfg_rmw(sfp, gpio, + JH7110_PADCFG_IE | JH7110_PADCFG_SMT | + JH7110_PADCFG_BIAS, 0); + return 0; +} + +static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + void __iomem *reg = sfp->base + info->gpioin_reg_base + + 4 * (gpio / 32); + + return !!(readl_relaxed(reg) & BIT(gpio % 32)); +} + +static void jh7110_gpio_set(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + const struct jh7110_pinctrl_soc_info *info = sfp->info; + unsigned int offset = 4 * (gpio / 4); + unsigned int shift = 8 * (gpio % 4); + void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset; + u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift; + u32 mask = info->dout_mask << shift; + unsigned long flags; + + raw_spin_lock_irqsave(&sfp->lock, flags); + dout |= readl_relaxed(reg_dout) & ~mask; + writel_relaxed(dout, reg_dout); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh7110_gpio_set_config(struct gpio_chip *gc, + unsigned int gpio, unsigned long config) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + u32 arg = pinconf_to_config_argument(config); + u32 value; + u32 mask; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_BIAS_DISABLE: + mask = JH7110_PADCFG_BIAS; + value = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask = JH7110_PADCFG_BIAS; + value = JH7110_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask = JH7110_PADCFG_BIAS; + value = JH7110_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return 0; + case PIN_CONFIG_INPUT_ENABLE: + mask = JH7110_PADCFG_IE; + value = arg ? JH7110_PADCFG_IE : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask = JH7110_PADCFG_SMT; + value = arg ? JH7110_PADCFG_SMT : 0; + break; + default: + return -ENOTSUPP; + } + + jh7110_padcfg_rmw(sfp, gpio, mask, value); + return 0; +} + +static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + + sfp->gpios.name = sfp->gc.label; + sfp->gpios.base = sfp->gc.base; + sfp->gpios.pin_base = 0; + sfp->gpios.npins = sfp->gc.ngpio; + sfp->gpios.gc = &sfp->gc; + pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); + return 0; +} + +static void jh7110_irq_ack(struct irq_data *d) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ic = sfp->base + irq_reg->ic_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); + writel_relaxed(value | mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh7110_irq_mask(struct irq_data *d) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + + gpiochip_disable_irq(&sfp->gc, d->hwirq); +} + +static void jh7110_irq_mask_ack(struct irq_data *d) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + void __iomem *ic = sfp->base + irq_reg->ic_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); + writel_relaxed(value | mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh7110_irq_unmask(struct irq_data *d) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + gpiochip_enable_irq(&sfp->gc, d->hwirq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) | mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d); + const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *base = sfp->base + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + u32 irq_type, edge_both, polarity; + unsigned long flags; + + switch (trigger) { + case IRQ_TYPE_EDGE_RISING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = mask; /* 1: rising edge */ + break; + case IRQ_TYPE_EDGE_FALLING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = 0; /* 0: falling edge */ + break; + case IRQ_TYPE_EDGE_BOTH: + irq_type = mask; /* 1: edge triggered */ + edge_both = mask; /* 1: both edges */ + polarity = 0; /* 0: ignored */ + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = mask; /* 1: high level */ + break; + case IRQ_TYPE_LEVEL_LOW: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = 0; /* 0: low level */ + break; + default: + return -EINVAL; + } + + if (trigger & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask; + writel_relaxed(irq_type, base + irq_reg->is_reg_base); + + edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask; + writel_relaxed(edge_both, base + irq_reg->ibe_reg_base); + + polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask; + writel_relaxed(polarity, base + irq_reg->iev_reg_base); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + return 0; +} + +static struct irq_chip jh7110_irq_chip = { + .irq_ack = jh7110_irq_ack, + .irq_mask = jh7110_irq_mask, + .irq_mask_ack = jh7110_irq_mask_ack, + .irq_unmask = jh7110_irq_unmask, + .irq_set_type = jh7110_irq_set_type, + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void jh7110_disable_clock(void *data) +{ + clk_disable_unprepare(data); +} + +int jh7110_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct jh7110_pinctrl_soc_info *info; + struct jh7110_pinctrl *sfp; + struct pinctrl_desc *jh7110_pinctrl_desc; + struct reset_control *rst; + struct clk *clk; + int ret; + + info = of_device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + if (!info->pins || !info->npins) { + dev_err(dev, "wrong pinctrl info\n"); + return -EINVAL; + } + + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); + if (!sfp) + return -ENOMEM; + + sfp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sfp->base)) + return PTR_ERR(sfp->base); + + clk = devm_clk_get_optional(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n"); + + rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n"); + + /* + * we don't want to assert reset and risk undoing pin muxing for the + * early boot serial console, but let's make sure the reset line is + * deasserted in case someone runs a really minimal bootloader. + */ + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(dev, ret, "could not deassert reset\n"); + + if (clk) { + ret = clk_prepare_enable(clk); + if (ret) + return dev_err_probe(dev, ret, "could not enable clock\n"); + + ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk); + if (ret) + return ret; + } + + jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev, + sizeof(*jh7110_pinctrl_desc), + GFP_KERNEL); + if (!jh7110_pinctrl_desc) + return -ENOMEM; + + jh7110_pinctrl_desc->name = dev_name(dev); + jh7110_pinctrl_desc->pins = info->pins; + jh7110_pinctrl_desc->npins = info->npins; + jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops; + jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops; + jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops; + jh7110_pinctrl_desc->owner = THIS_MODULE; + + sfp->info = info; + sfp->dev = dev; + platform_set_drvdata(pdev, sfp); + sfp->gc.parent = dev; + raw_spin_lock_init(&sfp->lock); + mutex_init(&sfp->mutex); + + ret = devm_pinctrl_register_and_init(dev, + jh7110_pinctrl_desc, + sfp, &sfp->pctl); + if (ret) + return dev_err_probe(dev, ret, + "could not register pinctrl driver\n"); + + sfp->gc.label = dev_name(dev); + sfp->gc.owner = THIS_MODULE; + sfp->gc.request = jh7110_gpio_request; + sfp->gc.free = jh7110_gpio_free; + sfp->gc.get_direction = jh7110_gpio_get_direction; + sfp->gc.direction_input = jh7110_gpio_direction_input; + sfp->gc.direction_output = jh7110_gpio_direction_output; + sfp->gc.get = jh7110_gpio_get; + sfp->gc.set = jh7110_gpio_set; + sfp->gc.set_config = jh7110_gpio_set_config; + sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges; + sfp->gc.base = info->gc_base; + sfp->gc.ngpio = info->ngpios; + + jh7110_irq_chip.name = sfp->gc.label; + gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip); + sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler; + sfp->gc.irq.num_parents = 1; + sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, + sizeof(*sfp->gc.irq.parents), + GFP_KERNEL); + if (!sfp->gc.irq.parents) + return -ENOMEM; + sfp->gc.irq.default_type = IRQ_TYPE_NONE; + sfp->gc.irq.handler = handle_bad_irq; + sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + sfp->gc.irq.parents[0] = ret; + + ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); + if (ret) + return dev_err_probe(dev, ret, "could not register gpiochip\n"); + + irq_domain_set_pm_device(sfp->gc.irq.domain, dev); + + dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio); + + return pinctrl_enable(sfp->pctl); +} +EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe); + +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC"); +MODULE_AUTHOR("Emil Renner Berthing "); +MODULE_AUTHOR("Jianlong Huang "); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h new file mode 100644 index 0000000000000..3f20b7ff96dd8 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __PINCTRL_STARFIVE_JH7110_H__ +#define __PINCTRL_STARFIVE_JH7110_H__ + +#include +#include + +struct jh7110_pinctrl { + struct device *dev; + struct gpio_chip gc; + struct pinctrl_gpio_range gpios; + raw_spinlock_t lock; + void __iomem *base; + struct pinctrl_dev *pctl; + /* register read/write mutex */ + struct mutex mutex; + const struct jh7110_pinctrl_soc_info *info; +}; + +struct jh7110_gpio_irq_reg { + unsigned int is_reg_base; + unsigned int ic_reg_base; + unsigned int ibe_reg_base; + unsigned int iev_reg_base; + unsigned int ie_reg_base; + unsigned int ris_reg_base; + unsigned int mis_reg_base; +}; + +struct jh7110_pinctrl_soc_info { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + unsigned int ngpios; + unsigned int gc_base; + + /* gpio dout/doen/din/gpioinput register */ + unsigned int dout_reg_base; + unsigned int dout_mask; + unsigned int doen_reg_base; + unsigned int doen_mask; + unsigned int gpi_reg_base; + unsigned int gpi_mask; + unsigned int gpioin_reg_base; + + const struct jh7110_gpio_irq_reg *irq_reg; + + /* generic pinmux */ + int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp, + unsigned int pin, + unsigned int din, u32 dout, + u32 doen, u32 func); + /* gpio chip */ + int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp, + unsigned int pin); + void (*jh7110_gpio_irq_handler)(struct irq_desc *desc); + int (*jh7110_gpio_init_hw)(struct gpio_chip *gc); +}; + +void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, + unsigned int din, u32 dout, u32 doen); +int jh7110_pinctrl_probe(struct platform_device *pdev); +struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc); + +#endif /* __PINCTRL_STARFIVE_JH7110_H__ */ From b1170c42141a71e07f9cf5976ecf71323cfcec32 Mon Sep 17 00:00:00 2001 From: Jianlong Huang Date: Thu, 9 Feb 2023 22:37:02 +0800 Subject: [PATCH 117/118] pinctrl: starfive: Add StarFive JH7110 aon controller driver Add pinctrl driver for StarFive JH7110 SoC aon pinctrl controller. Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng Link: https://lore.kernel.org/r/20230209143702.44408-5-hal.feng@starfivetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/Kconfig | 12 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jh7110-aon.c | 177 ++++++++++++++++++ 3 files changed, 190 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 453c8a0b3118c..8192ac2087fc3 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -37,3 +37,15 @@ config PINCTRL_STARFIVE_JH7110_SYS This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH7110_AON + tristate "Always-on pinctrl and GPIO driver for the StarFive JH7110 SoC" + depends on SOC_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH7110 + default SOC_STARFIVE + help + Say yes here to support always-on pin control on the StarFive JH7110 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index dc2d1e3923148..ee0d32d085cbc 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c new file mode 100644 index 0000000000000..8cf28aaed2542 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" +#include "pinctrl-starfive-jh7110.h" + +#define JH7110_AON_NGPIO 4 +#define JH7110_AON_GC_BASE 64 + +/* registers */ +#define JH7110_AON_DOEN 0x0 +#define JH7110_AON_DOUT 0x4 +#define JH7110_AON_GPI 0x8 +#define JH7110_AON_GPIOIN 0x2c + +#define JH7110_AON_GPIOEN 0xc +#define JH7110_AON_GPIOIS 0x10 +#define JH7110_AON_GPIOIC 0x14 +#define JH7110_AON_GPIOIBE 0x18 +#define JH7110_AON_GPIOIEV 0x1c +#define JH7110_AON_GPIOIE 0x20 +#define JH7110_AON_GPIORIS 0x28 +#define JH7110_AON_GPIOMIS 0x28 + +#define JH7110_AON_GPO_PDA_0_5_CFG 0x30 + +static const struct pinctrl_pin_desc jh7110_aon_pins[] = { + PINCTRL_PIN(PAD_TESTEN, "TESTEN"), + PINCTRL_PIN(PAD_RGPIO0, "RGPIO0"), + PINCTRL_PIN(PAD_RGPIO1, "RGPIO1"), + PINCTRL_PIN(PAD_RGPIO2, "RGPIO2"), + PINCTRL_PIN(PAD_RGPIO3, "RGPIO3"), + PINCTRL_PIN(PAD_RSTN, "RSTN"), + PINCTRL_PIN(PAD_GMAC0_MDC, "GMAC0_MDC"), + PINCTRL_PIN(PAD_GMAC0_MDIO, "GMAC0_MDIO"), + PINCTRL_PIN(PAD_GMAC0_RXD0, "GMAC0_RXD0"), + PINCTRL_PIN(PAD_GMAC0_RXD1, "GMAC0_RXD1"), + PINCTRL_PIN(PAD_GMAC0_RXD2, "GMAC0_RXD2"), + PINCTRL_PIN(PAD_GMAC0_RXD3, "GMAC0_RXD3"), + PINCTRL_PIN(PAD_GMAC0_RXDV, "GMAC0_RXDV"), + PINCTRL_PIN(PAD_GMAC0_RXC, "GMAC0_RXC"), + PINCTRL_PIN(PAD_GMAC0_TXD0, "GMAC0_TXD0"), + PINCTRL_PIN(PAD_GMAC0_TXD1, "GMAC0_TXD1"), + PINCTRL_PIN(PAD_GMAC0_TXD2, "GMAC0_TXD2"), + PINCTRL_PIN(PAD_GMAC0_TXD3, "GMAC0_TXD3"), + PINCTRL_PIN(PAD_GMAC0_TXEN, "GMAC0_TXEN"), + PINCTRL_PIN(PAD_GMAC0_TXC, "GMAC0_TXC"), +}; + +static int jh7110_aon_set_one_pin_mux(struct jh7110_pinctrl *sfp, + unsigned int pin, + unsigned int din, u32 dout, + u32 doen, u32 func) +{ + if (pin < sfp->gc.ngpio && func == 0) + jh7110_set_gpiomux(sfp, pin, din, dout, doen); + + return 0; +} + +static int jh7110_aon_get_padcfg_base(struct jh7110_pinctrl *sfp, + unsigned int pin) +{ + if (pin < PAD_GMAC0_MDC) + return JH7110_AON_GPO_PDA_0_5_CFG; + + return -1; +} + +static void jh7110_aon_irq_handler(struct irq_desc *desc) +{ + struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long mis; + unsigned int pin; + + chained_irq_enter(chip, desc); + + mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS); + for_each_set_bit(pin, &mis, JH7110_AON_NGPIO) + generic_handle_domain_irq(sfp->gc.irq.domain, pin); + + chained_irq_exit(chip, desc); +} + +static int jh7110_aon_init_hw(struct gpio_chip *gc) +{ + struct jh7110_pinctrl *sfp = container_of(gc, + struct jh7110_pinctrl, gc); + + /* mask all GPIO interrupts */ + writel_relaxed(0, sfp->base + JH7110_AON_GPIOIE); + /* clear edge interrupt flags */ + writel_relaxed(0, sfp->base + JH7110_AON_GPIOIC); + writel_relaxed(0x0f, sfp->base + JH7110_AON_GPIOIC); + /* enable GPIO interrupts */ + writel_relaxed(1, sfp->base + JH7110_AON_GPIOEN); + return 0; +} + +static const struct jh7110_gpio_irq_reg jh7110_aon_irq_reg = { + .is_reg_base = JH7110_AON_GPIOIS, + .ic_reg_base = JH7110_AON_GPIOIC, + .ibe_reg_base = JH7110_AON_GPIOIBE, + .iev_reg_base = JH7110_AON_GPIOIEV, + .ie_reg_base = JH7110_AON_GPIOIE, + .ris_reg_base = JH7110_AON_GPIORIS, + .mis_reg_base = JH7110_AON_GPIOMIS, +}; + +static const struct jh7110_pinctrl_soc_info jh7110_aon_pinctrl_info = { + .pins = jh7110_aon_pins, + .npins = ARRAY_SIZE(jh7110_aon_pins), + .ngpios = JH7110_AON_NGPIO, + .gc_base = JH7110_AON_GC_BASE, + .dout_reg_base = JH7110_AON_DOUT, + .dout_mask = GENMASK(3, 0), + .doen_reg_base = JH7110_AON_DOEN, + .doen_mask = GENMASK(2, 0), + .gpi_reg_base = JH7110_AON_GPI, + .gpi_mask = GENMASK(3, 0), + .gpioin_reg_base = JH7110_AON_GPIOIN, + .irq_reg = &jh7110_aon_irq_reg, + .jh7110_set_one_pin_mux = jh7110_aon_set_one_pin_mux, + .jh7110_get_padcfg_base = jh7110_aon_get_padcfg_base, + .jh7110_gpio_irq_handler = jh7110_aon_irq_handler, + .jh7110_gpio_init_hw = jh7110_aon_init_hw, +}; + +static const struct of_device_id jh7110_aon_pinctrl_of_match[] = { + { + .compatible = "starfive,jh7110-aon-pinctrl", + .data = &jh7110_aon_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_aon_pinctrl_of_match); + +static struct platform_driver jh7110_aon_pinctrl_driver = { + .probe = jh7110_pinctrl_probe, + .driver = { + .name = "starfive-jh7110-aon-pinctrl", + .of_match_table = jh7110_aon_pinctrl_of_match, + }, +}; +module_platform_driver(jh7110_aon_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller"); +MODULE_AUTHOR("Jianlong Huang "); +MODULE_LICENSE("GPL"); From 099f37a539e616f762241ab999495fb8aa2f5971 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 9 Feb 2023 09:45:09 +0200 Subject: [PATCH 118/118] pinctrl: qcom: Add support for i2c specific pull feature Add support for the new i2c_pull property introduced for SM8550 setting a I2C specific pull mode on I2C able pins. Add the bit to the SM8550 specific driver while at it. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209074510.4153294-1-abel.vesa@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 1 + drivers/pinctrl/qcom/pinctrl-sm8550.c | 1 + 3 files changed, 9 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 5142c363480a0..a69f93e74435b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -310,6 +310,8 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, case PIN_CONFIG_BIAS_PULL_UP: *bit = g->pull_bit; *mask = 3; + if (g->i2c_pull_bit) + *mask |= BIT(g->i2c_pull_bit) >> *bit; break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: *bit = g->od_bit; @@ -336,6 +338,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, #define MSM_KEEPER 2 #define MSM_PULL_UP_NO_KEEPER 2 #define MSM_PULL_UP 3 +#define MSM_I2C_STRONG_PULL_UP 2200 static unsigned msm_regval_to_drive(u32 val) { @@ -387,6 +390,8 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_BIAS_PULL_UP: if (pctrl->soc->pull_no_keeper) arg = arg == MSM_PULL_UP_NO_KEEPER; + else if (arg & BIT(g->i2c_pull_bit)) + arg = MSM_I2C_STRONG_PULL_UP; else arg = arg == MSM_PULL_UP; if (!arg) @@ -467,6 +472,8 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_BIAS_PULL_UP: if (pctrl->soc->pull_no_keeper) arg = MSM_PULL_UP_NO_KEEPER; + else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) + arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; else arg = MSM_PULL_UP; break; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 05a1209bf9ae0..985eceda25173 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -80,6 +80,7 @@ struct msm_pingroup { unsigned pull_bit:5; unsigned drv_bit:5; + unsigned i2c_pull_bit:5; unsigned od_bit:5; unsigned egpio_enable:5; diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 0b7db7d4054ab..c9d038098f2ca 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -47,6 +47,7 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .i2c_pull_bit = 13, \ .egpio_enable = 12, \ .egpio_present = 11, \ .oe_bit = 9, \