From 690dccc4a0bf8b6b4eeb160882ec584d3d0bb642 Mon Sep 17 00:00:00 2001
From: Adam Ford <aford173@gmail.com>
Date: Sun, 23 Apr 2023 07:38:27 -0500
Subject: [PATCH 1/3] Revert "clk: imx: composite-8m: Add support to
determine_rate"
This reverts commit 156e96ff2172518b6f83e97d8f11f677bc668e22.
This patch was found to cause some division issues on the i.MX8MP
which causes the video clocks to not properly divide when division
was greate than 8. This causes video failures on disp1_pix and
disp2_pix clocks.
Until a better solution is found, we'll have to revert this.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20230423123828.1346511-1-aford173@gmail.com
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/imx/clk-composite-8m.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 6883a8199b6c3..cbf0d7955a00a 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -119,17 +119,10 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
return ret;
}
-static int imx8m_clk_divider_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return clk_divider_ops.determine_rate(hw, req);
-}
-
static const struct clk_ops imx8m_clk_composite_divider_ops = {
.recalc_rate = imx8m_clk_composite_divider_recalc_rate,
.round_rate = imx8m_clk_composite_divider_round_rate,
.set_rate = imx8m_clk_composite_divider_set_rate,
- .determine_rate = imx8m_clk_divider_determine_rate,
};
static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
From 5c667d5a5a3ec16609229dddf25a46654186b52b Mon Sep 17 00:00:00 2001
From: Nathan Chancellor <nathan@kernel.org>
Date: Mon, 1 May 2023 14:34:47 -0700
Subject: [PATCH 2/3] clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()
When building with clang + W=1, there is a warning around an internal
comparison check within the FIELD_PREP() macro, due to a 32-bit variable
comparison against ~0ull:
drivers/clk/clk-sp7021.c:316:8: error: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((_m), ...' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/clk-sp7021.c:45:15: note: expanded from macro 'HWM_FIELD_PREP'
(_m << 16) | FIELD_PREP(_m, value); \
^~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK'
BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
include/linux/compiler_types.h:397:22: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:385:23: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler_types.h:377:9: note: expanded from macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
This is expected given the types of the input. Increase the size of the
temporary variable in HWM_FIELD_PREP() to eliminate the warning, which
follows the logic of commit cfd6fb45cfaf ("crypto: ccree - avoid
out-of-range warnings from clang") for the same reasons.
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20230501-sp7021-field_prep-warning-v1-1-5b36d71feefe@kernel.org
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/202303221947.pXP2v4xJ-lkp@intel.com/
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/clk-sp7021.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c
index 8fec14120105e..11d22043ddd7d 100644
--- a/drivers/clk/clk-sp7021.c
+++ b/drivers/clk/clk-sp7021.c
@@ -41,7 +41,7 @@ enum {
/* HIWORD_MASK FIELD_PREP */
#define HWM_FIELD_PREP(mask, value) \
({ \
- u32 _m = mask; \
+ u64 _m = mask; \
(_m << 16) | FIELD_PREP(_m, value); \
})
From 31c6ed4e89187beef8fe2f979c8881ca94839427 Mon Sep 17 00:00:00 2001
From: Hal Feng <hal.feng@starfivetech.com>
Date: Tue, 18 Apr 2023 20:37:56 +0800
Subject: [PATCH 3/3] clk: starfive: Fix RESET_STARFIVE_JH7110 can't be
selected in a specified case
When (ARCH_STARFIVE [=n] && COMPILE_TEST [=y] && RESET_CONTROLLER [=n]),
RESET_STARFIVE_JH7110 can't be selected by CLK_STARFIVE_JH7110_SYS
and CLK_STARFIVE_JH7110_AON.
Add a condition `if RESET_CONTROLLER` to fix it. Also, delete redundant
selected options of CLK_STARFIVE_JH7110_AON because these options are
already selected by the dependency.
Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver")
Fixes: b2ab3c94f41f ("clk: starfive: Add StarFive JH7110 always-on clock driver")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230418123756.62495-2-hal.feng@starfivetech.com
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/starfive/Kconfig | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 71c1148ee5f66..5d2333106f134 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -26,7 +26,7 @@ config CLK_STARFIVE_JH7110_SYS
depends on ARCH_STARFIVE || COMPILE_TEST
select AUXILIARY_BUS
select CLK_STARFIVE_JH71X0
- select RESET_STARFIVE_JH7110
+ select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
default ARCH_STARFIVE
help
Say yes here to support the system clock controller on the
@@ -35,9 +35,6 @@ config CLK_STARFIVE_JH7110_SYS
config CLK_STARFIVE_JH7110_AON
tristate "StarFive JH7110 always-on clock support"
depends on CLK_STARFIVE_JH7110_SYS
- select AUXILIARY_BUS
- select CLK_STARFIVE_JH71X0
- select RESET_STARFIVE_JH7110
default m if ARCH_STARFIVE
help
Say yes here to support the always-on clock controller on the