From 2f4ac2d79eb4c09ee6dbda1d2fc2616f281094f9 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 27 Sep 2020 15:03:13 +0800 Subject: [PATCH 1/4] ARM: imx: Add revision support for i.MX7ULP revision 2.2 On i.MX7ULP revision 2.2, the value is 3, so add support for this revision, otherwise, it will use default revision of 1.0 which is incorrect. Signed-off-by: Anson Huang Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 445256e6a4a0b..f6032ea7de8ba 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -45,6 +45,9 @@ static void __init imx7ulp_set_revision(void) case 2: imx_set_soc_revision(IMX_CHIP_REVISION_2_1); break; + case 3: + imx_set_soc_revision(IMX_CHIP_REVISION_2_2); + break; default: imx_set_soc_revision(IMX_CHIP_REVISION_1_0); break; From 7544bfc0866f56326e47f8ec8b3f68c6db496125 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Nov 2020 19:04:54 -0300 Subject: [PATCH 2/4] ARM: imx: imx7ulp: Add a comment explaining the B2 silicon version To help the users to understand the meaning of bits 31-28 of the JTAG_ID_REG register, add a comment explaining the value that is expected from a i.MX7ULP rev B2. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index f6032ea7de8ba..a3c8dadec1c5a 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -37,6 +37,7 @@ static void __init imx7ulp_set_revision(void) * bit[31:28] of JTAG_ID register defines revision as below from B0: * 0001 B0 * 0010 B1 + * 0011 B2 */ switch (revision >> 28) { case 1: From 53cc6bc69e536efe6c1cef98edfb7b3f0a14fabe Mon Sep 17 00:00:00 2001 From: Sven Van Asbroeck Date: Wed, 4 Nov 2020 11:54:18 -0500 Subject: [PATCH 3/4] ARM: imx: mach-imx6q: correctly identify i.MX6QP SoCs The i.MX6QP rev 1.1 SoC on my board is mis-identified by Linux: the log (incorrectly) shows "i.MX6Q rev 2.1". Correct this by assuming that every SoC that identifies as i.MX6Q with rev >= 2.0 is really an i.MX6QP. Signed-off-by: Sven Van Asbroeck Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6q.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab9..703998ebb52eb 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -245,8 +245,13 @@ static void __init imx6q_axi_init(void) static void __init imx6q_init_machine(void) { - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) - imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + /* + * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. + * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), + * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. + */ + imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); From 4ba79e25d7f1a7394021ba4c215a7ecdcc270fb6 Mon Sep 17 00:00:00 2001 From: Ivan Zaentsev Date: Mon, 16 Nov 2020 19:58:26 +0300 Subject: [PATCH 4/4] ARM: mxs: Add serial number support for i.MX23, i.MX28 SoCs i.MX23 and i.MX28 SoCs unique identifiers are factory-programmed in On-Chip OTP memory. i.MX28's 64-bit unique id is in HW_OCOTP_OPS2:HW_OCOTP_OPS3 (see MCIMX28 Ref. Man., sec. 20.4.22-23). i.MX23 provides 32-bit long unique id in HW_OCOTP_OPS3. Though not clearly documented, there is a clue in sec. 35.9.3. The unique id is reported in /sys/devices/soc0/serial_number and in /proc/cpuinfo Signed-off-by: Ivan Zaentsev Suggested-by: Evgeny Boger Signed-off-by: Shawn Guo --- arch/arm/mach-mxs/mach-mxs.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index c109f47e9cbca..25c9d184fa4c6 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "pm.h" @@ -51,6 +52,9 @@ #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc +#define HW_OCOTP_OPS2 19 /* offset 0x150 */ +#define HW_OCOTP_OPS3 20 /* offset 0x160 */ + static u32 chipid; static u32 socid; @@ -379,6 +383,8 @@ static void __init mxs_machine_init(void) struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; + u64 soc_uid = 0; + const u32 *ocotp = mxs_get_ocotp(); int ret; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -394,8 +400,21 @@ static void __init mxs_machine_init(void) soc_dev_attr->soc_id = mxs_get_soc_id(); soc_dev_attr->revision = mxs_get_revision(); + if (socid == HW_DIGCTL_CHIPID_MX23) { + soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3]; + } else if (socid == HW_DIGCTL_CHIPID_MX28) { + soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2]; + soc_uid <<= 32; + system_serial_low = ocotp[HW_OCOTP_OPS3]; + soc_uid |= system_serial_low; + } + + if (soc_uid) + soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); + soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->serial_number); kfree(soc_dev_attr->revision); kfree(soc_dev_attr); return;