From fdd690969b8b05b0636ac46a66a885c5b1ccd651 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 16 Jul 2014 11:54:17 +0300 Subject: [PATCH 01/10] ARM: tegra: Add SATA controller to Tegra124 device tree This adds the integrated AHCI-compliant Serial ATA controller present in Tegra124 systems-on-chip to the Tegra124 device tree. Signed-off-by: Mikko Perttunen [swarren, fixed node sort order] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 03916efd6fa98..727d395d7ce94 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -480,6 +480,31 @@ reset-names = "fuse"; }; + sata@0,70020000 { + compatible = "nvidia,tegra124-ahci"; + + reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ + <0x0 0x70020000 0x0 0x7000>; /* SATA */ + + interrupts = ; + + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "sata", "sata-oob", "cml1", "pll_e"; + + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + reset-names = "sata", "sata-oob", "sata-cold"; + + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; + phy-names = "sata-phy"; + + status = "disabled"; + }; + hda@0,70030000 { compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; reg = <0x0 0x70030000 0x0 0x10000>; From 1b3ce99f930f991cb2e2b848f35321e23b6020a6 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 16 Jul 2014 11:54:18 +0300 Subject: [PATCH 02/10] ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree This enables the integrated SATA controller on the Tegra124 system-on-chip on the Jetson TK1 board and adds regulators for the onboard Molex connector commonly used to power SATA devices. The regulators are marked always-on since they can be used for other purposes than powering SATA devices. Signed-off-by: Mikko Perttunen [swarren, fixed node sort order] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 624b0fba2d0a0..ef578a71a0484 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1619,6 +1619,18 @@ nvidia,sys-clock-req-active-high; }; + /* Serial ATA */ + sata@0,70020000 { + status = "okay"; + + hvdd-supply = <&vdd_3v3_lp0>; + vddio-supply = <&vdd_1v05_run>; + avdd-supply = <&vdd_1v05_run>; + + target-5v-supply = <&vdd_5v0_sata>; + target-12v-supply = <&vdd_12v0_sata>; + }; + padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; @@ -1828,6 +1840,29 @@ enable-active-high; vin-supply = <&vdd_5v0_sys>; }; + + /* Molex power connector */ + vdd_5v0_sata: regulator@13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_12v0_sata: regulator@14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; }; sound { From b0da12d59d9432aed9f2ae04d6baa8a0e9bc384c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 22 Aug 2014 15:07:13 -0600 Subject: [PATCH 03/10] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables This pinmux tables currently omit any configuration for PCIe clk_req, wake, and rst pins, which in turn causes intermittent failures in U-Boot's PCIe support. Import an updated version of the pinmux tables which rectifies this. (While I'm still hoping to remove the pinmux tables from DTs for Tegra124+ devices, while they're still here, they may as well be complete and correct). Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index ef578a71a0484..3ea41534334da 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1231,6 +1231,41 @@ nvidia,tristate = ; nvidia,enable-input = ; }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pe0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pe"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pe1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; clk3_out_pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; From b10231344f64352bcfc1112b4d33c53e0a63fbcc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 26 Aug 2014 08:14:03 +0200 Subject: [PATCH 04/10] ARM: tegra: Add device tree nodes for flow controller These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 5 +++++ arch/arm/boot/dts/tegra124.dtsi | 5 +++++ arch/arm/boot/dts/tegra20.dtsi | 5 +++++ arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 80b8eddb41050..2ca9c1807f723 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -157,6 +157,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 727d395d7ce94..a6e48142b0278 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -137,6 +137,11 @@ #reset-cells = <1>; }; + flow-controller@0,60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 1908f6937e532..3b374c49d04d9 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -190,6 +190,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 6b35c29278d76..aa6ccea13d308 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -272,6 +272,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; From bf8f0392306869412887bf4a681fea9cb8062fc5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 2 Sep 2014 09:57:09 -0600 Subject: [PATCH 05/10] ARM: tegra: add touchpad to Venice2 DT Venice2 contains an Atmel MXT touchpad. Add an I2C node for it to DT. The Linux driver doesn't quite work on this platform yet, but adding the DT node causes no issues, and will allow the device to work once the driver is fixed. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 70ad91d1a20be..dcbe5858faf14 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -606,6 +606,14 @@ i2c@0,7000c400 { status = "okay"; clock-frequency = <100000>; + + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio>; + interrupts = ; + linux,gpio-keymap = <0 0 0 BTN_LEFT>; + }; }; i2c@0,7000c500 { From edfbad068bde82ef228c551569ae4eabeacaf9a6 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Thu, 4 Sep 2014 15:20:34 -0700 Subject: [PATCH 06/10] ARM: tegra: Move pwm and dpaux labels to tegra124.dtsi These labels will be used by other boards in addition to Venice2, move them to tegra124.dtsi so they are defined in a common place. Signed-off-by: Dylan Reid Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 4 ++-- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index dcbe5858faf14..a076a2c536032 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -36,7 +36,7 @@ nvidia,panel = <&panel>; }; - dpaux: dpaux@0,545c0000 { + dpaux@0,545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; }; @@ -587,7 +587,7 @@ status = "okay"; }; - pwm: pwm@0,7000a000 { + pwm@0,7000a000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a6e48142b0278..0ba3a0b6685f2 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -78,7 +78,7 @@ status = "disabled"; }; - dpaux@0,545c0000 { + dpaux: dpaux@0,545c0000 { compatible = "nvidia,tegra124-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = ; @@ -272,7 +272,7 @@ status = "disabled"; }; - pwm@0,7000a000 { + pwm: pwm@0,7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; From eb481f9ac95cc9350436311036e3a513e1993430 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Thu, 4 Sep 2014 15:20:35 -0700 Subject: [PATCH 07/10] ARM: tegra: add Acer Chromebook 13 device tree The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124 processor and is similar to the Venice2 reference platform. The keyboard, USB 2, audio, sdcard and emmc have been tested and work on the 1366x768 models. The Full HD models haven't been tested yet. WiFi does not yet work, it needs at least some PMIC changes to enable the 32k clock. The elan trackpad is not yet functional but hopefully will be soon as there are patches under review. There is also an issue on reboot because the TPM isn't reset. It will cause the stock firmware to enter recovery mode. This can be worked around by an EC-reset, press the refresh and power keys at the same time. Signed-off-by: Dylan Reid Signed-off-by: Stephen Warren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra124-nyan-big.dts | 1136 +++++++++++++++++++++++ 2 files changed, 1137 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-nyan-big.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3ddeb9c..25d0b9fba4272 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -440,6 +440,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-roth.dtb \ tegra114-tn7.dtb \ tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts new file mode 100644 index 0000000000000..7d0784ce4c748 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -0,0 +1,1136 @@ +/dts-v1/; + +#include +#include "tegra124.dtsi" + +/ { + model = "Acer Chromebook 13 CB5-311"; + compatible = "google,nyan-big", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@0,54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@0,545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pk0 { + nvidia,pins = "pk0", + "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,rcv-sel = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <1>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + nvidia,drive-type = <1>; + }; + codec_irq_l { + nvidia,pins = "ph4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_bl_en { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch_irq_l { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + tpm_davint_l { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_irq_l { + nvidia,pins = "pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_reset_l { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_shdn_l { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_ap { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lid_open { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_sd { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ac_ok { + nvidia,pins = "pj0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sensor_irq_l { + nvidia,pins = "pi6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wifi_en { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_bl { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_hdmi { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + soc_warm_reset_l { + nvidia,pins = "pi5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp_det_l { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mic_det_l { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@0,70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@0,7000a000 { + status = "okay"; + }; + + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@0,7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = ; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@0,70030000 { + status = "okay"; + }; + + sdhci@0,700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + }; + + sdhci@0,700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + sdhci@0,700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + usb@0,7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@0,7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@0,7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = ; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + panel: panel { + compatible = "auo,b133xtn01"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090"; + nvidia,model = "Acer Chromebook 13"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + }; +}; + +#include "cros-ec-keyboard.dtsi" From 6dbaff2bfb2ab0cf5590b193ca6ba52b8990a919 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 3 Sep 2014 09:42:06 -0600 Subject: [PATCH 08/10] ARM: tegra: rely on bootloader pinmux programming on Tegra124 The defined mechanism for programming the Tegra pinmux is to perform all of the following at once in order, before using any I/O controller that is affected by the pinmux: - Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit. - Set up any GPIO pins to their "initial" state. - Program all pinmux settings in one go. Other methods such as: - Not setting CLAMP_INPUTS_WHEN_TRISTATED. - Not setting GPIOs to their "initial" state before programming the pinmux settings of the related pin, in particular the mux function. - Not programming the entire pinmux at once, in order to avoid possible conflicting settings. ... are not qualified or supported by NVIDIA ASIC/syseng. They could cause glitches or undesired output levels on some pins, or controller malfunction. While we've been getting away with doing something different on many Tegra boards without issue, I believe we've just been getting lucky. I'd like to switch all Tegra124 systems to the correct scheme now so they provide the right example to follow, and require that any new boards we support upstream work in the same fashion. While it would be nice to update boards containing older SoCs for consistency, I don't anticipate doing so. It's too much churn to change at this time. At least with all Tegra124 boards converted, the most recent boards provide the correct example. Since the bootloader needs to reprogram the pinmux to access certain peripherals, it must program the entire pinmux due to the supported rules above. As such, there is no need to program any part of the pinmux from the kernel, unless dynamic pinmuxing is used. Given this, we couuld simply remove the pinmux "default" state from the DT entirely. However, some bootloaders parse the DT to perform their initial pinmux setup, so it's useful to keep the pinmux data in DT. To allow this while avoiding redundant work in the kernel, rename the "default" state to "boot". The kernel won't apply this, but bootloaders can still look for this state name and apply it. Note however that the DT provides zero information about the required initial GPIO setup, so bootloaders using this approach are not likely to operate correctly without an additional GPIO initialization table somewhere. Previous discussions on the DT mailing list have rejected adding such a table to DT... The following U-Boot commits fully initialize the pinmux: Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1 Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates Both are part of U-Boot v2014.07 and later. Without those commits, the only fallout I see from this change is that HDMI on Venice2 no longer works. Given the very small user-base of this platform, I feel that requiring a bootloader update is reasonable. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 +++--- arch/arm/boot/dts/tegra124-venice2.dts | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 3ea41534334da..64828c265414e 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -31,10 +31,10 @@ }; pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; - state_default: pinmux { + state_boot: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index a076a2c536032..13008858e9675 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -43,10 +43,10 @@ }; pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; + pinctrl-names = "boot"; + pinctrl-0 = <&pinmux_boot>; - pinmux_default: common { + pinmux_boot: common { dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; From ee588e2a30269d0572fc9ebdd7527f9711d6366d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 17 Sep 2014 10:02:44 -0600 Subject: [PATCH 09/10] ARM: tegra: add PCIe to Tegra124 DT Add the PCIe controller device tree node and hook up the PCIe PHY from the XUSB pad controller. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 66 +++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0ba3a0b6685f2..478c555ebd96b 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -12,6 +12,72 @@ #address-cells = <2>; #size-cells = <2>; + pcie-controller@0,01003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + host1x@0,50000000 { compatible = "nvidia,tegra124-host1x", "simple-bus"; reg = <0x0 0x50000000 0x0 0x00034000>; From 8e2b9e4df655f3708fb8b712f0e66e6ea700995e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 17 Sep 2014 10:02:45 -0600 Subject: [PATCH 10/10] ARM: tegra: enable PCIe in Jetson TK1 DT Enable both PCIe ports, one of which is connected to an onboard ethernet chip, whereas the other goes to a miniPCIe slot. Signed-off-by: Thierry Reding [swarren, fixed PCIe supply property names in DT] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 64828c265414e..029c9a0215413 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -16,6 +16,26 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + pcie-controller@0,01003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + vddio-pex-ctl-supply = <&vdd_3v3_lp0>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + host1x@0,50000000 { hdmi@0,54280000 { status = "okay"; @@ -1550,7 +1570,7 @@ regulator-always-on; }; - ldo0 { + avdd_1v05_run: ldo0 { regulator-name = "+1.05V_RUN_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>;