From fe2edd9cbb7763c68350e267f8060113ce9848fe Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 30 Jul 2015 01:02:36 +0200 Subject: [PATCH 01/22] Documentation: dt: atmel-at91: add clocks to system timer, rstc and shdwc The system timer (at91rm9200), the reset controller and the shutdown controller need an input clock. This is the slow clock and they will not function without it. Also fix the shutdown controller example. Acked-By: Sebastian Reichel Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/arm/atmel-at91.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 424ac8cbfa082..209710cdf3aa8 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -50,6 +50,7 @@ System Timer (ST) required properties: - reg: Should contain registers location and length - interrupts: Should contain interrupt for the ST which is the IRQ line shared across all System Controller members. +- clocks: phandle to input clock. Its subnodes can be: - watchdog: compatible should be "atmel,at91rm9200-wdt" @@ -89,12 +90,14 @@ RSTC Reset Controller required properties: - compatible: Should be "atmel,-rstc". can be "at91sam9260" or "at91sam9g45" - reg: Should contain registers location and length +- clocks: phandle to input clock. Example: rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; RAMC SDRAM/DDR Controller required properties: @@ -117,6 +120,7 @@ required properties: - compatible: Should be "atmel,-shdwc". can be "at91sam9260", "at91sam9rl" or "at91sam9x5". - reg: Should contain registers location and length +- clocks: phandle to input clock. optional properties: - atmel,wakeup-mode: String, operation mode of the wakeup mode. @@ -135,9 +139,10 @@ optional at91sam9x5 properties: Example: - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; Special Function Registers (SFR) From 04600560a01270ef3a9bdeaeeebcfa23df81a327 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Fri, 31 Jul 2015 02:11:14 +0200 Subject: [PATCH 02/22] Documentation: dt: atmel-at91: add slow clock to tcb The timer counters need the slow clock. It is required as they will not function without it. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/arm/atmel-at91.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 209710cdf3aa8..dc2d0f06d0580 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -62,7 +62,7 @@ TC/TCLIB Timer required properties: Note that you can specify several interrupt cells if the TC block has one interrupt per channel. - clock-names: tuple listing input clock names. - Required elements: "t0_clk" + Required elements: "t0_clk", "slow_clk" Optional elements: "t1_clk", "t2_clk" - clocks: phandles to input clocks. From d79e327aa58505fe693ef4a5157cc61eb968be02 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 30 Jul 2015 00:43:07 +0200 Subject: [PATCH 03/22] Documentation: watchdog: at91sam9_wdt: add clocks property The watchdog has an input clock, the slow clock. It is required as it will not function without it. Reviewed-by: Guenter Roeck Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/watchdog/atmel-wdt.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt index a4d869744f595..86fa6de1019bd 100644 --- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt @@ -6,6 +6,7 @@ Required properties: - compatible: must be "atmel,at91sam9260-wdt". - reg: physical base address of the controller and length of memory mapped region. +- clocks: phandle to input clock. Optional properties: - timeout-sec: contains the watchdog timeout in seconds. @@ -39,6 +40,7 @@ Example: compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; timeout-sec = <15>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; From e1162cba4e44bd97d7e690bf664afc71a85b1413 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 30 Jul 2015 00:49:44 +0200 Subject: [PATCH 04/22] Documentation: dt: rtc: at91rm9200: add clocks property The RTC needs an input clock, it is the slow clock. It is required as it will not function without it. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt index 34c1505774bfc..5d3791e789c6b 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt @@ -5,6 +5,7 @@ Required properties: - reg: physical base address of the controller and length of memory mapped region. - interrupts: rtc alarm/event interrupt +- clocks: phandle to input clock. Example: @@ -12,4 +13,5 @@ rtc@fffffe00 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffe00 0x100>; interrupts = <1 4 7>; + clocks = <&clk32k>; }; From 07e15f2155a6cc57dc945e67aaa1267b254cba0f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:09:52 +0200 Subject: [PATCH 05/22] ARM: at91/dt: at91rm9200: use slow clock where necessary The system timer, the RTC and the timer counters need the slow clock, add it. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91rm9200.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index e3cfb9972f545..60edd8baebb81 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -359,6 +359,7 @@ compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; reg = <0xfffffd00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; watchdog { compatible = "atmel,at91rm9200-wdt"; @@ -369,6 +370,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffe00 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; status = "disabled"; }; @@ -378,8 +380,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; tcb1: timer@fffa4000 { @@ -388,8 +390,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; i2c0: i2c@fffb8000 { From d0c7faba1f37885cd2de66b62d00240623c5e59c Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:09:53 +0200 Subject: [PATCH 06/22] ARM: at91/dt: at91sam9260: use slow clock where necessary The watchdog, the reset controller, the real-time timer, the shutdown controller, the timer counters need the slow clock, add it where necessary. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9260.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 4bc3475491028..be9c027ddd979 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -359,11 +359,13 @@ rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffd30 { @@ -379,8 +381,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; tcb1: timer@fffdc000 { @@ -389,8 +391,8 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; pinctrl@fffff400 { @@ -973,6 +975,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; From 547eab90f9ee6495e1a61520c38a7386e8898fad Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:09:54 +0200 Subject: [PATCH 07/22] ARM: at91/dt: at91sam9261: use slow clock where necessary The watchdog, the reset controller, the real-time timer, the shutdown controller and the timer counter need the slow clock, add it where necessary. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9261.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index b2c44a07a3d0e..ce1e3e94a40c2 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -119,8 +119,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>, <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; usb1: gadget@fffa4000 { @@ -820,11 +820,13 @@ rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; }; pit: timer@fffffd30 { @@ -846,6 +848,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; status = "disabled"; }; From 53b0b37852134b19df04cadf7526ddf6650e9915 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:03 +0200 Subject: [PATCH 08/22] ARM: at91/dt: at91sam9263: use slow clock where necessary The watchdog, the reset controller, the two real-time timers, the shutdown controller and the timer counter need the slow clock, add it where necessary. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9263.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index e36d966ef5e88..f1f5fa3a9e6e2 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -377,18 +377,20 @@ compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>; - clock-names = "t0_clk"; + clocks = <&tcb_clk>, <&slow_xtal>; + clock-names = "t0_clk", "slow_clk"; }; rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&slow_xtal>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&slow_xtal>; }; pinctrl@fffff200 { @@ -902,6 +904,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; From 6b2717928c6a938dcd2d1cc6a3054be86117700e Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:04 +0200 Subject: [PATCH 09/22] ARM: at91/dt: at91sam9g45: use slow clock where necessary The watchdog, the reset controller, the RTC, the real-time timer, the shutdown controller and the timer counters need the slow clock, add it where necessary. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9g45.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 4268341b0ebba..18b8b9e297043 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -387,6 +387,7 @@ rstc@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffd30 { @@ -400,22 +401,23 @@ shdwc@fffffd10 { compatible = "atmel,at91sam9rl-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; tcb0: timer@fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; tcb1: timer@fffd4000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; dma: dma-controller@ffffec00 { @@ -1123,6 +1125,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1257,6 +1260,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffdb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; From 67451069d4442d2833c906facaff20aa532dea22 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:05 +0200 Subject: [PATCH 10/22] ARM: at91/dt: at91sam9n12: use slow clock where necessary The watchdog, the reset controller, the RTC, the shutdown controller, the timer counters and the LCD PWM need the slow clock, add it where necessary. The LCD PWM will be handled later. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9n12.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 5c2a8c8c8bd48..345186f91422d 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -376,6 +376,7 @@ rstc@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -388,6 +389,7 @@ shdwc@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; sckc@fffffe50 { @@ -431,16 +433,16 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>; - clock-names = "t0_clk"; + clocks = <&tcb_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>; - clock-names = "t0_clk"; + clocks = <&tcb_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; dma: dma-controller@ffffec00 { @@ -891,6 +893,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -901,6 +904,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; From 8c945b7e4eceb09ecb1405b02561fcc1b058a8eb Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:05 +0200 Subject: [PATCH 11/22] ARM: at91/dt: at91sam9rl: use slow clock where necessary The watchdog, the reset controller, the RTC, the real-time timer, the shutdown controller and the timer counter need the slow clock, add it where necessary. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9rl.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index c9920c64791cf..a0b90aedd3b82 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -121,8 +121,8 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>; - clock-names = "t0_clk", "t1_clk", "t2_clk"; + clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; mmc0: mmc@fffa4000 { @@ -1018,11 +1018,13 @@ rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffd30 { @@ -1036,6 +1038,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; @@ -1083,6 +1086,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffe00 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; From 39c6491505ce872fa52c4961e21ee13ca7675739 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:06 +0200 Subject: [PATCH 12/22] ARM: at91/dt: at91sam9x5: use slow clock where necessary The watchdog, the reset controller, the RTC, the shutdown controller, the timer counters and the LCD PWM need the slow clock, add it where necessary, The LCD PWM will be handled later. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9x5.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index b6c8df8d380ea..747d8f070a5c2 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -376,11 +376,13 @@ rstc@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; shdwc@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -418,16 +420,16 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; dma0: dma-controller@ffffec00 { @@ -1173,6 +1175,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1183,6 +1186,7 @@ compatible = "atmel,at91sam9x5-rtc"; reg = <0xfffffeb0 0x40>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; From 288fb7ff8eed8a611af0fa35648a035976ed5108 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:06 +0200 Subject: [PATCH 13/22] ARM: at91/dt: sama5d3: use slow clock where necessary The watchdog, the reset controller, the RTC, the shutdown controller, the timer counters and the LCD PWM need the slow clock, add it where necessary. [boris.brezillon@free-electrons.com: add tcb clocks] Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d3.dtsi | 8 ++++++-- arch/arm/boot/dts/sama5d3_tcb1.dtsi | 4 ++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 81ced62cedafd..7fa276515f11b 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -145,8 +145,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; i2c0: i2c@f0014000 { @@ -1261,11 +1261,13 @@ rstc@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; }; shutdown-controller@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; }; pit: timer@fffffe30 { @@ -1279,6 +1281,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1315,6 +1318,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; }; }; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index f7fa58fe09f15..801f9745e82f1 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -31,8 +31,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>; - clock-names = "t0_clk"; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; }; }; From 16fd6572e48a3e3ab42cba72a9d7d57881c5fdfd Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 29 Jul 2015 14:10:07 +0200 Subject: [PATCH 14/22] ARM: at91/dt: sama5d4: use slow clock where necessary The watchdog, the reset controller, the RTC, the shutdown controller, the timer counters and the LCD PWM need the slow clock, add it where necessary. Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d4.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 1fa8b3611a03d..8d1de29e8da10 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -957,8 +957,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf801c000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; macb0: ethernet@f8020000 { @@ -1185,8 +1185,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xfc020000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>; - clock-names = "t0_clk"; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; adc0: adc@fc034000 { @@ -1270,11 +1270,13 @@ rstc@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; + clocks = <&clk32k>; }; shdwc@fc068610 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfc068610 0x10>; + clocks = <&clk32k>; }; pit: timer@fc068630 { @@ -1287,6 +1289,7 @@ watchdog@fc068640 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfc068640 0x10>; + clocks = <&clk32k>; status = "disabled"; }; @@ -1320,6 +1323,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xfc0686b0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; }; dbgu: serial@fc069000 { From eeff040ab2f9579bdfa1c4df6a35b2d1cdeeaf31 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 31 Jul 2014 09:35:31 +0200 Subject: [PATCH 15/22] ARM: at91/dt: define hlcdc node in at91sam9x5_lcd.dtsi Define at91sam9x5 hlcdc node for the SoCs with an LCD controller. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9x5_lcd.dtsi | 139 ++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi index 485302e8233d4..1629db9dd5636 100644 --- a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi @@ -13,6 +13,137 @@ / { ahb { apb { + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9x5-hlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + pinctrl@fffff400 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + ; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + ; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + ; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + }; + pmc: pmc@fffffc00 { periphck { lcdc_clk: lcdc_clk { @@ -20,6 +151,14 @@ reg = <25>; }; }; + + systemck { + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; }; }; }; From c052a72ade4dd7ad0e9ddc7a424f93c04657c19d Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 31 Jul 2014 09:36:10 +0200 Subject: [PATCH 16/22] ARM: at91/dt: include lcd dtsi in at91sam9x5 dtsis Actually make use of at91sam9x5_lcd.dtsi in the relevant SoC dtsis. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9g15.dtsi | 1 + arch/arm/boot/dts/at91sam9g35.dtsi | 1 + arch/arm/boot/dts/at91sam9x35.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index cfd7044616d79..27de7dc0f0e09 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" / { model = "Atmel AT91SAM9G15 SoC"; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index e35c2fcf82985..ff4115886f978 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" #include "at91sam9x5_macb0.dtsi" / { diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 499cdc81f4c07..d9054e8167b7c 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -7,6 +7,7 @@ */ #include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" #include "at91sam9x5_macb0.dtsi" #include "at91sam9x5_can.dtsi" From 0171d1d8cf54d4389e596e45c1e5faad73d93eba Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 31 Jul 2014 09:34:54 +0200 Subject: [PATCH 17/22] ARM: at91/dt: add at91sam9x5-ek Display Module dtsi All the at91sam9x5-ek share the share display module, add a dtsi to describe it. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9x5dm.dtsi | 74 +++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/arm/boot/dts/at91sam9x5dm.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi new file mode 100644 index 0000000000000..31676f1b6e31a --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5dm.dtsi @@ -0,0 +1,74 @@ +/* + * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module + * + * Copyright (C) 2014 Atmel, + * 2014 Free Electrons + * + * Author: Boris Brezillon + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + hlcdc: hlcdc@f8038000 { + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "disabled"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "disabled"; + }; + + panel: panel { + compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; +}; From 432a4a82d06fbbf40a76b7cf2c3494c75eaf9863 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 31 Jul 2014 09:37:06 +0200 Subject: [PATCH 18/22] ARM: at91/dt: enable lcd support for at91sam9x5 SoCs Use the at91sam9x5 display module dtsi in the relevant board dts. Signed-off-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9g15ek.dts | 25 +++++++++++++++++++++++++ arch/arm/boot/dts/at91sam9g35ek.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/at91sam9x35ek.dts | 20 ++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts index 26b0444b0f96d..d1d2b400f1c64 100644 --- a/arch/arm/boot/dts/at91sam9g15ek.dts +++ b/arch/arm/boot/dts/at91sam9g15ek.dts @@ -8,9 +8,34 @@ */ /dts-v1/; #include "at91sam9g15.dtsi" +#include "at91sam9x5dm.dtsi" #include "at91sam9x5ek.dtsi" / { model = "Atmel AT91SAM9G15-EK"; compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; + }; + }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts index 641a9bf89ed18..23ec8b13f30a0 100644 --- a/arch/arm/boot/dts/at91sam9g35ek.dts +++ b/arch/arm/boot/dts/at91sam9g35ek.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "at91sam9g35.dtsi" +#include "at91sam9x5dm.dtsi" #include "at91sam9x5ek.dtsi" / { @@ -20,6 +21,26 @@ phy-mode = "rmii"; status = "okay"; }; + + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; }; }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts index 343d32818ca31..fcb67180ea26f 100644 --- a/arch/arm/boot/dts/at91sam9x35ek.dts +++ b/arch/arm/boot/dts/at91sam9x35ek.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "at91sam9x35.dtsi" +#include "at91sam9x5dm.dtsi" #include "at91sam9x5ek.dtsi" / { @@ -20,6 +21,25 @@ phy-mode = "rmii"; status = "okay"; }; + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; }; }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; }; From a437fc59e8a604667634697a13183dc673559348 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 25 Mar 2015 18:41:31 +0800 Subject: [PATCH 19/22] ARM: at91/dt: add drm support for at91sam9n12ek Add drm support for at91sam9n12ek board. Signed-off-by: Bo Shen Signed-off-by: Josh Wu Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9n12.dtsi | 71 +++++++++++++++++++++++++++++ arch/arm/boot/dts/at91sam9n12ek.dts | 61 +++++++++++++++++++++++++ 2 files changed, 132 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 345186f91422d..32bc9a189db0f 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -445,6 +445,34 @@ clock-names = "t0_clk", "slow_clk"; }; + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9n12-hlcdc"; + reg = <0xf8038000 0x2000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; @@ -477,6 +505,49 @@ }; }; + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + ; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = ; /* LCDPWM */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + ; /* LCDD23 pin */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index eab17fcace6d9..efa75064d38a6 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -128,6 +128,22 @@ }; }; + hlcdc: hlcdc@f8038000 { + status = "okay"; + + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + usb1: gadget@f803c000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_vbus_sense>; @@ -161,6 +177,23 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "okay"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + leds { compatible = "gpio-leds"; @@ -194,6 +227,34 @@ }; }; + panel: panel { + compatible = "qd,qd43003c0-40", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + sound { compatible = "atmel,asoc-wm8904"; pinctrl-names = "default"; From 8cf5938713e11cb0a47737c6fa550f444f7ea8b4 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 31 Jul 2015 23:17:10 +0200 Subject: [PATCH 20/22] ARM: at91/dt: at91sam9x5dm: add support for the touschscreen The display module on the at91sam9x5-ek has a resistive touchscreen, add it. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9x5dm.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi index 31676f1b6e31a..3e6b4a0421865 100644 --- a/arch/arm/boot/dts/at91sam9x5dm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5dm.dtsi @@ -25,6 +25,12 @@ }; }; }; + + adc0: adc@f804c000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; }; }; From 921f9a6ca5982efb2a300d45078617ad88f448a4 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 25 Mar 2015 17:31:09 +0100 Subject: [PATCH 21/22] ARM: at91/dt: at91sam9x5dm: add QT1070 touch button controller The display module for at91sam9x5-ek has a few touch buttons, add support for those. Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9x5dm.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi index 3e6b4a0421865..34c089fe0bc0c 100644 --- a/arch/arm/boot/dts/at91sam9x5dm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5dm.dtsi @@ -12,6 +12,18 @@ / { ahb { apb { + i2c0: i2c@f8010000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <7 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + hlcdc: hlcdc@f8038000 { hlcdc-display-controller { pinctrl-names = "default"; @@ -31,6 +43,15 @@ atmel,adc-ts-pressure-threshold = <10000>; status = "okay"; }; + + pinctrl@fffff400 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + ; + }; + }; + }; }; }; From 761c5867ef031fae244d030bc17c93f5a3df106f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 7 Aug 2015 12:54:10 +0200 Subject: [PATCH 22/22] ARM: at91/dt: sama5d2: use slow clock where necessary The watchdog, the reset controller, the RTC, the shutdown controller, the timer counters and the LCD PWM need the slow clock, add it to the currently defined nodes. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d2.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index f39258fa38159..034cd48ae28b4 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -764,16 +764,16 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>; - clock-names = "t0_clk"; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; tcb1: timer@f8010000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8010000 0x100>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>; - clock-names = "t0_clk"; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; }; uart0: serial@f801c000 { @@ -857,6 +857,7 @@ compatible = "atmel,at91rm9200-rtc"; reg = <0xf80480b0 0x30>; interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; }; spi1: spi@fc000000 {