From 65424b99a1c24ef668b3c0ab0ca98e415b3e0f06 Mon Sep 17 00:00:00 2001 From: Jeff Johnson Date: Thu, 16 May 2024 17:19:10 -0700 Subject: [PATCH 01/61] clk: qcom: add missing MODULE_DESCRIPTION() macros Fix the following from 'make W=1' with allmodconfig: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/clk-qcom.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/gcc-msm8976.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/lpass-gfm-sm8250.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/qcom/videocc-sdm845.o Signed-off-by: Jeff Johnson Link: https://lore.kernel.org/r/20240516-qcom-clk-md-v1-1-baca27dd2fb2@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/common.c | 1 + drivers/clk/qcom/gcc-msm8976.c | 1 + drivers/clk/qcom/lpass-gfm-sm8250.c | 1 + drivers/clk/qcom/videocc-sdm845.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 48f81e3a5e802..1e79f05d52265 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -356,3 +356,4 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index, EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QTI Common Clock module"); diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c index f60a8171972b8..7fac0ca594aaf 100644 --- a/drivers/clk/qcom/gcc-msm8976.c +++ b/drivers/clk/qcom/gcc-msm8976.c @@ -4154,3 +4154,4 @@ module_exit(gcc_msm8976_exit); MODULE_AUTHOR("AngeloGioacchino Del Regno "); MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QTI MSM8996 Global Clock Controller"); diff --git a/drivers/clk/qcom/lpass-gfm-sm8250.c b/drivers/clk/qcom/lpass-gfm-sm8250.c index 8a1ee52cbcc38..65d380e30eed9 100644 --- a/drivers/clk/qcom/lpass-gfm-sm8250.c +++ b/drivers/clk/qcom/lpass-gfm-sm8250.c @@ -315,3 +315,4 @@ static struct platform_driver lpass_gfm_clk_driver = { }; module_platform_driver(lpass_gfm_clk_driver); MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QTI SM8250 LPASS Glitch Free Mux clock driver"); diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c index b7f21ecad9612..80095a283a86c 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -343,3 +343,4 @@ static struct platform_driver video_cc_sdm845_driver = { module_platform_driver(video_cc_sdm845_driver); MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("QTI SDM845 VIDEOCC Driver"); From d85dc696ca60d04b499d8c3d44040ac54599a0d3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:07 +0300 Subject: [PATCH 02/61] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks On the affected Qualcomm platforms the display clock controller has additional DP input clocks, describe them in DT schema. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 59cc88a52f6b8..0d82521a5433c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8350-dispcc clocks: + minItems: 7 items: - description: Board XO source - description: Byte clock from DSI PHY0 @@ -35,8 +36,15 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY + - description: Link clock from eDP PHY + - description: VCO DIV clock from eDP PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Link clock from DP2 PHY + - description: VCO DIV clock from DP2 PHY clock-names: + minItems: 7 items: - const: bi_tcxo - const: dsi0_phy_pll_out_byteclk @@ -45,6 +53,12 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + - const: dptx1_phy_pll_link_clk + - const: dptx1_phy_pll_vco_div_clk + - const: dptx2_phy_pll_link_clk + - const: dptx2_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -77,6 +91,20 @@ required: - '#reset-cells' - '#power-domain-cells' +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sc8180x-dispcc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + additionalProperties: false examples: From fcd9354ceb7ae52b11a93e8ac990ad4a8c3a0da7 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Fri, 10 May 2024 18:50:00 +0200 Subject: [PATCH 03/61] clk: qcom: Constify struct pll_vco pll_vco structure are never modified. They are used as .vco_table in "struct clk_alpha_pll". And in this structure, we have: const struct pll_vco *vco_table; Constifying these structures moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: text data bss dec hex filename 9905 47576 0 57481 e089 drivers/clk/qcom/mmcc-msm8994.o After: text data bss dec hex filename 10033 47440 0 57473 e081 drivers/clk/qcom/mmcc-msm8994.o Signed-off-by: Christophe JAILLET Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/c3c9a75ed77a5ef2e9b72081e88225d84bba91cd.1715359776.git.christophe.jaillet@wanadoo.fr Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/camcc-sc8280xp.c | 4 ++-- drivers/clk/qcom/camcc-sm6350.c | 2 +- drivers/clk/qcom/camcc-sm8250.c | 4 ++-- drivers/clk/qcom/dispcc-sm6125.c | 2 +- drivers/clk/qcom/dispcc-sm6350.c | 2 +- drivers/clk/qcom/dispcc-sm6375.c | 2 +- drivers/clk/qcom/dispcc-sm8450.c | 2 +- drivers/clk/qcom/dispcc-sm8550.c | 2 +- drivers/clk/qcom/dispcc-sm8650.c | 2 +- drivers/clk/qcom/gcc-msm8998.c | 2 +- drivers/clk/qcom/gcc-sc8180x.c | 2 +- drivers/clk/qcom/gcc-sm6115.c | 6 +++--- drivers/clk/qcom/gcc-sm6375.c | 4 ++-- drivers/clk/qcom/gpucc-msm8998.c | 2 +- drivers/clk/qcom/gpucc-sdm660.c | 2 +- drivers/clk/qcom/gpucc-sm6115.c | 4 ++-- drivers/clk/qcom/gpucc-sm6125.c | 2 +- drivers/clk/qcom/gpucc-sm6375.c | 2 +- drivers/clk/qcom/gpucc-sm8250.c | 2 +- drivers/clk/qcom/gpucc-sm8350.c | 2 +- drivers/clk/qcom/gpucc-sm8450.c | 2 +- drivers/clk/qcom/gpucc-sm8650.c | 2 +- drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +- drivers/clk/qcom/mmcc-msm8994.c | 4 ++-- drivers/clk/qcom/mmcc-msm8996.c | 6 +++--- drivers/clk/qcom/mmcc-sdm660.c | 4 ++-- drivers/clk/qcom/videocc-sm8150.c | 2 +- drivers/clk/qcom/videocc-sm8250.c | 2 +- 28 files changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c index 8e26ec2def73a..d8de924a878a9 100644 --- a/drivers/clk/qcom/camcc-sc8280xp.c +++ b/drivers/clk/qcom/camcc-sc8280xp.c @@ -45,11 +45,11 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 1800000000, 0 }, }; -static struct pll_vco zonda_vco[] = { +static const struct pll_vco zonda_vco[] = { { 595200000, 3600000000, 0 }, }; diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c index e4e7b308ecf16..c6fe684aa780d 100644 --- a/drivers/clk/qcom/camcc-sm6350.c +++ b/drivers/clk/qcom/camcc-sm6350.c @@ -32,7 +32,7 @@ enum { P_CAMCC_PLL3_OUT_MAIN, }; -static struct pll_vco fabia_vco[] = { +static const struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c index 9b32c56a5bc5a..96103eeda5864 100644 --- a/drivers/clk/qcom/camcc-sm8250.c +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -32,11 +32,11 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; -static struct pll_vco zonda_vco[] = { +static const struct pll_vco zonda_vco[] = { { 595200000UL, 3600000000UL, 0 }, }; diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c index 1cc5f220a3c49..85e07731cce2a 100644 --- a/drivers/clk/qcom/dispcc-sm6125.c +++ b/drivers/clk/qcom/dispcc-sm6125.c @@ -28,7 +28,7 @@ enum { P_GPLL0_OUT_MAIN, }; -static struct pll_vco disp_cc_pll_vco[] = { +static const struct pll_vco disp_cc_pll_vco[] = { { 500000000, 1000000000, 2 }, }; diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c index e4b7464c4d0e9..f712cbef94564 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -31,7 +31,7 @@ enum { P_GCC_DISP_GPLL0_CLK, }; -static struct pll_vco fabia_vco[] = { +static const struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/dispcc-sm6375.c b/drivers/clk/qcom/dispcc-sm6375.c index d81d4e3c0b0de..2d42f85f184b8 100644 --- a/drivers/clk/qcom/dispcc-sm6375.c +++ b/drivers/clk/qcom/dispcc-sm6375.c @@ -35,7 +35,7 @@ enum { P_GCC_DISP_GPLL0_CLK, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 49bb4f58c3915..5d028871624e9 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -71,7 +71,7 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco lucid_evo_vco[] = { +static const struct pll_vco lucid_evo_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 38ecea805503d..88f9347ab77c2 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -71,7 +71,7 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco lucid_ole_vco[] = { +static const struct pll_vco lucid_ole_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index 3eb64bcad487e..c0e1ea63166b4 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -69,7 +69,7 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco lucid_ole_vco[] = { +static const struct pll_vco lucid_ole_vco[] = { { 249600000, 2100000000, 0 }, }; diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index cad7f1c7789cf..5f8c87c1793f3 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -27,7 +27,7 @@ #define GCC_MMSS_MISC 0x0902C #define GCC_GPU_MISC 0x71028 -static struct pll_vco fabia_vco[] = { +static const struct pll_vco fabia_vco[] = { { 250000000, 2000000000, 0 }, { 125000000, 1000000000, 1 }, }; diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 5261bfc92b3dc..ad905affd3766 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -39,7 +39,7 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco trion_vco[] = { +static const struct pll_vco trion_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 13e521cd42596..167e344ad3996 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -42,15 +42,15 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco default_vco[] = { +static const struct pll_vco default_vco[] = { { 500000000, 1000000000, 2 }, }; -static struct pll_vco gpll9_vco[] = { +static const struct pll_vco gpll9_vco[] = { { 500000000, 1250000000, 0 }, }; -static struct pll_vco gpll10_vco[] = { +static const struct pll_vco gpll10_vco[] = { { 750000000, 1500000000, 1 }, }; diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 84639d5b89bfb..ac1ed2d728f91 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -50,11 +50,11 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; -static struct pll_vco zonda_vco[] = { +static const struct pll_vco zonda_vco[] = { { 595200000, 3600000000UL, 0 }, }; diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c index 9a4fdff719ec5..7b1cb44e31b21 100644 --- a/drivers/clk/qcom/gpucc-msm8998.c +++ b/drivers/clk/qcom/gpucc-msm8998.c @@ -48,7 +48,7 @@ static struct clk_branch gpucc_cxo_clk = { }, }; -static struct pll_vco fabia_vco[] = { +static const struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, { 125000000, 1000000000, 1 }, }; diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 459f123a6720b..a52d98b7cf4c2 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -51,7 +51,7 @@ static struct clk_branch gpucc_cxo_clk = { }, }; -static struct pll_vco gpu_vco[] = { +static const struct pll_vco gpu_vco[] = { { 1000000000, 2000000000, 0 }, { 500000000, 1000000000, 2 }, { 250000000, 500000000, 3 }, diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index fb71c21c9a896..9793dd9a25967 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -38,11 +38,11 @@ enum { P_GPU_CC_PLL1_OUT_MAIN, }; -static struct pll_vco default_vco[] = { +static const struct pll_vco default_vco[] = { { 1000000000, 2000000000, 0 }, }; -static struct pll_vco pll1_vco[] = { +static const struct pll_vco pll1_vco[] = { { 500000000, 1000000000, 2 }, }; diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c index 61959ba02f9a4..b719a48fe706c 100644 --- a/drivers/clk/qcom/gpucc-sm6125.c +++ b/drivers/clk/qcom/gpucc-sm6125.c @@ -36,7 +36,7 @@ enum { P_GPU_CC_PLL1_OUT_AUX2, }; -static struct pll_vco gpu_cc_pll_vco[] = { +static const struct pll_vco gpu_cc_pll_vco[] = { { 1000000000, 2000000000, 0 }, { 500000000, 1000000000, 2 }, }; diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index da24276a018e7..4e9a30a080d39 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -42,7 +42,7 @@ enum { P_GPU_CC_PLL1_OUT_ODD, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c index 84f7f65c8d428..012bd1380f555 100644 --- a/drivers/clk/qcom/gpucc-sm8250.c +++ b/drivers/clk/qcom/gpucc-sm8250.c @@ -32,7 +32,7 @@ enum { P_GPU_CC_PLL1_OUT_MAIN, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c index 38505d1388b67..9437d316d145c 100644 --- a/drivers/clk/qcom/gpucc-sm8350.c +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -33,7 +33,7 @@ enum { P_GPU_CC_PLL1_OUT_MAIN, }; -static struct pll_vco lucid_5lpe_vco[] = { +static const struct pll_vco lucid_5lpe_vco[] = { { 249600000, 1750000000, 0 }, }; diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c index 1c4769b646b0e..7b329a8032892 100644 --- a/drivers/clk/qcom/gpucc-sm8450.c +++ b/drivers/clk/qcom/gpucc-sm8450.c @@ -36,7 +36,7 @@ enum { P_GPU_CC_PLL1_OUT_MAIN, }; -static struct pll_vco lucid_evo_vco[] = { +static const struct pll_vco lucid_evo_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c index 03307e482acaa..c53306d3093f7 100644 --- a/drivers/clk/qcom/gpucc-sm8650.c +++ b/drivers/clk/qcom/gpucc-sm8650.c @@ -37,7 +37,7 @@ enum { P_GPU_CC_PLL1_OUT_MAIN, }; -static struct pll_vco lucid_ole_vco[] = { +static const struct pll_vco lucid_ole_vco[] = { { 249600000, 2100000000, 0 }, }; diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c index fd9cd2e3f9565..8ac72d26087e2 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -27,7 +27,7 @@ enum { P_SLEEP_CLK, }; -static struct pll_vco fabia_vco[] = { +static const struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c index 3229ff77372f2..f19080cf715bc 100644 --- a/drivers/clk/qcom/mmcc-msm8994.c +++ b/drivers/clk/qcom/mmcc-msm8994.c @@ -84,14 +84,14 @@ static const struct clk_parent_data mmcc_xo_dsibyte[] = { { .fw_name = "dsi1pllbyte" }, }; -static struct pll_vco mmpll_p_vco[] = { +static const struct pll_vco mmpll_p_vco[] = { { 250000000, 500000000, 3 }, { 500000000, 1000000000, 2 }, { 1000000000, 1500000000, 1 }, { 1500000000, 2000000000, 0 }, }; -static struct pll_vco mmpll_t_vco[] = { +static const struct pll_vco mmpll_t_vco[] = { { 500000000, 1500000000, 0 }, }; diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index d3f2dc798567d..92287d40c3a5f 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -57,20 +57,20 @@ static struct clk_fixed_factor gpll0_div = { }, }; -static struct pll_vco mmpll_p_vco[] = { +static const struct pll_vco mmpll_p_vco[] = { { 250000000, 500000000, 3 }, { 500000000, 1000000000, 2 }, { 1000000000, 1500000000, 1 }, { 1500000000, 2000000000, 0 }, }; -static struct pll_vco mmpll_gfx_vco[] = { +static const struct pll_vco mmpll_gfx_vco[] = { { 400000000, 1000000000, 2 }, { 1000000000, 1500000000, 1 }, { 1500000000, 2000000000, 0 }, }; -static struct pll_vco mmpll_t_vco[] = { +static const struct pll_vco mmpll_t_vco[] = { { 500000000, 1500000000, 0 }, }; diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c index 996bd01fb9ac8..4b8380c2d6485 100644 --- a/drivers/clk/qcom/mmcc-sdm660.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -96,14 +96,14 @@ static struct clk_alpha_pll mmpll6 = { }; /* APSS controlled PLLs */ -static struct pll_vco vco[] = { +static const struct pll_vco vco[] = { { 1000000000, 2000000000, 0 }, { 750000000, 1500000000, 1 }, { 500000000, 1000000000, 2 }, { 250000000, 500000000, 3 }, }; -static struct pll_vco mmpll3_vco[] = { +static const struct pll_vco mmpll3_vco[] = { { 750000000, 1500000000, 1 }, }; diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index a0329260157a0..554631aa279b5 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -24,7 +24,7 @@ enum { P_VIDEO_PLL0_OUT_MAIN, }; -static struct pll_vco trion_vco[] = { +static const struct pll_vco trion_vco[] = { { 249600000, 2000000000, 0 }, }; diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 016b596e03b30..914eddd0ae152 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -26,7 +26,7 @@ enum { P_VIDEO_PLL1_OUT_MAIN, }; -static struct pll_vco lucid_vco[] = { +static const struct pll_vco lucid_vco[] = { { 249600000, 2000000000, 0 }, }; From 97cf92963aeff328829007dd1f5ba51e815438d0 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:31 +0300 Subject: [PATCH 04/61] clk: qcom: Fix SM_GCC_7150 dependencies Add dependencies on "ARM64 or COMPILE_TEST" for SM_GCC_7150. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20240505201038.276047-2-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1bb51a0588726..2b0e536d6d70f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -953,6 +953,7 @@ config SM_GCC_6375 config SM_GCC_7150 tristate "SM7150 Global Clock Controller" + depends on ARM64 || COMPILE_TEST select QCOM_GDSC help Support for the global clock controller on SM7150 devices. From 734b6e7a3b947c045ba9e5f853f6ea33bd78d097 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:32 +0300 Subject: [PATCH 05/61] clk: qcom: gcc-sm7150: constify clk_init_data structures The clk_init_data structures are never modified, make them const. No functional changes. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20240505201038.276047-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sm7150.c | 392 +++++++++++++++++----------------- 1 file changed, 196 insertions(+), 196 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index 44b49f7cd1783..b0c50ebb86bed 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -44,9 +44,9 @@ static struct clk_alpha_pll gpll0 = { .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ + .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, }, .num_parents = 1, @@ -70,9 +70,9 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -83,9 +83,9 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pll0_main_div_cdiv", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -99,9 +99,9 @@ static struct clk_alpha_pll gpll6 = { .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gpll6", - .parent_data = &(const struct clk_parent_data){ + .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, }, .num_parents = 1, @@ -116,9 +116,9 @@ static struct clk_alpha_pll gpll7 = { .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ + .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, }, .num_parents = 1, @@ -252,7 +252,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_ahb_clk_src", .parent_data = gcc_parent_data_0_ao, .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), @@ -272,7 +272,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_rbcpr_clk_src", .parent_data = gcc_parent_data_2_ao, .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), @@ -295,7 +295,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), @@ -309,7 +309,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), @@ -323,7 +323,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), @@ -343,7 +343,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), @@ -363,7 +363,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_phy_refgen_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -383,7 +383,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -687,7 +687,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), @@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -734,7 +734,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), @@ -760,7 +760,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_7, .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_ref_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), @@ -802,7 +802,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -824,7 +824,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -838,7 +838,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), @@ -859,7 +859,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -881,7 +881,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), @@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_vs_ctrl_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_vs_ctrl_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), @@ -957,7 +957,7 @@ static struct clk_rcg2 gcc_vsensor_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_gcc_vsensor_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_vsensor_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), @@ -971,7 +971,7 @@ static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { .clkr = { .enable_reg = 0x2800c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_noc_pcie_tbu_clk", .ops = &clk_branch2_ops, }, @@ -986,9 +986,9 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .clkr = { .enable_reg = 0x82024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, @@ -1006,9 +1006,9 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { .clkr = { .enable_reg = 0x82024, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_aggre_ufs_phy_axi_clk.clkr.hw, }, .num_parents = 1, @@ -1024,9 +1024,9 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { .clkr = { .enable_reg = 0x8201c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, @@ -1042,9 +1042,9 @@ static struct clk_branch gcc_apc_vs_clk = { .clkr = { .enable_reg = 0x7a050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_apc_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -1062,7 +1062,7 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_boot_rom_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1075,7 +1075,7 @@ static struct clk_branch gcc_camera_hf_axi_clk = { .clkr = { .enable_reg = 0xb020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_camera_hf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1088,7 +1088,7 @@ static struct clk_branch gcc_camera_sf_axi_clk = { .clkr = { .enable_reg = 0xb06c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_camera_sf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1103,7 +1103,7 @@ static struct clk_branch gcc_ce1_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ce1_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1116,7 +1116,7 @@ static struct clk_branch gcc_ce1_axi_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ce1_axi_clk", .ops = &clk_branch2_ops, }, @@ -1129,7 +1129,7 @@ static struct clk_branch gcc_ce1_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ce1_clk", .ops = &clk_branch2_ops, }, @@ -1142,9 +1142,9 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .clkr = { .enable_reg = 0x502c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, @@ -1160,9 +1160,9 @@ static struct clk_branch gcc_cpuss_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, @@ -1178,9 +1178,9 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = { .clkr = { .enable_reg = 0x48008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_rbcpr_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_cpuss_rbcpr_clk_src.clkr.hw, }, .num_parents = 1, @@ -1196,7 +1196,7 @@ static struct clk_branch gcc_ddrss_gpu_axi_clk = { .clkr = { .enable_reg = 0x4452c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ddrss_gpu_axi_clk", .ops = &clk_branch2_ops, }, @@ -1209,9 +1209,9 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -1225,9 +1225,9 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, @@ -1242,7 +1242,7 @@ static struct clk_branch gcc_disp_hf_axi_clk = { .clkr = { .enable_reg = 0xb024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_hf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1255,7 +1255,7 @@ static struct clk_branch gcc_disp_sf_axi_clk = { .clkr = { .enable_reg = 0xb070, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_sf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1269,9 +1269,9 @@ static struct clk_branch gcc_gp1_clk = { .clkr = { .enable_reg = 0x64000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, @@ -1287,9 +1287,9 @@ static struct clk_branch gcc_gp2_clk = { .clkr = { .enable_reg = 0x65000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1305,9 +1305,9 @@ static struct clk_branch gcc_gp3_clk = { .clkr = { .enable_reg = 0x66000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, @@ -1322,9 +1322,9 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -1338,9 +1338,9 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, @@ -1355,7 +1355,7 @@ static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .clkr = { .enable_reg = 0x7100c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_memnoc_gfx_clk", .ops = &clk_branch2_ops, }, @@ -1368,7 +1368,7 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .clkr = { .enable_reg = 0x71018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_snoc_dvm_gfx_clk", .ops = &clk_branch2_ops, }, @@ -1381,9 +1381,9 @@ static struct clk_branch gcc_gpu_vs_clk = { .clkr = { .enable_reg = 0x7a04c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -1399,7 +1399,7 @@ static struct clk_branch gcc_npu_axi_clk = { .clkr = { .enable_reg = 0x4d008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_axi_clk", .ops = &clk_branch2_ops, }, @@ -1414,7 +1414,7 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { .clkr = { .enable_reg = 0x4d004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_cfg_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1427,9 +1427,9 @@ static struct clk_branch gcc_npu_gpll0_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -1443,9 +1443,9 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, @@ -1461,9 +1461,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -1481,7 +1481,7 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_cfg_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1494,7 +1494,7 @@ static struct clk_branch gcc_pcie_0_clkref_clk = { .clkr = { .enable_reg = 0x8c008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_clkref_clk", .ops = &clk_branch2_ops, }, @@ -1507,7 +1507,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_mstr_axi_clk", .ops = &clk_branch2_ops, }, @@ -1520,7 +1520,7 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk", .ops = &clk_branch2_ops, }, @@ -1535,7 +1535,7 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_slv_axi_clk", .ops = &clk_branch2_ops, }, @@ -1548,7 +1548,7 @@ static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_slv_q2a_axi_clk", .ops = &clk_branch2_ops, }, @@ -1561,9 +1561,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { .clkr = { .enable_reg = 0x6f004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -1579,9 +1579,9 @@ static struct clk_branch gcc_pcie_phy_refgen_clk = { .clkr = { .enable_reg = 0x6f02c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_phy_refgen_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pcie_phy_refgen_clk_src.clkr.hw, }, .num_parents = 1, @@ -1597,9 +1597,9 @@ static struct clk_branch gcc_pdm2_clk = { .clkr = { .enable_reg = 0x3300c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1617,7 +1617,7 @@ static struct clk_branch gcc_pdm_ahb_clk = { .clkr = { .enable_reg = 0x33004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1630,7 +1630,7 @@ static struct clk_branch gcc_pdm_xo4_clk = { .clkr = { .enable_reg = 0x33008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm_xo4_clk", .ops = &clk_branch2_ops, }, @@ -1645,7 +1645,7 @@ static struct clk_branch gcc_prng_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_prng_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1658,7 +1658,7 @@ static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_core_2x_clk", .ops = &clk_branch2_ops, }, @@ -1671,7 +1671,7 @@ static struct clk_branch gcc_qupv3_wrap0_core_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_core_clk", .ops = &clk_branch2_ops, }, @@ -1684,9 +1684,9 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, @@ -1702,9 +1702,9 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, @@ -1720,9 +1720,9 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1738,9 +1738,9 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, @@ -1756,9 +1756,9 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, @@ -1774,9 +1774,9 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, @@ -1792,9 +1792,9 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, }, .num_parents = 1, @@ -1810,9 +1810,9 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, }, .num_parents = 1, @@ -1828,7 +1828,7 @@ static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_core_2x_clk", .ops = &clk_branch2_ops, }, @@ -1841,7 +1841,7 @@ static struct clk_branch gcc_qupv3_wrap1_core_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_core_clk", .ops = &clk_branch2_ops, }, @@ -1854,9 +1854,9 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, @@ -1872,9 +1872,9 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, @@ -1890,9 +1890,9 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1908,9 +1908,9 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, @@ -1926,9 +1926,9 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, @@ -1944,9 +1944,9 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, @@ -1962,9 +1962,9 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s6_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, }, .num_parents = 1, @@ -1980,9 +1980,9 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s7_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, }, .num_parents = 1, @@ -1998,7 +1998,7 @@ static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_0_m_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2013,7 +2013,7 @@ static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_0_s_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2026,7 +2026,7 @@ static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_1_m_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2041,7 +2041,7 @@ static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_1_s_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2054,7 +2054,7 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .clkr = { .enable_reg = 0x12008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2067,9 +2067,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .clkr = { .enable_reg = 0x1200c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_apps_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, @@ -2085,9 +2085,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .clkr = { .enable_reg = 0x12040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ice_core_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, @@ -2103,7 +2103,7 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .clkr = { .enable_reg = 0x14008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc2_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2116,9 +2116,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .clkr = { .enable_reg = 0x14004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, @@ -2134,7 +2134,7 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .clkr = { .enable_reg = 0x16008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc4_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2147,9 +2147,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .clkr = { .enable_reg = 0x16004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, @@ -2165,9 +2165,9 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, @@ -2183,7 +2183,7 @@ static struct clk_branch gcc_tsif_ahb_clk = { .clkr = { .enable_reg = 0x36004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2196,7 +2196,7 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = { .clkr = { .enable_reg = 0x3600c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_inactivity_timers_clk", .ops = &clk_branch2_ops, }, @@ -2209,9 +2209,9 @@ static struct clk_branch gcc_tsif_ref_clk = { .clkr = { .enable_reg = 0x36008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_tsif_ref_clk_src.clkr.hw, }, .num_parents = 1, @@ -2227,7 +2227,7 @@ static struct clk_branch gcc_ufs_mem_clkref_clk = { .clkr = { .enable_reg = 0x8c000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_mem_clkref_clk", .ops = &clk_branch2_ops, }, @@ -2242,7 +2242,7 @@ static struct clk_branch gcc_ufs_phy_ahb_clk = { .clkr = { .enable_reg = 0x77014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2257,9 +2257,9 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .clkr = { .enable_reg = 0x77038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, @@ -2277,9 +2277,9 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { .clkr = { .enable_reg = 0x77038, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_axi_clk.clkr.hw, }, .num_parents = 1, @@ -2297,9 +2297,9 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .clkr = { .enable_reg = 0x77090, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, @@ -2317,9 +2317,9 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { .clkr = { .enable_reg = 0x77090, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_ice_core_clk.clkr.hw, }, .num_parents = 1, @@ -2337,9 +2337,9 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .clkr = { .enable_reg = 0x77094, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -2357,9 +2357,9 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { .clkr = { .enable_reg = 0x77094, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_phy_aux_clk.clkr.hw, }, .num_parents = 1, @@ -2375,7 +2375,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .clkr = { .enable_reg = 0x7701c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_rx_symbol_0_clk", .ops = &clk_branch2_ops, }, @@ -2388,7 +2388,7 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { .clkr = { .enable_reg = 0x77018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_tx_symbol_0_clk", .ops = &clk_branch2_ops, }, @@ -2403,9 +2403,9 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .clkr = { .enable_reg = 0x7708c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, @@ -2423,9 +2423,9 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { .clkr = { .enable_reg = 0x7708c, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_unipro_core_clk.clkr.hw, }, .num_parents = 1, @@ -2441,9 +2441,9 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .clkr = { .enable_reg = 0xf010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, @@ -2459,9 +2459,9 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { .clkr = { .enable_reg = 0xf018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, @@ -2477,7 +2477,7 @@ static struct clk_branch gcc_usb30_prim_sleep_clk = { .clkr = { .enable_reg = 0xf014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_sleep_clk", .ops = &clk_branch2_ops, }, @@ -2490,7 +2490,7 @@ static struct clk_branch gcc_usb3_prim_clkref_clk = { .clkr = { .enable_reg = 0x8c010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_clkref_clk", .ops = &clk_branch2_ops, }, @@ -2503,9 +2503,9 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { .clkr = { .enable_reg = 0xf050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -2521,9 +2521,9 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .clkr = { .enable_reg = 0xf054, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -2538,7 +2538,7 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { .clkr = { .enable_reg = 0xf058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_pipe_clk", .ops = &clk_branch2_ops, }, @@ -2553,7 +2553,7 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { .clkr = { .enable_reg = 0x6a004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb_phy_cfg_ahb2phy_clk", .ops = &clk_branch2_ops, }, @@ -2566,9 +2566,9 @@ static struct clk_branch gcc_vdda_vs_clk = { .clkr = { .enable_reg = 0x7a00c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vdda_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -2584,9 +2584,9 @@ static struct clk_branch gcc_vddcx_vs_clk = { .clkr = { .enable_reg = 0x7a004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vddcx_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -2602,9 +2602,9 @@ static struct clk_branch gcc_vddmx_vs_clk = { .clkr = { .enable_reg = 0x7a008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vddmx_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -2621,7 +2621,7 @@ static struct clk_branch gcc_video_axi_clk = { .clkr = { .enable_reg = 0xb01c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_video_axi_clk", .ops = &clk_branch2_ops, }, @@ -2636,7 +2636,7 @@ static struct clk_branch gcc_vs_ctrl_ahb_clk = { .clkr = { .enable_reg = 0x7a014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vs_ctrl_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2649,9 +2649,9 @@ static struct clk_branch gcc_vs_ctrl_clk = { .clkr = { .enable_reg = 0x7a010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vs_ctrl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vs_ctrl_clk_src.clkr.hw, }, .num_parents = 1, From ca3a91063acc3abc0fb233591d8cda4b37dc39ac Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:33 +0300 Subject: [PATCH 06/61] dt-bindings: clock: qcom: Add SM7150 DISPCC clocks Add device tree bindings for the display clock controller on Qualcomm SM7150 platform. Co-developed-by: David Wronek Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20240505201038.276047-4-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm7150-dispcc.yaml | 75 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm7150-dispcc.h | 59 +++++++++++++++ 2 files changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm7150-dispcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml new file mode 100644 index 0000000000000..b8d6e1d05ce2f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM7150 + +maintainers: + - Danila Tikhonov + - David Wronek + - Jens Reidel + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM7150. + + See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h + +properties: + compatible: + const: qcom,sm7150-dispcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: GPLL0 source from GCC + - description: Sleep clock source + - description: Byte clock from MDSS DSI PHY0 + - description: Pixel clock from MDSS DSI PHY0 + - description: Byte clock from MDSS DSI PHY1 + - description: Pixel clock from MDSS DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + power-domains: + maxItems: 1 + description: + CX power domain. + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@af00000 { + compatible = "qcom,sm7150-dispcc"; + reg = <0x0af00000 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/include/dt-bindings/clock/qcom,sm7150-dispcc.h new file mode 100644 index 0000000000000..fc1fefe8fd724 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7150-dispcc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, David Wronek + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H +#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H + +/* DISPCC clock registers */ +#define DISPCC_PLL0 0 +#define DISPCC_MDSS_AHB_CLK 1 +#define DISPCC_MDSS_AHB_CLK_SRC 2 +#define DISPCC_MDSS_BYTE0_CLK 3 +#define DISPCC_MDSS_BYTE0_CLK_SRC 4 +#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISPCC_MDSS_BYTE0_INTF_CLK 6 +#define DISPCC_MDSS_BYTE1_CLK 7 +#define DISPCC_MDSS_BYTE1_CLK_SRC 8 +#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9 +#define DISPCC_MDSS_BYTE1_INTF_CLK 10 +#define DISPCC_MDSS_DP_AUX_CLK 11 +#define DISPCC_MDSS_DP_AUX_CLK_SRC 12 +#define DISPCC_MDSS_DP_CRYPTO_CLK 13 +#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14 +#define DISPCC_MDSS_DP_LINK_CLK 15 +#define DISPCC_MDSS_DP_LINK_CLK_SRC 16 +#define DISPCC_MDSS_DP_LINK_INTF_CLK 17 +#define DISPCC_MDSS_DP_PIXEL1_CLK 18 +#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19 +#define DISPCC_MDSS_DP_PIXEL_CLK 20 +#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21 +#define DISPCC_MDSS_ESC0_CLK 22 +#define DISPCC_MDSS_ESC0_CLK_SRC 23 +#define DISPCC_MDSS_ESC1_CLK 24 +#define DISPCC_MDSS_ESC1_CLK_SRC 25 +#define DISPCC_MDSS_MDP_CLK 26 +#define DISPCC_MDSS_MDP_CLK_SRC 27 +#define DISPCC_MDSS_MDP_LUT_CLK 28 +#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29 +#define DISPCC_MDSS_PCLK0_CLK 30 +#define DISPCC_MDSS_PCLK0_CLK_SRC 31 +#define DISPCC_MDSS_PCLK1_CLK 32 +#define DISPCC_MDSS_PCLK1_CLK_SRC 33 +#define DISPCC_MDSS_ROT_CLK 34 +#define DISPCC_MDSS_ROT_CLK_SRC 35 +#define DISPCC_MDSS_RSCC_AHB_CLK 36 +#define DISPCC_MDSS_RSCC_VSYNC_CLK 37 +#define DISPCC_MDSS_VSYNC_CLK 38 +#define DISPCC_MDSS_VSYNC_CLK_SRC 39 +#define DISPCC_XO_CLK_SRC 40 +#define DISPCC_SLEEP_CLK 41 +#define DISPCC_SLEEP_CLK_SRC 42 + +/* DISPCC GDSCR */ +#define MDSS_GDSC 0 + +#endif From 3829c412197e14b8cac445d0e3a76c7cd5fff064 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:34 +0300 Subject: [PATCH 07/61] clk: qcom: Add Display Clock Controller driver for SM7150 Add support for the display clock controller found on SM7150. Co-developed-by: David Wronek Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20240505201038.276047-5-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-sm7150.c | 1006 ++++++++++++++++++++++++++++++ 3 files changed, 1017 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-sm7150.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 2b0e536d6d70f..7b4c2ff580a39 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -847,6 +847,16 @@ config SM_DISPCC_6125 Say Y if you want to support display devices and functionality such as splash screen +config SM_DISPCC_7150 + tristate "SM7150 Display Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on SM_GCC_7150 + help + Support for the display clock controller on Qualcomm Technologies, Inc + SM7150 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config SM_DISPCC_8250 tristate "SM8150/SM8250/SM8350 Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec5b6db6860c..cdec5ce2bb94e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -113,6 +113,7 @@ obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o +obj-$(CONFIG_SM_DISPCC_7150) += dispcc-sm7150.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c new file mode 100644 index 0000000000000..5c8ae95b67636 --- /dev/null +++ b/drivers/clk/qcom/dispcc-sm7150.c @@ -0,0 +1,1006 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + * Copyright (c) 2024, David Wronek + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_GCC_DISP_GPLL0_CLK, + DT_CHIP_SLEEP_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + DT_DP_PHY_PLL_LINK_CLK, + DT_DP_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_CHIP_SLEEP_CLK, + P_DISPCC_PLL0_OUT_EVEN, + P_DISPCC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GCC_DISP_GPLL0_CLK, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, + { 125000000, 1000000000, 1 }, +}; + +/* 860MHz configuration */ +static const struct alpha_pll_config dispcc_pll0_config = { + .l = 0x2c, + .alpha = 0xcaaa, + .test_ctl_val = 0x40000000, +}; + +static struct clk_alpha_pll dispcc_pll0 = { + .offset = 0x0, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct parent_map dispcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, +}; + +static const struct clk_parent_data dispcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map dispcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data dispcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DP_PHY_PLL_LINK_CLK }, + { .index = DT_DP_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map dispcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data dispcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct clk_parent_data dispcc_parent_data_2_ao[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct parent_map dispcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISPCC_PLL0_OUT_MAIN, 1 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, + { P_DISPCC_PLL0_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data dispcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &dispcc_pll0.clkr.hw }, + { .index = DT_GCC_DISP_GPLL0_CLK }, + { .hw = &dispcc_pll0.clkr.hw }, +}; + +static const struct parent_map dispcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data dispcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, +}; + +static const struct parent_map dispcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, +}; + +static const struct clk_parent_data dispcc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_DISP_GPLL0_CLK }, +}; + +static const struct parent_map dispcc_parent_map_6[] = { + { P_CHIP_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data dispcc_parent_data_6[] = { + { .index = DT_CHIP_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_dispcc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0), + F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), + { } +}; + +static struct clk_rcg2 dispcc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x22bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_5, + .freq_tbl = ftbl_dispcc_mdss_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_ahb_clk_src", + .parent_data = dispcc_parent_data_5, + .num_parents = ARRAY_SIZE(dispcc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dispcc_mdss_byte0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dispcc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x2110, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_0, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte0_clk_src", + .parent_data = dispcc_parent_data_0, + .num_parents = ARRAY_SIZE(dispcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_byte1_clk_src = { + .cmd_rcgr = 0x212c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_0, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte1_clk_src", + .parent_data = dispcc_parent_data_0, + .num_parents = ARRAY_SIZE(dispcc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x21dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_2, + .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_aux_clk_src", + .parent_data = dispcc_parent_data_2, + .num_parents = ARRAY_SIZE(dispcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dispcc_mdss_dp_crypto_clk_src[] = { + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 dispcc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x2194, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_1, + .freq_tbl = ftbl_dispcc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_crypto_clk_src", + .parent_data = dispcc_parent_data_1, + .num_parents = ARRAY_SIZE(dispcc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x2178, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_1, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_link_clk_src", + .parent_data = dispcc_parent_data_1, + .num_parents = ARRAY_SIZE(dispcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr = 0x21c4, + .mnd_width = 16, + .hid_width = 5, + .parent_map = dispcc_parent_map_1, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_pixel1_clk_src", + .parent_data = dispcc_parent_data_1, + .num_parents = ARRAY_SIZE(dispcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x21ac, + .mnd_width = 16, + .hid_width = 5, + .parent_map = dispcc_parent_map_1, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_pixel_clk_src", + .parent_data = dispcc_parent_data_1, + .num_parents = ARRAY_SIZE(dispcc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x2148, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_0, + .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_esc0_clk_src", + .parent_data = dispcc_parent_data_0, + .num_parents = ARRAY_SIZE(dispcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_esc1_clk_src = { + .cmd_rcgr = 0x2160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_0, + .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_esc1_clk_src", + .parent_data = dispcc_parent_data_0, + .num_parents = ARRAY_SIZE(dispcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dispcc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(85714286, P_GCC_DISP_GPLL0_CLK, 7, 0, 0), + F(100000000, P_GCC_DISP_GPLL0_CLK, 6, 0, 0), + F(150000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0), + F(172000000, P_DISPCC_PLL0_OUT_MAIN, 5, 0, 0), + F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0), + F(286666667, P_DISPCC_PLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0), + F(344000000, P_DISPCC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(430000000, P_DISPCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dispcc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x20c8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_3, + .freq_tbl = ftbl_dispcc_mdss_mdp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_mdp_clk_src", + .parent_data = dispcc_parent_data_3, + .num_parents = ARRAY_SIZE(dispcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x2098, + .mnd_width = 8, + .hid_width = 5, + .parent_map = dispcc_parent_map_4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_pclk0_clk_src", + .parent_data = dispcc_parent_data_4, + .num_parents = ARRAY_SIZE(dispcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_pclk1_clk_src = { + .cmd_rcgr = 0x20b0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = dispcc_parent_map_4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_pclk1_clk_src", + .parent_data = dispcc_parent_data_4, + .num_parents = ARRAY_SIZE(dispcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_pixel_ops, + }, +}; + +static const struct freq_tbl ftbl_dispcc_mdss_rot_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(171428571, P_GCC_DISP_GPLL0_CLK, 3.5, 0, 0), + F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0), + F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0), + F(344000000, P_DISPCC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(430000000, P_DISPCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dispcc_mdss_rot_clk_src = { + .cmd_rcgr = 0x20e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_3, + .freq_tbl = ftbl_dispcc_mdss_rot_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_rot_clk_src", + .parent_data = dispcc_parent_data_3, + .num_parents = ARRAY_SIZE(dispcc_parent_data_3), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 dispcc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x20f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_2, + .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_vsync_clk_src", + .parent_data = dispcc_parent_data_2, + .num_parents = ARRAY_SIZE(dispcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dispcc_sleep_clk_src[] = { + F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dispcc_sleep_clk_src = { + .cmd_rcgr = 0x6060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_6, + .freq_tbl = ftbl_dispcc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_sleep_clk_src", + .parent_data = dispcc_parent_data_6, + .num_parents = ARRAY_SIZE(dispcc_parent_data_6), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 dispcc_xo_clk_src = { + .cmd_rcgr = 0x6044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = dispcc_parent_map_2, + .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "dispcc_xo_clk_src", + .parent_data = dispcc_parent_data_2_ao, + .num_parents = ARRAY_SIZE(dispcc_parent_data_2_ao), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch dispcc_mdss_ahb_clk = { + .halt_reg = 0x2080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_byte0_clk = { + .halt_reg = 0x2028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte0_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div dispcc_mdss_byte0_div_clk_src = { + .reg = 0x2128, + .shift = 0, + .width = 2, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_byte0_intf_clk = { + .halt_reg = 0x202c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x202c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_byte1_clk = { + .halt_reg = 0x2030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte1_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div dispcc_mdss_byte1_div_clk_src = { + .reg = 0x2144, + .shift = 0, + .width = 2, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_byte1_intf_clk = { + .halt_reg = 0x2034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_byte1_intf_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_dp_aux_clk = { + .halt_reg = 0x2054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_aux_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_dp_crypto_clk = { + .halt_reg = 0x2048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_crypto_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_dp_link_clk = { + .halt_reg = 0x2040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_link_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_dp_pixel1_clk = { + .halt_reg = 0x2050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_pixel1_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_dp_pixel1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_dp_pixel_clk = { + .halt_reg = 0x204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x204c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_dp_pixel_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_esc0_clk = { + .halt_reg = 0x2038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_esc0_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_esc1_clk = { + .halt_reg = 0x203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x203c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_esc1_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_mdp_clk = { + .halt_reg = 0x200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x200c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_mdp_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_mdp_lut_clk = { + .halt_reg = 0x201c, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x201c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_non_gdsc_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_pclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_pclk1_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_pclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_rot_clk = { + .halt_reg = 0x2014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_rot_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_rscc_ahb_clk = { + .halt_reg = 0x400c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x400c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_rscc_ahb_clk", + .parent_names = (const char *[]) { + "dispcc_mdss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_rscc_vsync_clk = { + .halt_reg = 0x4008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_rscc_vsync_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_mdss_vsync_clk = { + .halt_reg = 0x2024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_mdss_vsync_clk", + .parent_hws = (const struct clk_hw*[]) { + &dispcc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dispcc_sleep_clk = { + .halt_reg = 0x6078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "dispcc_sleep_clk", + .parent_names = (const char *[]) { + "dispcc_sleep_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x3000, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "mdss_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL, +}; + +static struct clk_regmap *dispcc_sm7150_clocks[] = { + [DISPCC_MDSS_AHB_CLK] = &dispcc_mdss_ahb_clk.clkr, + [DISPCC_MDSS_AHB_CLK_SRC] = &dispcc_mdss_ahb_clk_src.clkr, + [DISPCC_MDSS_BYTE0_CLK] = &dispcc_mdss_byte0_clk.clkr, + [DISPCC_MDSS_BYTE0_CLK_SRC] = &dispcc_mdss_byte0_clk_src.clkr, + [DISPCC_MDSS_BYTE0_DIV_CLK_SRC] = &dispcc_mdss_byte0_div_clk_src.clkr, + [DISPCC_MDSS_BYTE0_INTF_CLK] = &dispcc_mdss_byte0_intf_clk.clkr, + [DISPCC_MDSS_BYTE1_CLK] = &dispcc_mdss_byte1_clk.clkr, + [DISPCC_MDSS_BYTE1_CLK_SRC] = &dispcc_mdss_byte1_clk_src.clkr, + [DISPCC_MDSS_BYTE1_DIV_CLK_SRC] = &dispcc_mdss_byte1_div_clk_src.clkr, + [DISPCC_MDSS_BYTE1_INTF_CLK] = &dispcc_mdss_byte1_intf_clk.clkr, + [DISPCC_MDSS_DP_AUX_CLK] = &dispcc_mdss_dp_aux_clk.clkr, + [DISPCC_MDSS_DP_AUX_CLK_SRC] = &dispcc_mdss_dp_aux_clk_src.clkr, + [DISPCC_MDSS_DP_CRYPTO_CLK] = &dispcc_mdss_dp_crypto_clk.clkr, + [DISPCC_MDSS_DP_CRYPTO_CLK_SRC] = &dispcc_mdss_dp_crypto_clk_src.clkr, + [DISPCC_MDSS_DP_LINK_CLK] = &dispcc_mdss_dp_link_clk.clkr, + [DISPCC_MDSS_DP_LINK_CLK_SRC] = &dispcc_mdss_dp_link_clk_src.clkr, + [DISPCC_MDSS_DP_LINK_INTF_CLK] = &dispcc_mdss_dp_link_intf_clk.clkr, + [DISPCC_MDSS_DP_PIXEL1_CLK] = &dispcc_mdss_dp_pixel1_clk.clkr, + [DISPCC_MDSS_DP_PIXEL1_CLK_SRC] = &dispcc_mdss_dp_pixel1_clk_src.clkr, + [DISPCC_MDSS_DP_PIXEL_CLK] = &dispcc_mdss_dp_pixel_clk.clkr, + [DISPCC_MDSS_DP_PIXEL_CLK_SRC] = &dispcc_mdss_dp_pixel_clk_src.clkr, + [DISPCC_MDSS_ESC0_CLK] = &dispcc_mdss_esc0_clk.clkr, + [DISPCC_MDSS_ESC0_CLK_SRC] = &dispcc_mdss_esc0_clk_src.clkr, + [DISPCC_MDSS_ESC1_CLK] = &dispcc_mdss_esc1_clk.clkr, + [DISPCC_MDSS_ESC1_CLK_SRC] = &dispcc_mdss_esc1_clk_src.clkr, + [DISPCC_MDSS_MDP_CLK] = &dispcc_mdss_mdp_clk.clkr, + [DISPCC_MDSS_MDP_CLK_SRC] = &dispcc_mdss_mdp_clk_src.clkr, + [DISPCC_MDSS_MDP_LUT_CLK] = &dispcc_mdss_mdp_lut_clk.clkr, + [DISPCC_MDSS_NON_GDSC_AHB_CLK] = &dispcc_mdss_non_gdsc_ahb_clk.clkr, + [DISPCC_MDSS_PCLK0_CLK] = &dispcc_mdss_pclk0_clk.clkr, + [DISPCC_MDSS_PCLK0_CLK_SRC] = &dispcc_mdss_pclk0_clk_src.clkr, + [DISPCC_MDSS_PCLK1_CLK] = &dispcc_mdss_pclk1_clk.clkr, + [DISPCC_MDSS_PCLK1_CLK_SRC] = &dispcc_mdss_pclk1_clk_src.clkr, + [DISPCC_MDSS_ROT_CLK] = &dispcc_mdss_rot_clk.clkr, + [DISPCC_MDSS_ROT_CLK_SRC] = &dispcc_mdss_rot_clk_src.clkr, + [DISPCC_MDSS_RSCC_AHB_CLK] = &dispcc_mdss_rscc_ahb_clk.clkr, + [DISPCC_MDSS_RSCC_VSYNC_CLK] = &dispcc_mdss_rscc_vsync_clk.clkr, + [DISPCC_MDSS_VSYNC_CLK] = &dispcc_mdss_vsync_clk.clkr, + [DISPCC_MDSS_VSYNC_CLK_SRC] = &dispcc_mdss_vsync_clk_src.clkr, + [DISPCC_PLL0] = &dispcc_pll0.clkr, + [DISPCC_SLEEP_CLK] = &dispcc_sleep_clk.clkr, + [DISPCC_SLEEP_CLK_SRC] = &dispcc_sleep_clk_src.clkr, + [DISPCC_XO_CLK_SRC] = &dispcc_xo_clk_src.clkr, +}; + +static struct gdsc *dispcc_sm7150_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, +}; + +static const struct regmap_config dispcc_sm7150_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc dispcc_sm7150_desc = { + .config = &dispcc_sm7150_regmap_config, + .clks = dispcc_sm7150_clocks, + .num_clks = ARRAY_SIZE(dispcc_sm7150_clocks), + .gdscs = dispcc_sm7150_gdscs, + .num_gdscs = ARRAY_SIZE(dispcc_sm7150_gdscs), +}; + +static const struct of_device_id dispcc_sm7150_match_table[] = { + { .compatible = "qcom,sm7150-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, dispcc_sm7150_match_table); + +static int dispcc_sm7150_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &dispcc_sm7150_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&dispcc_pll0, regmap, &dispcc_pll0_config); + /* Enable clock gating for DSI and MDP clocks */ + regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x605c); /* DISPCC_XO_CLK */ + + return qcom_cc_really_probe(pdev, &dispcc_sm7150_desc, regmap); +} + +static struct platform_driver dispcc_sm7150_driver = { + .probe = dispcc_sm7150_probe, + .driver = { + .name = "dispcc-sm7150", + .of_match_table = dispcc_sm7150_match_table, + }, +}; + +module_platform_driver(dispcc_sm7150_driver); + +MODULE_DESCRIPTION("Qualcomm SM7150 Display Clock Controller"); +MODULE_LICENSE("GPL"); From 0fd2a048368ea99feccd7dfd6a5f42f6d011f10f Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:35 +0300 Subject: [PATCH 08/61] dt-bindings: clock: qcom: Add SM7150 CAMCC clocks Add device tree bindings for the camera clock controller on Qualcomm SM7150 platform. Signed-off-by: Danila Tikhonov Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20240505201038.276047-6-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm7150-camcc.yaml | 60 ++++++++++ include/dt-bindings/clock/qcom,sm7150-camcc.h | 113 ++++++++++++++++++ 2 files changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm7150-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml new file mode 100644 index 0000000000000..7be4b10c430cd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm7150-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM7150 + +maintainers: + - Danila Tikhonov + - David Wronek + - Jens Reidel + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM7150. + + See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h + +properties: + compatible: + const: qcom,sm7150-camcc + + clocks: + items: + - description: Board XO source + - description: Board XO Active-Only source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: + CX power domain. + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@ad00000 { + compatible = "qcom,sm7150-camcc"; + reg = <0xad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm7150-camcc.h b/include/dt-bindings/clock/qcom,sm7150-camcc.h new file mode 100644 index 0000000000000..ce73ef0fe95d5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7150-camcc.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H +#define _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H + +/* Hardware clocks */ +#define CAMCC_PLL0_OUT_EVEN 0 +#define CAMCC_PLL0_OUT_ODD 1 +#define CAMCC_PLL1_OUT_EVEN 2 +#define CAMCC_PLL2_OUT_EARLY 3 +#define CAMCC_PLL3_OUT_EVEN 4 +#define CAMCC_PLL4_OUT_EVEN 5 + +/* CAMCC clock registers */ +#define CAMCC_PLL0 6 +#define CAMCC_PLL1 7 +#define CAMCC_PLL2 8 +#define CAMCC_PLL2_OUT_AUX 9 +#define CAMCC_PLL2_OUT_MAIN 10 +#define CAMCC_PLL3 11 +#define CAMCC_PLL4 12 +#define CAMCC_BPS_AHB_CLK 13 +#define CAMCC_BPS_AREG_CLK 14 +#define CAMCC_BPS_AXI_CLK 15 +#define CAMCC_BPS_CLK 16 +#define CAMCC_BPS_CLK_SRC 17 +#define CAMCC_CAMNOC_AXI_CLK 18 +#define CAMCC_CAMNOC_AXI_CLK_SRC 19 +#define CAMCC_CAMNOC_DCD_XO_CLK 20 +#define CAMCC_CCI_0_CLK 21 +#define CAMCC_CCI_0_CLK_SRC 22 +#define CAMCC_CCI_1_CLK 23 +#define CAMCC_CCI_1_CLK_SRC 24 +#define CAMCC_CORE_AHB_CLK 25 +#define CAMCC_CPAS_AHB_CLK 26 +#define CAMCC_CPHY_RX_CLK_SRC 27 +#define CAMCC_CSI0PHYTIMER_CLK 28 +#define CAMCC_CSI0PHYTIMER_CLK_SRC 29 +#define CAMCC_CSI1PHYTIMER_CLK 30 +#define CAMCC_CSI1PHYTIMER_CLK_SRC 31 +#define CAMCC_CSI2PHYTIMER_CLK 32 +#define CAMCC_CSI2PHYTIMER_CLK_SRC 33 +#define CAMCC_CSI3PHYTIMER_CLK 34 +#define CAMCC_CSI3PHYTIMER_CLK_SRC 35 +#define CAMCC_CSIPHY0_CLK 36 +#define CAMCC_CSIPHY1_CLK 37 +#define CAMCC_CSIPHY2_CLK 38 +#define CAMCC_CSIPHY3_CLK 39 +#define CAMCC_FAST_AHB_CLK_SRC 40 +#define CAMCC_FD_CORE_CLK 41 +#define CAMCC_FD_CORE_CLK_SRC 42 +#define CAMCC_FD_CORE_UAR_CLK 43 +#define CAMCC_ICP_AHB_CLK 44 +#define CAMCC_ICP_CLK 45 +#define CAMCC_ICP_CLK_SRC 46 +#define CAMCC_IFE_0_AXI_CLK 47 +#define CAMCC_IFE_0_CLK 48 +#define CAMCC_IFE_0_CLK_SRC 49 +#define CAMCC_IFE_0_CPHY_RX_CLK 50 +#define CAMCC_IFE_0_CSID_CLK 51 +#define CAMCC_IFE_0_CSID_CLK_SRC 52 +#define CAMCC_IFE_0_DSP_CLK 53 +#define CAMCC_IFE_1_AXI_CLK 54 +#define CAMCC_IFE_1_CLK 55 +#define CAMCC_IFE_1_CLK_SRC 56 +#define CAMCC_IFE_1_CPHY_RX_CLK 57 +#define CAMCC_IFE_1_CSID_CLK 58 +#define CAMCC_IFE_1_CSID_CLK_SRC 59 +#define CAMCC_IFE_1_DSP_CLK 60 +#define CAMCC_IFE_LITE_CLK 61 +#define CAMCC_IFE_LITE_CLK_SRC 62 +#define CAMCC_IFE_LITE_CPHY_RX_CLK 63 +#define CAMCC_IFE_LITE_CSID_CLK 64 +#define CAMCC_IFE_LITE_CSID_CLK_SRC 65 +#define CAMCC_IPE_0_AHB_CLK 66 +#define CAMCC_IPE_0_AREG_CLK 67 +#define CAMCC_IPE_0_AXI_CLK 68 +#define CAMCC_IPE_0_CLK 69 +#define CAMCC_IPE_0_CLK_SRC 70 +#define CAMCC_IPE_1_AHB_CLK 71 +#define CAMCC_IPE_1_AREG_CLK 72 +#define CAMCC_IPE_1_AXI_CLK 73 +#define CAMCC_IPE_1_CLK 74 +#define CAMCC_JPEG_CLK 75 +#define CAMCC_JPEG_CLK_SRC 76 +#define CAMCC_LRME_CLK 77 +#define CAMCC_LRME_CLK_SRC 78 +#define CAMCC_MCLK0_CLK 79 +#define CAMCC_MCLK0_CLK_SRC 80 +#define CAMCC_MCLK1_CLK 81 +#define CAMCC_MCLK1_CLK_SRC 82 +#define CAMCC_MCLK2_CLK 83 +#define CAMCC_MCLK2_CLK_SRC 84 +#define CAMCC_MCLK3_CLK 85 +#define CAMCC_MCLK3_CLK_SRC 86 +#define CAMCC_SLEEP_CLK 87 +#define CAMCC_SLEEP_CLK_SRC 88 +#define CAMCC_SLOW_AHB_CLK_SRC 89 +#define CAMCC_XO_CLK_SRC 90 + +/* CAMCC GDSCRs */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IPE_0_GDSC 3 +#define IPE_1_GDSC 4 +#define TITAN_TOP_GDSC 5 + +#endif From 9f0532da42261476561c0a683097f6de82e7c3ed Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:36 +0300 Subject: [PATCH 09/61] clk: qcom: Add Camera Clock Controller driver for SM7150 Add support for the camera clock controller found on SM7150. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20240505201038.276047-7-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sm7150.c | 2061 +++++++++++++++++++++++++++++++ 3 files changed, 2070 insertions(+) create mode 100644 drivers/clk/qcom/camcc-sm7150.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7b4c2ff580a39..14e19f4c804c3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -803,6 +803,14 @@ config SM_CAMCC_6350 Support for the camera clock controller on SM6350 devices. Say Y if you want to support camera devices and camera functionality. +config SM_CAMCC_7150 + tristate "SM7150 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_7150 + help + Support for the camera clock controller on SM7150 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_CAMCC_8250 tristate "SM8250 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index cdec5ce2bb94e..9c83abef9cacf 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o +obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c new file mode 100644 index 0000000000000..a81ce6ab8cd52 --- /dev/null +++ b/drivers/clk/qcom/camcc-sm7150.c @@ -0,0 +1,2061 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_CHIP_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_MX, + P_CAMCC_PLL0_OUT_EVEN, + P_CAMCC_PLL0_OUT_MAIN, + P_CAMCC_PLL0_OUT_ODD, + P_CAMCC_PLL1_OUT_EVEN, + P_CAMCC_PLL2_OUT_AUX, + P_CAMCC_PLL2_OUT_EARLY, + P_CAMCC_PLL2_OUT_MAIN, + P_CAMCC_PLL3_OUT_EVEN, + P_CAMCC_PLL4_OUT_EVEN, + P_CHIP_SLEEP_CLK, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 1200MHz configuration */ +static const struct alpha_pll_config camcc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .post_div_mask = 0xff << 8, + .post_div_val = 0x31 << 8, + .test_ctl_val = 0x40000000, +}; + +static struct clk_alpha_pll camcc_pll0 = { + .offset = 0x0, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static struct clk_fixed_factor camcc_pll0_out_even = { + .mult = 1, + .div = 2, + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor camcc_pll0_out_odd = { + .mult = 1, + .div = 3, + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +/* 680MHz configuration */ +static const struct alpha_pll_config camcc_pll1_config = { + .l = 0x23, + .alpha = 0x6aaa, + .post_div_mask = 0xf << 8, + .post_div_val = 0x1 << 8, + .test_ctl_val = 0x40000000, +}; + +static struct clk_alpha_pll camcc_pll1 = { + .offset = 0x1000, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static struct clk_fixed_factor camcc_pll1_out_even = { + .mult = 1, + .div = 2, + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +/* 1920MHz configuration */ +static const struct alpha_pll_config camcc_pll2_config = { + .l = 0x64, + .post_div_val = 0x3 << 8, + .post_div_mask = 0x3 << 8, + .early_output_mask = BIT(3), + .aux_output_mask = BIT(1), + .main_output_mask = BIT(0), + .config_ctl_hi_val = 0x400003d6, + .config_ctl_val = 0x20000954, +}; + +static struct clk_alpha_pll camcc_pll2 = { + .offset = 0x2000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_agera_ops, + }, + }, +}; + +static struct clk_fixed_factor camcc_pll2_out_early = { + .mult = 1, + .div = 2, + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll2_out_early", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll2.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll_postdiv camcc_pll2_out_aux = { + .offset = 0x2000, + .post_div_shift = 8, + .width = 2, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_pll2_out_aux", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll2.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +static struct clk_alpha_pll_postdiv camcc_pll2_out_main = { + .offset = 0x2000, + .post_div_shift = 8, + .width = 2, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_pll2_out_main", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll2.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +/* 760MHz configuration */ +static const struct alpha_pll_config camcc_pll3_config = { + .l = 0x27, + .alpha = 0x9555, + .post_div_mask = 0xf << 8, + .post_div_val = 0x1 << 8, + .test_ctl_val = 0x40000000, +}; + +static struct clk_alpha_pll camcc_pll3 = { + .offset = 0x3000, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static struct clk_fixed_factor camcc_pll3_out_even = { + .mult = 1, + .div = 2, + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll camcc_pll4 = { + .offset = 0x4000, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static struct clk_fixed_factor camcc_pll4_out_even = { + .mult = 1, + .div = 2, + .hw.init = &(const struct clk_init_data) { + .name = "camcc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &camcc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct parent_map camcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL0_OUT_MAIN, 1 }, + { P_CAMCC_PLL0_OUT_EVEN, 2 }, + { P_CAMCC_PLL0_OUT_ODD, 3 }, + { P_CAMCC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data camcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll0.clkr.hw }, + { .hw = &camcc_pll0_out_even.hw }, + { .hw = &camcc_pll0_out_odd.hw }, + { .hw = &camcc_pll2_out_main.clkr.hw }, +}; + +static const struct parent_map camcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL0_OUT_MAIN, 1 }, + { P_CAMCC_PLL0_OUT_EVEN, 2 }, + { P_CAMCC_PLL0_OUT_ODD, 3 }, + { P_CAMCC_PLL1_OUT_EVEN, 4 }, + { P_CAMCC_PLL2_OUT_EARLY, 5 }, +}; + +static const struct clk_parent_data camcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll0.clkr.hw }, + { .hw = &camcc_pll0_out_even.hw }, + { .hw = &camcc_pll0_out_odd.hw }, + { .hw = &camcc_pll1_out_even.hw }, + { .hw = &camcc_pll2_out_early.hw }, +}; + +static const struct parent_map camcc_parent_map_2[] = { + { P_BI_TCXO_MX, 0 }, + { P_CAMCC_PLL2_OUT_AUX, 5 }, +}; + +static const struct clk_parent_data camcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll2_out_aux.clkr.hw }, +}; + +static const struct parent_map camcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL0_OUT_MAIN, 1 }, + { P_CAMCC_PLL0_OUT_EVEN, 2 }, + { P_CAMCC_PLL0_OUT_ODD, 3 }, + { P_CAMCC_PLL2_OUT_EARLY, 5 }, + { P_CAMCC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data camcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll0.clkr.hw }, + { .hw = &camcc_pll0_out_even.hw }, + { .hw = &camcc_pll0_out_odd.hw }, + { .hw = &camcc_pll2_out_early.hw }, + { .hw = &camcc_pll4_out_even.hw }, +}; + +static const struct parent_map camcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data camcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll3_out_even.hw }, +}; + +static const struct parent_map camcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data camcc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll4_out_even.hw }, +}; + +static const struct parent_map camcc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data camcc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll1_out_even.hw }, +}; + +static const struct parent_map camcc_parent_map_7[] = { + { P_CHIP_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data camcc_parent_data_7[] = { + { .index = DT_CHIP_SLEEP_CLK }, +}; + +static const struct parent_map camcc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_CAMCC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data camcc_parent_data_8[] = { + { .index = DT_BI_TCXO }, + { .hw = &camcc_pll0_out_odd.hw }, +}; + +static const struct parent_map camcc_parent_map_9[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data camcc_parent_data_9[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), + F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_bps_clk_src = { + .cmd_rcgr = 0x7010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_bps_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0), + F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), + F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_camnoc_axi_clk_src = { + .cmd_rcgr = 0xc12c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_camnoc_axi_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_camnoc_axi_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_cci_0_clk_src = { + .cmd_rcgr = 0xc0c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_cci_0_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_cci_1_clk_src = { + .cmd_rcgr = 0xc0e0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_cci_1_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), + F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_cphy_rx_clk_src = { + .cmd_rcgr = 0xa064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_1, + .freq_tbl = ftbl_camcc_cphy_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_cphy_rx_clk_src", + .parent_data = camcc_parent_data_1, + .num_parents = ARRAY_SIZE(camcc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x6004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_csi0phytimer_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x6028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_csi1phytimer_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x604c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_csi2phytimer_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x6070, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_csi3phytimer_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0), + F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), + F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_fast_ahb_clk_src = { + .cmd_rcgr = 0x703c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_fast_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_fast_ahb_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_fd_core_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), + F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0), + F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_fd_core_clk_src = { + .cmd_rcgr = 0xc09c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_3, + .freq_tbl = ftbl_camcc_fd_core_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_fd_core_clk_src", + .parent_data = camcc_parent_data_3, + .num_parents = ARRAY_SIZE(camcc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), + F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_icp_clk_src = { + .cmd_rcgr = 0xc074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_icp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_icp_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), + F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), + F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), + F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_ife_0_clk_src = { + .cmd_rcgr = 0xa010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_4, + .freq_tbl = ftbl_camcc_ife_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_clk_src", + .parent_data = camcc_parent_data_4, + .num_parents = ARRAY_SIZE(camcc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), + F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), + F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_ife_0_csid_clk_src = { + .cmd_rcgr = 0xa03c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_1, + .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_csid_clk_src", + .parent_data = camcc_parent_data_1, + .num_parents = ARRAY_SIZE(camcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), + F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), + F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), + F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_ife_1_clk_src = { + .cmd_rcgr = 0xb010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_5, + .freq_tbl = ftbl_camcc_ife_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_clk_src", + .parent_data = camcc_parent_data_5, + .num_parents = ARRAY_SIZE(camcc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 camcc_ife_1_csid_clk_src = { + .cmd_rcgr = 0xb034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_1, + .freq_tbl = ftbl_camcc_ife_0_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_csid_clk_src", + .parent_data = camcc_parent_data_1, + .num_parents = ARRAY_SIZE(camcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), + F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_ife_lite_clk_src = { + .cmd_rcgr = 0xc004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_ife_lite_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_lite_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0xc020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_1, + .freq_tbl = ftbl_camcc_cphy_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_lite_csid_clk_src", + .parent_data = camcc_parent_data_1, + .num_parents = ARRAY_SIZE(camcc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), + F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), + F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_ipe_0_clk_src = { + .cmd_rcgr = 0x8010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_6, + .freq_tbl = ftbl_camcc_ipe_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_0_clk_src", + .parent_data = camcc_parent_data_6, + .num_parents = ARRAY_SIZE(camcc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 camcc_jpeg_clk_src = { + .cmd_rcgr = 0xc048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_jpeg_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), + F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), + F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0), + F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), + F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_lrme_clk_src = { + .cmd_rcgr = 0xc100, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_0, + .freq_tbl = ftbl_camcc_lrme_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_lrme_clk_src", + .parent_data = camcc_parent_data_0, + .num_parents = ARRAY_SIZE(camcc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO_MX, 1, 0, 0), + F(24000000, P_CAMCC_PLL2_OUT_AUX, 1, 1, 20), + F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_mclk0_clk_src = { + .cmd_rcgr = 0x5004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = camcc_parent_map_2, + .freq_tbl = ftbl_camcc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk0_clk_src", + .parent_data = camcc_parent_data_2, + .num_parents = ARRAY_SIZE(camcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_mclk1_clk_src = { + .cmd_rcgr = 0x5024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = camcc_parent_map_2, + .freq_tbl = ftbl_camcc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk1_clk_src", + .parent_data = camcc_parent_data_2, + .num_parents = ARRAY_SIZE(camcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_mclk2_clk_src = { + .cmd_rcgr = 0x5044, + .mnd_width = 8, + .hid_width = 5, + .parent_map = camcc_parent_map_2, + .freq_tbl = ftbl_camcc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk2_clk_src", + .parent_data = camcc_parent_data_2, + .num_parents = ARRAY_SIZE(camcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 camcc_mclk3_clk_src = { + .cmd_rcgr = 0x5064, + .mnd_width = 8, + .hid_width = 5, + .parent_map = camcc_parent_map_2, + .freq_tbl = ftbl_camcc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk3_clk_src", + .parent_data = camcc_parent_data_2, + .num_parents = ARRAY_SIZE(camcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = { + F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_sleep_clk_src = { + .cmd_rcgr = 0xc1a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_7, + .freq_tbl = ftbl_camcc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_sleep_clk_src", + .parent_data = camcc_parent_data_7, + .num_parents = ARRAY_SIZE(camcc_parent_data_7), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_slow_ahb_clk_src = { + .cmd_rcgr = 0x7058, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_8, + .freq_tbl = ftbl_camcc_slow_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_slow_ahb_clk_src", + .parent_data = camcc_parent_data_8, + .num_parents = ARRAY_SIZE(camcc_parent_data_8), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_camcc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 camcc_xo_clk_src = { + .cmd_rcgr = 0xc188, + .mnd_width = 0, + .hid_width = 5, + .parent_map = camcc_parent_map_9, + .freq_tbl = ftbl_camcc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "camcc_xo_clk_src", + .parent_data = camcc_parent_data_9, + .num_parents = ARRAY_SIZE(camcc_parent_data_9), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch camcc_bps_ahb_clk = { + .halt_reg = 0x7070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_bps_areg_clk = { + .halt_reg = 0x7054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_bps_areg_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_bps_axi_clk = { + .halt_reg = 0x7038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_bps_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_bps_clk = { + .halt_reg = 0x7028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_camnoc_axi_clk = { + .halt_reg = 0xc148, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_camnoc_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_camnoc_dcd_xo_clk = { + .halt_reg = 0xc150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_cci_0_clk = { + .halt_reg = 0xc0dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_cci_1_clk = { + .halt_reg = 0xc0f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_core_ahb_clk = { + .halt_reg = 0xc184, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xc184, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_cpas_ahb_clk = { + .halt_reg = 0xc124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc124, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csi0phytimer_clk = { + .halt_reg = 0x601c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x601c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csi1phytimer_clk = { + .halt_reg = 0x6040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csi2phytimer_clk = { + .halt_reg = 0x6064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csi3phytimer_clk = { + .halt_reg = 0x6088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csiphy0_clk = { + .halt_reg = 0x6020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csiphy1_clk = { + .halt_reg = 0x6044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csiphy2_clk = { + .halt_reg = 0x6068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_csiphy3_clk = { + .halt_reg = 0x608c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x608c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_fd_core_clk = { + .halt_reg = 0xc0b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_fd_core_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_fd_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_fd_core_uar_clk = { + .halt_reg = 0xc0bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc0bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_fd_core_uar_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_fd_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_icp_ahb_clk = { + .halt_reg = 0xc094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_icp_clk = { + .halt_reg = 0xc08c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc08c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_icp_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_0_axi_clk = { + .halt_reg = 0xa080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_0_clk = { + .halt_reg = 0xa028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_0_cphy_rx_clk = { + .halt_reg = 0xa07c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa07c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_0_csid_clk = { + .halt_reg = 0xa054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_0_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_0_dsp_clk = { + .halt_reg = 0xa038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_0_dsp_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_1_axi_clk = { + .halt_reg = 0xb058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_1_clk = { + .halt_reg = 0xb028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_1_cphy_rx_clk = { + .halt_reg = 0xb054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_1_csid_clk = { + .halt_reg = 0xb04c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb04c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_1_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_1_dsp_clk = { + .halt_reg = 0xb030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_1_dsp_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_lite_clk = { + .halt_reg = 0xc01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_lite_cphy_rx_clk = { + .halt_reg = 0xc040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ife_lite_csid_clk = { + .halt_reg = 0xc038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_0_ahb_clk = { + .halt_reg = 0x8040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_0_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_0_areg_clk = { + .halt_reg = 0x803c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x803c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_0_areg_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_0_axi_clk = { + .halt_reg = 0x8038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_0_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_0_clk = { + .halt_reg = 0x8028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ipe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_1_ahb_clk = { + .halt_reg = 0x9028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_1_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_1_areg_clk = { + .halt_reg = 0x9024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_1_areg_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_1_axi_clk = { + .halt_reg = 0x9020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_1_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_ipe_1_clk = { + .halt_reg = 0x9010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_ipe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_ipe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_jpeg_clk = { + .halt_reg = 0xc060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_lrme_clk = { + .halt_reg = 0xc118, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc118, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_lrme_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_lrme_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_mclk0_clk = { + .halt_reg = 0x501c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x501c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_mclk1_clk = { + .halt_reg = 0x503c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x503c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_mclk2_clk = { + .halt_reg = 0x505c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x505c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_mclk3_clk = { + .halt_reg = 0x507c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x507c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camcc_sleep_clk = { + .halt_reg = 0xc1bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc1bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "camcc_sleep_clk", + .parent_hws = (const struct clk_hw*[]) { + &camcc_sleep_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc camcc_titan_top_gdsc; + +static struct gdsc camcc_bps_gdsc = { + .gdscr = 0x7004, + .pd = { + .name = "camcc_bps_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camcc_ife_0_gdsc = { + .gdscr = 0xa004, + .pd = { + .name = "camcc_ife_0_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &camcc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camcc_ife_1_gdsc = { + .gdscr = 0xb004, + .pd = { + .name = "camcc_ife_1_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .parent = &camcc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camcc_ipe_0_gdsc = { + .gdscr = 0x8004, + .pd = { + .name = "camcc_ipe_0_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camcc_ipe_1_gdsc = { + .gdscr = 0x9004, + .pd = { + .name = "camcc_ipe_1_gdsc", + }, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camcc_titan_top_gdsc = { + .gdscr = 0xc1c4, + .pd = { + .name = "camcc_titan_top_gdsc", + }, + .flags = POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +struct clk_hw *camcc_sm7150_hws[] = { + [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw, + [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw, + [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw, + [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw, + [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.hw, + [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.hw, +}; + +static struct clk_regmap *camcc_sm7150_clocks[] = { + [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, + [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, + [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, + [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, + [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, + [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, + [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr, + [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr, + [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, + [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, + [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, + [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, + [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, + [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, + [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, + [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, + [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, + [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, + [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, + [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, + [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, + [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, + [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, + [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, + [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, + [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, + [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, + [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, + [CAMCC_FD_CORE_CLK] = &camcc_fd_core_clk.clkr, + [CAMCC_FD_CORE_CLK_SRC] = &camcc_fd_core_clk_src.clkr, + [CAMCC_FD_CORE_UAR_CLK] = &camcc_fd_core_uar_clk.clkr, + [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr, + [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, + [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, + [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, + [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, + [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, + [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, + [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, + [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, + [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, + [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, + [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, + [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, + [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, + [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, + [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, + [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, + [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr, + [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr, + [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr, + [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr, + [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr, + [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, + [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, + [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, + [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, + [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, + [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr, + [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr, + [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr, + [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr, + [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, + [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, + [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, + [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, + [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, + [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, + [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, + [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, + [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, + [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, + [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, + [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, + [CAMCC_PLL0] = &camcc_pll0.clkr, + [CAMCC_PLL1] = &camcc_pll1.clkr, + [CAMCC_PLL2] = &camcc_pll2.clkr, + [CAMCC_PLL2_OUT_AUX] = &camcc_pll2_out_aux.clkr, + [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr, + [CAMCC_PLL3] = &camcc_pll3.clkr, + [CAMCC_PLL4] = &camcc_pll4.clkr, + [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr, + [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr, + [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, + [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr, +}; + +static struct gdsc *camcc_sm7150_gdscs[] = { + [BPS_GDSC] = &camcc_bps_gdsc, + [IFE_0_GDSC] = &camcc_ife_0_gdsc, + [IFE_1_GDSC] = &camcc_ife_1_gdsc, + [IPE_0_GDSC] = &camcc_ipe_0_gdsc, + [IPE_1_GDSC] = &camcc_ipe_1_gdsc, + [TITAN_TOP_GDSC] = &camcc_titan_top_gdsc, +}; + +static const struct regmap_config camcc_sm7150_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xd024, + .fast_io = true, +}; + +static const struct qcom_cc_desc camcc_sm7150_desc = { + .config = &camcc_sm7150_regmap_config, + .clk_hws = camcc_sm7150_hws, + .num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws), + .clks = camcc_sm7150_clocks, + .num_clks = ARRAY_SIZE(camcc_sm7150_clocks), + .gdscs = camcc_sm7150_gdscs, + .num_gdscs = ARRAY_SIZE(camcc_sm7150_gdscs), +}; + +static const struct of_device_id camcc_sm7150_match_table[] = { + { .compatible = "qcom,sm7150-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, camcc_sm7150_match_table); + +static int camcc_sm7150_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &camcc_sm7150_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); + clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); + clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); + clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); + clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */ + + return qcom_cc_really_probe(pdev, &camcc_sm7150_desc, regmap); +} + +static struct platform_driver camcc_sm7150_driver = { + .probe = camcc_sm7150_probe, + .driver = { + .name = "camcc-sm7150", + .of_match_table = camcc_sm7150_match_table, + }, +}; + +module_platform_driver(camcc_sm7150_driver); + +MODULE_DESCRIPTION("Qualcomm SM7150 Camera Clock Controller"); +MODULE_LICENSE("GPL"); From a4be1860b9319e9e55eaa9e28e35e7b19128060c Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:37 +0300 Subject: [PATCH 10/61] dt-bindings: clock: qcom: Add SM7150 VIDEOCC clocks Add device tree bindings for the video clock controller on Qualcomm SM7150 platform. Signed-off-by: Danila Tikhonov Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20240505201038.276047-8-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm7150-videocc.yaml | 58 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm7150-videocc.h | 28 +++++++++ 2 files changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm7150-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml new file mode 100644 index 0000000000000..037ffc71e70e0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm7150-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM7150 + +maintainers: + - Danila Tikhonov + - David Wronek + - Jens Reidel + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM7150. + + See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h + +properties: + compatible: + const: qcom,sm7150-videocc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + + power-domains: + maxItems: 1 + description: + CX power domain. + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + videocc: clock-controller@ab00000 { + compatible = "qcom,sm7150-videocc"; + reg = <0x0ab00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm7150-videocc.h b/include/dt-bindings/clock/qcom,sm7150-videocc.h new file mode 100644 index 0000000000000..d86e0fbb159a7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7150-videocc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEOCC_SM7150_H +#define _DT_BINDINGS_CLK_QCOM_VIDEOCC_SM7150_H + +#define VIDEOCC_PLL0 0 +#define VIDEOCC_IRIS_AHB_CLK 1 +#define VIDEOCC_IRIS_CLK_SRC 2 +#define VIDEOCC_MVS0_AXI_CLK 3 +#define VIDEOCC_MVS0_CORE_CLK 4 +#define VIDEOCC_MVS1_AXI_CLK 5 +#define VIDEOCC_MVS1_CORE_CLK 6 +#define VIDEOCC_MVSC_CORE_CLK 7 +#define VIDEOCC_MVSC_CTL_AXI_CLK 8 +#define VIDEOCC_VENUS_AHB_CLK 9 +#define VIDEOCC_XO_CLK 10 +#define VIDEOCC_XO_CLK_SRC 11 + +/* VIDEOCC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif From aa9fc5c90814fcb9ecabbb505e097ff05abf962e Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 May 2024 23:10:38 +0300 Subject: [PATCH 11/61] clk: qcom: Add Video Clock Controller driver for SM7150 Add support for the video clock controller found on SM7150. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20240505201038.276047-9-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm7150.c | 357 ++++++++++++++++++++++++++++++ 3 files changed, 368 insertions(+) create mode 100644 drivers/clk/qcom/videocc-sm7150.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 14e19f4c804c3..20ba2eeb24ec0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1137,6 +1137,16 @@ config SM_TCSRCC_8650 Support for the TCSR clock controller on SM8650 devices. Say Y if you want to use peripheral devices such as SD/UFS. +config SM_VIDEOCC_7150 + tristate "SM7150 Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_7150 + select QCOM_GDSC + help + Support for the video clock controller on SM7150 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9c83abef9cacf..b7de8600dc3d8 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -143,6 +143,7 @@ obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o +obj-$(CONFIG_SM_VIDEOCC_7150) += videocc-sm7150.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o diff --git a/drivers/clk/qcom/videocc-sm7150.c b/drivers/clk/qcom/videocc-sm7150.c new file mode 100644 index 0000000000000..64f6b03996fc9 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm7150.c @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "gdsc.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, +}; + +enum { + P_BI_TCXO, + P_VIDEOCC_PLL0_OUT_EVEN, + P_VIDEOCC_PLL0_OUT_MAIN, + P_VIDEOCC_PLL0_OUT_ODD, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, + { 125000000, 1000000000, 1 }, +}; + +static struct alpha_pll_config videocc_pll0_config = { + .l = 0x19, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002067, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00004805, + .test_ctl_hi_val = 0x40000000, +}; + +static struct clk_alpha_pll videocc_pll0 = { + .offset = 0x42c, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "videocc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct parent_map videocc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_VIDEOCC_PLL0_OUT_MAIN, 1 }, + { P_VIDEOCC_PLL0_OUT_EVEN, 2 }, + { P_VIDEOCC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data videocc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &videocc_pll0.clkr.hw }, + { .hw = &videocc_pll0.clkr.hw }, + { .hw = &videocc_pll0.clkr.hw }, +}; + +static const struct parent_map videocc_parent_map_1[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data videocc_parent_data_1[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_videocc_iris_clk_src[] = { + F(240000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0), + F(365000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 videocc_iris_clk_src = { + .cmd_rcgr = 0x7f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_0, + .freq_tbl = ftbl_videocc_iris_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "videocc_iris_clk_src", + .parent_data = videocc_parent_data_0, + .num_parents = ARRAY_SIZE(videocc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_videocc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 videocc_xo_clk_src = { + .cmd_rcgr = 0xa98, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_1, + .freq_tbl = ftbl_videocc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "videocc_xo_clk_src", + .parent_data = videocc_parent_data_1, + .num_parents = ARRAY_SIZE(videocc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch videocc_iris_ahb_clk = { + .halt_reg = 0x8f4, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x8f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_iris_ahb_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &videocc_iris_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs0_axi_clk = { + .halt_reg = 0x9ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_mvs0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs0_core_clk = { + .halt_reg = 0x890, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x890, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_mvs0_core_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &videocc_iris_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs1_axi_clk = { + .halt_reg = 0xa0c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa0c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_mvs1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs1_core_clk = { + .halt_reg = 0x8d0, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x8d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_mvs1_core_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &videocc_iris_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvsc_core_clk = { + .halt_reg = 0x850, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x850, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_mvsc_core_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &videocc_iris_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvsc_ctl_axi_clk = { + .halt_reg = 0x9cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_mvsc_ctl_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_venus_ahb_clk = { + .halt_reg = 0xa6c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xa6c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "videocc_venus_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc venus_gdsc = { + .gdscr = 0x814, + .pd = { + .name = "venus_gdsc", + }, + .cxcs = (unsigned int []){ 0x850, 0x9cc }, + .cxc_count = 2, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + +static struct gdsc vcodec0_gdsc = { + .gdscr = 0x874, + .pd = { + .name = "vcodec0_gdsc", + }, + .cxcs = (unsigned int []){ 0x890, 0x9ec }, + .cxc_count = 2, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc vcodec1_gdsc = { + .gdscr = 0x8b4, + .pd = { + .name = "vcodec1_gdsc", + }, + .cxcs = (unsigned int []){ 0x8d0, 0xa0c }, + .cxc_count = 2, + .flags = HW_CTRL | POLL_CFG_GDSCR, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct clk_regmap *videocc_sm7150_clocks[] = { + [VIDEOCC_PLL0] = &videocc_pll0.clkr, + [VIDEOCC_IRIS_AHB_CLK] = &videocc_iris_ahb_clk.clkr, + [VIDEOCC_IRIS_CLK_SRC] = &videocc_iris_clk_src.clkr, + [VIDEOCC_MVS0_AXI_CLK] = &videocc_mvs0_axi_clk.clkr, + [VIDEOCC_MVS0_CORE_CLK] = &videocc_mvs0_core_clk.clkr, + [VIDEOCC_MVS1_AXI_CLK] = &videocc_mvs1_axi_clk.clkr, + [VIDEOCC_MVS1_CORE_CLK] = &videocc_mvs1_core_clk.clkr, + [VIDEOCC_MVSC_CORE_CLK] = &videocc_mvsc_core_clk.clkr, + [VIDEOCC_MVSC_CTL_AXI_CLK] = &videocc_mvsc_ctl_axi_clk.clkr, + [VIDEOCC_VENUS_AHB_CLK] = &videocc_venus_ahb_clk.clkr, + [VIDEOCC_XO_CLK_SRC] = &videocc_xo_clk_src.clkr, +}; + +static struct gdsc *videocc_sm7150_gdscs[] = { + [VENUS_GDSC] = &venus_gdsc, + [VCODEC0_GDSC] = &vcodec0_gdsc, + [VCODEC1_GDSC] = &vcodec1_gdsc, +}; + +static const struct regmap_config videocc_sm7150_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xb94, + .fast_io = true, +}; + +static const struct qcom_cc_desc videocc_sm7150_desc = { + .config = &videocc_sm7150_regmap_config, + .clks = videocc_sm7150_clocks, + .num_clks = ARRAY_SIZE(videocc_sm7150_clocks), + .gdscs = videocc_sm7150_gdscs, + .num_gdscs = ARRAY_SIZE(videocc_sm7150_gdscs), +}; + +static const struct of_device_id videocc_sm7150_match_table[] = { + { .compatible = "qcom,sm7150-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, videocc_sm7150_match_table); + +static int videocc_sm7150_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &videocc_sm7150_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&videocc_pll0, regmap, &videocc_pll0_config); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x984); /* VIDEOCC_XO_CLK */ + + return qcom_cc_really_probe(pdev, &videocc_sm7150_desc, regmap); +} + +static struct platform_driver videocc_sm7150_driver = { + .probe = videocc_sm7150_probe, + .driver = { + .name = "videocc-sm7150", + .of_match_table = videocc_sm7150_match_table, + }, +}; +module_platform_driver(videocc_sm7150_driver); + +MODULE_DESCRIPTION("Qualcomm SM7150 Video Clock Controller"); +MODULE_LICENSE("GPL"); From 475beea0b9f631656b5cc39429a39696876af613 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Tue, 30 Apr 2024 23:07:43 -0500 Subject: [PATCH 12/61] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Add defines for the missing PCIe PIPE clocks. Signed-off-by: Alexandru Gagniuc Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240501040800.1542805-2-mr.nuke.me@gmail.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa2..52123c5a09fa1 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -216,4 +216,8 @@ #define GCC_CRYPTO_AHB_CLK 207 #define GCC_USB0_PIPE_CLK 208 #define GCC_USB0_SLEEP_CLK 209 +#define GCC_PCIE0_PIPE_CLK 210 +#define GCC_PCIE1_PIPE_CLK 211 +#define GCC_PCIE2_PIPE_CLK 212 +#define GCC_PCIE3_PIPE_CLK 213 #endif From a8fe85d40ffe5ec0fd2f557932ffee902be35b38 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Tue, 30 Apr 2024 23:07:44 -0500 Subject: [PATCH 13/61] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by PCIe PHYs. Port the pipe clocks from the downstream 5.4 kernel. Signed-off-by: Alexandru Gagniuc Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240501040800.1542805-3-mr.nuke.me@gmail.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0a3f846695b80..bc3e17f342954 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x28044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x28044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { @@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { @@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie2_pipe_clk = { + .halt_reg = 0x2a044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2a044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie2_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie2_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { @@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie3_pipe_clk = { + .halt_reg = 0x2b044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2b044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie3_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie3_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(100000000, P_GPLL0, 8, 0, 0), @@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { From 7f10197853006c45e51f17e5f6b2da8d98b60784 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 31 May 2024 15:21:40 +0530 Subject: [PATCH 14/61] clk: qcom: sc7280: Update the transition delay for GDSC Add support to update the GDSC transition delay values to avoid the GDSC FSM state stuck issues without which it could lead to GDSC power on/off failures. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240531095142.9688-2-quic_tdas@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/camcc-sc7280.c | 19 +++++++++++++++++++ drivers/clk/qcom/gcc-sc7280.c | 10 ++++++++++ drivers/clk/qcom/gpucc-sc7280.c | 7 +++++++ drivers/clk/qcom/videocc-sc7280.c | 7 +++++++ 4 files changed, 43 insertions(+) diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index d89ddb2298e32..27bfb0f959c4b 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2247,6 +2248,9 @@ static struct clk_branch cam_cc_sleep_clk = { static struct gdsc cam_cc_titan_top_gdsc = { .gdscr = 0xc194, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_titan_top_gdsc", }, @@ -2256,6 +2260,9 @@ static struct gdsc cam_cc_titan_top_gdsc = { static struct gdsc cam_cc_bps_gdsc = { .gdscr = 0x7004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_bps_gdsc", }, @@ -2265,6 +2272,9 @@ static struct gdsc cam_cc_bps_gdsc = { static struct gdsc cam_cc_ife_0_gdsc = { .gdscr = 0xa004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_0_gdsc", }, @@ -2274,6 +2284,9 @@ static struct gdsc cam_cc_ife_0_gdsc = { static struct gdsc cam_cc_ife_1_gdsc = { .gdscr = 0xb004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_1_gdsc", }, @@ -2283,6 +2296,9 @@ static struct gdsc cam_cc_ife_1_gdsc = { static struct gdsc cam_cc_ife_2_gdsc = { .gdscr = 0xb070, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_2_gdsc", }, @@ -2292,6 +2308,9 @@ static struct gdsc cam_cc_ife_2_gdsc = { static struct gdsc cam_cc_ipe_0_gdsc = { .gdscr = 0x8004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ipe_0_gdsc", }, diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index f45a8318900c5..c622cd9a9d246 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -3094,6 +3095,9 @@ static struct clk_branch gcc_wpss_rscp_clk = { static struct gdsc gcc_pcie_0_gdsc = { .gdscr = 0x6b004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_pcie_0_gdsc", }, @@ -3112,6 +3116,9 @@ static struct gdsc gcc_pcie_1_gdsc = { static struct gdsc gcc_ufs_phy_gdsc = { .gdscr = 0x77004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_ufs_phy_gdsc", }, @@ -3121,6 +3128,9 @@ static struct gdsc gcc_ufs_phy_gdsc = { static struct gdsc gcc_usb30_prim_gdsc = { .gdscr = 0xf004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_usb30_prim_gdsc", }, diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 35b394feb68da..ebda57eac979d 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -379,6 +380,9 @@ static struct clk_branch gpu_cc_sleep_clk = { static struct gdsc cx_gdsc = { .gdscr = 0x106c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .gds_hw_ctrl = 0x1540, .pd = { .name = "cx_gdsc", @@ -389,6 +393,9 @@ static struct gdsc cx_gdsc = { static struct gdsc gx_gdsc = { .gdscr = 0x100c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .clamp_io_ctrl = 0x1508, .pd = { .name = "gx_gdsc", diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c index cdd59c6f60df8..119a3ed6eb6ad 100644 --- a/drivers/clk/qcom/videocc-sc7280.c +++ b/drivers/clk/qcom/videocc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -232,6 +233,9 @@ static struct clk_branch video_cc_venus_ahb_clk = { static struct gdsc mvs0_gdsc = { .gdscr = 0x3004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, .pd = { .name = "mvs0_gdsc", }, @@ -241,6 +245,9 @@ static struct gdsc mvs0_gdsc = { static struct gdsc mvsc_gdsc = { .gdscr = 0x2004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, .pd = { .name = "mvsc_gdsc", }, From f38467b5a920be1473710428a93c4e54b6f8a0c1 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 31 May 2024 15:21:41 +0530 Subject: [PATCH 15/61] clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clock Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. When retention bit of the clock is set the memories of the subsystem will retain the logic across power states. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240531095142.9688-3-quic_tdas@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sc7280.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index c622cd9a9d246..b937d513b8148 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3473,6 +3473,9 @@ static int gcc_sc7280_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) From 63aec3e4d987fd43237f557460345bca3b51e530 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 31 May 2024 15:21:42 +0530 Subject: [PATCH 16/61] clk: qcom: camcc-sc7280: Add parent dependency to all camera GDSCs Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 1daec8cfebc2 ("clk: qcom: camcc: Add camera clock controller driver for SC7280") Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240531095142.9688-4-quic_tdas@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/camcc-sc7280.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index 27bfb0f959c4b..da29d3b953eea 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -2267,6 +2267,7 @@ static struct gdsc cam_cc_bps_gdsc = { .name = "cam_cc_bps_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = HW_CTRL | RETAIN_FF_ENABLE, }; @@ -2279,6 +2280,7 @@ static struct gdsc cam_cc_ife_0_gdsc = { .name = "cam_cc_ife_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = RETAIN_FF_ENABLE, }; @@ -2291,6 +2293,7 @@ static struct gdsc cam_cc_ife_1_gdsc = { .name = "cam_cc_ife_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = RETAIN_FF_ENABLE, }; @@ -2303,6 +2306,7 @@ static struct gdsc cam_cc_ife_2_gdsc = { .name = "cam_cc_ife_2_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = RETAIN_FF_ENABLE, }; @@ -2315,6 +2319,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = { .name = "cam_cc_ipe_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = HW_CTRL | RETAIN_FF_ENABLE, }; From d99c899d2c42a37d331b8ac6f38c025884df15b2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:46:59 +0300 Subject: [PATCH 17/61] dt-bindings: clock: qcom,gcc-other: rename to qcom,mdm-mdm9607 The only platform remaining in qcom,gcc-other.yaml is MDM9607. Drop the stale mentioning of gcc-msm8953.h include and rename the schema file accordingly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-1-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- .../clock/{qcom,gcc-other.yaml => qcom,gcc-mdm9607.yaml} | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) rename Documentation/devicetree/bindings/clock/{qcom,gcc-other.yaml => qcom,gcc-mdm9607.yaml} (87%) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml similarity index 87% rename from Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml rename to Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml index 7d05f0f63cef2..1264f3d557616 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml# +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller @@ -15,7 +15,6 @@ description: | domains. See also:: - include/dt-bindings/clock/qcom,gcc-msm8953.h include/dt-bindings/clock/qcom,gcc-mdm9607.h allOf: From b0ef3434da07e7516a89a80206af53ea81954a80 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:00 +0300 Subject: [PATCH 18/61] dt-bindings: clock: qcom,gcc: sort out power-domains support On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Move requirement for the '#power-domain-cells' out of the common qcom,gcc.yaml into individual schema files. For the platforms that do not provide power-domains, explicitly forbid having the '#power-domain-cells' property. Suggested-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-2-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc.yaml | 1 - Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml | 1 + 46 files changed, 53 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 19211176ee0bf..27df7e3e5bf36 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -69,6 +69,8 @@ properties: const: 1 deprecated: true + '#power-domain-cells': false + required: - compatible @@ -81,7 +83,6 @@ examples: reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; thermal-sensor { compatible = "qcom,msm8960-tsens"; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml index d846082690802..0a0a26d9beab1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -51,6 +51,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml index fb3957d485f9a..012048921f92e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml @@ -34,6 +34,8 @@ properties: - const: xo - const: sleep_clk + '#power-domain-cells': false + required: - compatible @@ -45,7 +47,6 @@ examples: compatible = "qcom,gcc-ipq4019"; reg = <0x1800000 0x60000>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; clocks = <&xo>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml index af5d883cfdc86..4d2614d4f3686 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml @@ -36,6 +36,8 @@ properties: - const: xo - const: sleep_clk + '#power-domain-cells': false + required: - compatible - clocks @@ -51,7 +53,6 @@ examples: clocks = <&xo>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml index 93f3084b97c12..a71557395c014 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -46,6 +46,8 @@ properties: allOf: - $ref: /schemas/thermal/qcom-tsens.yaml# + '#power-domain-cells': false + required: - compatible - clocks @@ -65,7 +67,6 @@ examples: clock-names = "pxo", "cxo", "pll4"; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 2d44ddc45aabb..38b9e42839004 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -39,6 +39,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml index 1264f3d557616..d7da30b0e7ee6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml @@ -27,6 +27,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml index c9e9855486213..e03b6d0acdb6e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml @@ -34,6 +34,8 @@ properties: - const: pxo - const: cxo + '#power-domain-cells': false + required: - compatible @@ -47,7 +49,6 @@ examples: reg = <0x900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; clocks = <&pxo_board>, <&cxo_board>; clock-names = "pxo", "cxo"; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml index b91462587df50..ce1f5a60bd8c9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml @@ -42,6 +42,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml index ad84c0f7680be..258b6b93deca7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml @@ -48,6 +48,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml index fe9fd4cb185f1..fe1f5f3ed9924 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -42,6 +42,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml index 1927aecc86bc4..929fafc84c195 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml @@ -41,6 +41,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml index 62d6f1fe1228a..cd49704dcb95a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml @@ -49,6 +49,7 @@ required: - clocks - clock-names - vdd_gfx-supply + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index 8f0f20c1442ad..6b9c1d198b14d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -35,6 +35,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml index 97523cc1ecfbf..013fd074a8d56 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml @@ -50,6 +50,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml index 58f7fb22c5c4d..abae658c0ed95 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml @@ -38,6 +38,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml index c9bec4656f6eb..38c4c8c61b3af 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml @@ -33,6 +33,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index 7bc6c57e4d11d..94755465c1fb4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -40,6 +40,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml index 7aae21a766908..1847bbeaa9d18 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml @@ -40,6 +40,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml index c4ca08d9ad5af..4e4f68b9f6d28 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml @@ -51,6 +51,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml index a1085ef4fd05a..b4784ecaf58d2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml @@ -40,6 +40,7 @@ required: - clocks - clock-names - power-domains + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml index 5681e535feded..5cfde8a4de4e9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml @@ -65,6 +65,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml index 52e7412aace51..724ce0491118a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml @@ -40,6 +40,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml index 0595da0e8a424..ef0a20456e8a5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml @@ -35,6 +35,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml index 428e954d76384..30819f3d85c62 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -34,6 +34,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml index 523e18d7f1506..9154492286685 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -39,6 +39,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml index a5ad0a3da3979..ecb69c707f09b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml @@ -33,6 +33,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml index 8e37623788bdd..a5a29dc75ae11 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml @@ -33,6 +33,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml index d1b26ab48eaff..2280b859b2ad6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml @@ -35,6 +35,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml index 58ccb7df847cc..1dcf97c0c064e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml @@ -34,6 +34,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml index 5d77c092be5b0..979ff0a8bf686 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -36,6 +36,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml index b4fdde71ef18d..594e87f5ba092 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml @@ -55,6 +55,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml index 75259f468d540..d848361beeb32 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -49,6 +49,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 788825105f24d..513d6fd892494 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -35,7 +35,6 @@ required: - reg - '#clock-cells' - '#reset-cells' - - '#power-domain-cells' additionalProperties: true diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml index ef84a0c95f7ee..489d0fc5607c0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml @@ -33,6 +33,8 @@ properties: - description: UNIPHY RX clock source - description: UNIPHY TX clk source + '#power-domain-cells': false + required: - compatible - clocks @@ -58,6 +60,5 @@ examples: <&uniphy_tx_clk>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 718fe0625424e..adc30d84fa8f0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -30,6 +30,8 @@ properties: - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - description: USB PCIE wrapper pipe clock source + '#power-domain-cells': false + required: - compatible - clocks @@ -47,7 +49,6 @@ examples: <&pcie_2lane_phy_pipe_clk_x1>, <&usb_pcie_wrapper_pipe_clk>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6b..ec349e2794802 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,8 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#power-domain-cells': false + required: - compatible - clocks @@ -57,6 +59,5 @@ examples: <&usb3phy_0_cc_pipe_clk>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index d712b1a87e25f..86befef026506 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -31,6 +31,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml index 0f641c235b138..addbd323fa6d7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml @@ -46,6 +46,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml index 98921fa236b18..567182aba3006 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml @@ -41,6 +41,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml index 5953c8d924367..0ac92d7871e12 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml @@ -32,6 +32,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml index 295d4bb1a9664..147b75a21508f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml @@ -31,6 +31,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml index 0eb76d9d51c4d..4d7bbbf4ce8af 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml @@ -30,6 +30,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml index 0c706de31cf11..d83b64dcce4fa 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml @@ -34,6 +34,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml index b54761cc8674b..976f29cce809c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml @@ -35,6 +35,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 14a796dbf8bc6..5951a60ab0815 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -41,6 +41,7 @@ required: - compatible - clocks - power-domains + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# From e81e9a845bab76461f952b6d81cf599ab957a33a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:01 +0300 Subject: [PATCH 19/61] dt-bindings: clock: add schema for qcom,gcc-mdm9615 Add schema for the Global Clock Controller (GCC) present on the Qualcomm MDM9615 platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-3-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,gcc-mdm9615.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml new file mode 100644 index 0000000000000..418dea31eb62d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains. + + See also:: + include/dt-bindings/clock/qcom,gcc-mdm9615.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-mdm9615 + + clocks: + items: + - description: CXO clock + - description: PLL4 from LLC + + '#power-domain-cells': false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, + <&lcc_pll4>; + }; +... From acc41014661cf424c262e8d532e461376bacbd90 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:28 +0200 Subject: [PATCH 20/61] dt-bindings: clock: qcom,sm8450-videocc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-1-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-videocc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d31..74034e3f79b74 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -21,9 +21,6 @@ properties: - qcom,sm8450-videocc - qcom,sm8550-videocc - reg: - maxItems: 1 - clocks: items: - description: Board XO source @@ -39,26 +36,17 @@ properties: description: A phandle to an OPP node describing required MMCX performance point. - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - required: - compatible - - reg - clocks - power-domains - required-opps - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 3b39fb00be1c5bd0c0c8855444a3b17d04bed667 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:29 +0200 Subject: [PATCH 21/61] dt-bindings: clock: qcom,videocc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-2-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,videocc.yaml | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 6999e36ace1b6..81c68039ac9e1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -37,18 +37,6 @@ properties: minItems: 1 maxItems: 3 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - power-domains: description: A phandle and PM domain specifier for the MMCX power domain. @@ -61,14 +49,13 @@ properties: required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' allOf: + - $ref: qcom,gcc.yaml# + - if: properties: compatible: @@ -119,7 +106,7 @@ allOf: - const: bi_tcxo - const: bi_tcxo_ao -additionalProperties: false +unevaluatedProperties: false examples: - | From cc9d138fffbaebe7c3f37f9e03b2d1840efa2af6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:30 +0200 Subject: [PATCH 22/61] dt-bindings: clock: qcom,dispcc-sc8280xp: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-3-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,dispcc-sc8280xp.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml index 3cb996b2c9d59..ffae037779a11 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml @@ -40,31 +40,19 @@ properties: - description: DSI 1 PLL byte clock - description: DSI 1 PLL DSI clock - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - power-domains: items: - description: MMCX power domain required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From f168430195ff37d1b075d70db95c9bf430ab208b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:31 +0200 Subject: [PATCH 23/61] dt-bindings: clock: qcom,dispcc-sm6350: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-4-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,dispcc-sm6350.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml index 8efac3fb159fe..a584b4953e686 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml @@ -37,28 +37,16 @@ properties: - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 5576b6f8e91fa4b2ff6c48b2810cb8fbe9242142 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:32 +0200 Subject: [PATCH 24/61] dt-bindings: clock: qcom,dispcc-sm8x50: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-5-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0d82521a5433c..53a5ab3191591 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -60,18 +60,6 @@ properties: - const: dptx2_phy_pll_link_clk - const: dptx2_phy_pll_vco_div_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - power-domains: description: A phandle and PM domain specifier for the MMCX power domain. @@ -84,14 +72,12 @@ properties: required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' allOf: + - $ref: qcom,gcc.yaml# - if: not: properties: @@ -105,7 +91,7 @@ allOf: clock-names: maxItems: 7 -additionalProperties: false +unevaluatedProperties: false examples: - | From b20b9a762695835016c2ccc26cf1447dca354c10 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:33 +0200 Subject: [PATCH 25/61] dt-bindings: clock: qcom,gpucc-sdm660: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-6-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,gpucc-sdm660.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml index 0518ea963cdde..79bb90dbe4c1a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml @@ -33,28 +33,16 @@ properties: - const: gcc_gpu_gpll0_clk - const: gcc_gpu_gpll0_div_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From f68872fe10193bb1b033aec0edaadcaab9de2935 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:34 +0200 Subject: [PATCH 26/61] dt-bindings: clock: qcom,gpucc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-7-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index f57aceddac6be..0858fd6352822 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -56,25 +56,10 @@ properties: vdd-gfx-supply: description: Regulator supply for the VDD_GFX pads - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' # Require that power-domains and vdd-gfx-supply are not both present @@ -83,7 +68,10 @@ not: - power-domains - vdd-gfx-supply -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From fa02399d69377a38ce49b7e77ece720c114265bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:35 +0200 Subject: [PATCH 27/61] dt-bindings: clock: qcom,msm8998-gpucc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-8-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,msm8998-gpucc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml index 7b271ae210a35..b9b218ef9b68d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml @@ -29,28 +29,16 @@ properties: - const: xo - const: gpll0 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From a8197afc44a6542631ec999f4b332643c91c79b3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:36 +0200 Subject: [PATCH 28/61] dt-bindings: clock: qcom,qcm2290-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-9-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,qcm2290-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml index 4a00f2d416842..243be4f76db3b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml @@ -37,28 +37,16 @@ properties: - const: dsi0_phy_pll_out_byteclk - const: dsi0_phy_pll_out_dsiclk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From e68a21bd186b2f15bb1106b6fd9ad697b3307ca9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:37 +0200 Subject: [PATCH 29/61] dt-bindings: clock: qcom,sc7180-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-10-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sc7180-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml index 1c9ce300a4352..0d8ea44d8141a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml @@ -37,28 +37,16 @@ properties: - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From c9ae35ace8c420ebcc7bf868a4f0feca142cb5cb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:38 +0200 Subject: [PATCH 30/61] dt-bindings: clock: qcom,sc7280-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-11-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sc7280-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml index c42b0ef61385f..23177661be403 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml @@ -41,28 +41,16 @@ properties: - const: edp_phy_pll_link_clk - const: edp_phy_pll_vco_div_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 4ef61bcf1aa9cdb3d4bb588ed591bbd4e96c3eaf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:39 +0200 Subject: [PATCH 31/61] dt-bindings: clock: qcom,sdm845-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-12-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sdm845-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml index 719844d7ea11a..220f4004f7fdc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -46,28 +46,16 @@ properties: - const: dp_link_clk_divsel_ten - const: dp_vco_divided_clk_src_mux - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 7b69a903fc73188c50577565093a5b3680448c57 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:40 +0200 Subject: [PATCH 32/61] dt-bindings: clock: qcom,sm6115-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-13-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm6115-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml index f802a2e7f8189..00be36683eb5d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml @@ -28,27 +28,15 @@ properties: - description: Pixel clock from DSI PHY0 - description: GPLL0 DISP DIV clock from GCC - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 8acff345c3e6b0c258177ba1db18d07ebd83183c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:41 +0200 Subject: [PATCH 33/61] dt-bindings: clock: qcom,sm8450-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-14-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml index 2f22310b08a9d..4794c53793a89 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml @@ -40,18 +40,6 @@ properties: - description: Link clock from DP PHY3 - description: VCO DIV clock from DP PHY3 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - power-domains: description: A phandle and PM domain specifier for the MMCX power domain. @@ -64,13 +52,13 @@ properties: required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 4da364c759dc66a23a4ea69cb85e038c847b9f0e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:42 +0200 Subject: [PATCH 34/61] dt-bindings: clock: qcom,sm8550-dispcc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-15-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8550-dispcc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index bad0260764d46..c17035a180dbf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -45,18 +45,6 @@ properties: - description: Link clock from DP PHY3 - description: VCO DIV clock from DP PHY3 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - power-domains: description: A phandle and PM domain specifier for the MMCX power domain. @@ -69,13 +57,13 @@ properties: required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 7e828d77d202f59d4f9b59c1930b82433cce1356 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jun 2024 10:09:43 +0200 Subject: [PATCH 35/61] dt-bindings: clock: qcom,sm8450-gpucc: reference qcom,gcc.yaml Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-16-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 20 ++++--------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 36974309cf696..3c2cac14e6c3a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -34,27 +34,15 @@ properties: - description: GPLL0 main branch source - description: GPLL0 div branch source - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From 7311bbfff31c4961c57d94c165fa843f155f8236 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Wed, 5 Jun 2024 20:45:38 +0800 Subject: [PATCH 36/61] clk: qcom: branch: Add clk_branch2_prepare_ops Add the clk_branch2_prepare_ops for supporting clock controller where the hardware register is accessed by MDIO bus, and the spin lock can't be used because of sleep during the MDIO operation. The clock is enabled by the .prepare instead of .enable when the clk_branch2_prepare_ops is used. Acked-by: Stephen Boyd Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20240605124541.2711467-2-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-branch.c | 7 +++++++ drivers/clk/qcom/clk-branch.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index c1dba33ac31af..229480c5b075a 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -191,3 +191,10 @@ const struct clk_ops clk_branch_simple_ops = { .is_enabled = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch_simple_ops); + +const struct clk_ops clk_branch2_prepare_ops = { + .prepare = clk_branch2_enable, + .unprepare = clk_branch2_disable, + .is_prepared = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_prepare_ops); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index f1b3b635ff324..292756435f536 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -109,6 +109,7 @@ extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; extern const struct clk_ops clk_branch2_aon_ops; extern const struct clk_ops clk_branch2_mem_ops; +extern const struct clk_ops clk_branch2_prepare_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr) From 80bbd1c355d661678d2a25bd36e739b6925e7a4e Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Wed, 5 Jun 2024 20:45:39 +0800 Subject: [PATCH 37/61] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions QCA8386/QCA8084 includes the clock & reset controller that is accessed by MDIO bus. Two work modes are supported, qca8386 works as switch mode, qca8084 works as PHY mode. Reviewed-by: Rob Herring Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,qca8k-nsscc.yaml | 86 +++++++++++++++ include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 ++++++++++++++++++ include/dt-bindings/reset/qcom,qca8k-nsscc.h | 76 +++++++++++++ 3 files changed, 263 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml new file mode 100644 index 0000000000000..61473385da2de --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084 + +maintainers: + - Bjorn Andersson + - Luo Jie + +description: | + Qualcomm NSS clock control module provides the clocks and resets + on QCA8386(switch mode)/QCA8084(PHY mode) + + See also:: + include/dt-bindings/clock/qcom,qca8k-nsscc.h + include/dt-bindings/reset/qcom,qca8k-nsscc.h + +properties: + compatible: + oneOf: + - const: qcom,qca8084-nsscc + - items: + - enum: + - qcom,qca8082-nsscc + - qcom,qca8085-nsscc + - qcom,qca8384-nsscc + - qcom,qca8385-nsscc + - qcom,qca8386-nsscc + - const: qcom,qca8084-nsscc + + clocks: + items: + - description: Chip reference clock source + - description: UNIPHY0 RX 312P5M/125M clock source + - description: UNIPHY0 TX 312P5M/125M clock source + - description: UNIPHY1 RX 312P5M/125M clock source + - description: UNIPHY1 TX 312P5M/125M clock source + - description: UNIPHY1 RX 312P5M clock source + - description: UNIPHY1 TX 312P5M clock source + + reg: + items: + - description: MDIO bus address for Clock & Reset Controller register + + reset-gpios: + description: GPIO connected to the chip + maxItems: 1 + +required: + - compatible + - clocks + - reg + - reset-gpios + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + mdio { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@18 { + compatible = "qcom,qca8084-nsscc"; + reg = <0x18>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + clocks = <&pcs0_pll>, + <&qca8k_uniphy0_rx>, + <&qca8k_uniphy0_tx>, + <&qca8k_uniphy1_rx>, + <&qca8k_uniphy1_tx>, + <&qca8k_uniphy1_rx312p5m>, + <&qca8k_uniphy1_tx312p5m>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,qca8k-nsscc.h b/include/dt-bindings/clock/qcom,qca8k-nsscc.h new file mode 100644 index 0000000000000..0ac3e4c69a1a7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qca8k-nsscc.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H +#define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H + +#define NSS_CC_SWITCH_CORE_CLK_SRC 0 +#define NSS_CC_SWITCH_CORE_CLK 1 +#define NSS_CC_APB_BRIDGE_CLK 2 +#define NSS_CC_MAC0_TX_CLK_SRC 3 +#define NSS_CC_MAC0_TX_DIV_CLK_SRC 4 +#define NSS_CC_MAC0_TX_CLK 5 +#define NSS_CC_MAC0_TX_SRDS1_CLK 6 +#define NSS_CC_MAC0_RX_CLK_SRC 7 +#define NSS_CC_MAC0_RX_DIV_CLK_SRC 8 +#define NSS_CC_MAC0_RX_CLK 9 +#define NSS_CC_MAC0_RX_SRDS1_CLK 10 +#define NSS_CC_MAC1_TX_CLK_SRC 11 +#define NSS_CC_MAC1_TX_DIV_CLK_SRC 12 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC 13 +#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK 14 +#define NSS_CC_MAC1_TX_CLK 15 +#define NSS_CC_MAC1_GEPHY0_TX_CLK 16 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK 17 +#define NSS_CC_MAC1_RX_CLK_SRC 18 +#define NSS_CC_MAC1_RX_DIV_CLK_SRC 19 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC 20 +#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK 21 +#define NSS_CC_MAC1_RX_CLK 22 +#define NSS_CC_MAC1_GEPHY0_RX_CLK 23 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK 24 +#define NSS_CC_MAC2_TX_CLK_SRC 25 +#define NSS_CC_MAC2_TX_DIV_CLK_SRC 26 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC 27 +#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK 28 +#define NSS_CC_MAC2_TX_CLK 29 +#define NSS_CC_MAC2_GEPHY1_TX_CLK 30 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK 31 +#define NSS_CC_MAC2_RX_CLK_SRC 32 +#define NSS_CC_MAC2_RX_DIV_CLK_SRC 33 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC 34 +#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK 35 +#define NSS_CC_MAC2_RX_CLK 36 +#define NSS_CC_MAC2_GEPHY1_RX_CLK 37 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK 38 +#define NSS_CC_MAC3_TX_CLK_SRC 39 +#define NSS_CC_MAC3_TX_DIV_CLK_SRC 40 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC 41 +#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK 42 +#define NSS_CC_MAC3_TX_CLK 43 +#define NSS_CC_MAC3_GEPHY2_TX_CLK 44 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK 45 +#define NSS_CC_MAC3_RX_CLK_SRC 46 +#define NSS_CC_MAC3_RX_DIV_CLK_SRC 47 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC 48 +#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK 49 +#define NSS_CC_MAC3_RX_CLK 50 +#define NSS_CC_MAC3_GEPHY2_RX_CLK 51 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK 52 +#define NSS_CC_MAC4_TX_CLK_SRC 53 +#define NSS_CC_MAC4_TX_DIV_CLK_SRC 54 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC 55 +#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK 56 +#define NSS_CC_MAC4_TX_CLK 57 +#define NSS_CC_MAC4_GEPHY3_TX_CLK 58 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK 59 +#define NSS_CC_MAC4_RX_CLK_SRC 60 +#define NSS_CC_MAC4_RX_DIV_CLK_SRC 61 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC 62 +#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK 63 +#define NSS_CC_MAC4_RX_CLK 64 +#define NSS_CC_MAC4_GEPHY3_RX_CLK 65 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK 66 +#define NSS_CC_MAC5_TX_CLK_SRC 67 +#define NSS_CC_MAC5_TX_DIV_CLK_SRC 68 +#define NSS_CC_MAC5_TX_SRDS0_CLK 69 +#define NSS_CC_MAC5_TX_CLK 70 +#define NSS_CC_MAC5_RX_CLK_SRC 71 +#define NSS_CC_MAC5_RX_DIV_CLK_SRC 72 +#define NSS_CC_MAC5_RX_SRDS0_CLK 73 +#define NSS_CC_MAC5_RX_CLK 74 +#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC 75 +#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC 76 +#define NSS_CC_AHB_CLK_SRC 77 +#define NSS_CC_AHB_CLK 78 +#define NSS_CC_SEC_CTRL_AHB_CLK 79 +#define NSS_CC_TLMM_CLK 80 +#define NSS_CC_TLMM_AHB_CLK 81 +#define NSS_CC_CNOC_AHB_CLK 82 +#define NSS_CC_MDIO_AHB_CLK 83 +#define NSS_CC_MDIO_MASTER_AHB_CLK 84 +#define NSS_CC_SYS_CLK_SRC 85 +#define NSS_CC_SRDS0_SYS_CLK 86 +#define NSS_CC_SRDS1_SYS_CLK 87 +#define NSS_CC_GEPHY0_SYS_CLK 88 +#define NSS_CC_GEPHY1_SYS_CLK 89 +#define NSS_CC_GEPHY2_SYS_CLK 90 +#define NSS_CC_GEPHY3_SYS_CLK 91 +#endif diff --git a/include/dt-bindings/reset/qcom,qca8k-nsscc.h b/include/dt-bindings/reset/qcom,qca8k-nsscc.h new file mode 100644 index 0000000000000..c71167a3bd414 --- /dev/null +++ b/include/dt-bindings/reset/qcom,qca8k-nsscc.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H +#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H + +#define NSS_CC_SWITCH_CORE_ARES 1 +#define NSS_CC_APB_BRIDGE_ARES 2 +#define NSS_CC_MAC0_TX_ARES 3 +#define NSS_CC_MAC0_TX_SRDS1_ARES 4 +#define NSS_CC_MAC0_RX_ARES 5 +#define NSS_CC_MAC0_RX_SRDS1_ARES 6 +#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7 +#define NSS_CC_MAC1_TX_ARES 8 +#define NSS_CC_MAC1_GEPHY0_TX_ARES 9 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10 +#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11 +#define NSS_CC_MAC1_RX_ARES 12 +#define NSS_CC_MAC1_GEPHY0_RX_ARES 13 +#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14 +#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15 +#define NSS_CC_MAC2_TX_ARES 16 +#define NSS_CC_MAC2_GEPHY1_TX_ARES 17 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18 +#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19 +#define NSS_CC_MAC2_RX_ARES 20 +#define NSS_CC_MAC2_GEPHY1_RX_ARES 21 +#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22 +#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23 +#define NSS_CC_MAC3_TX_ARES 24 +#define NSS_CC_MAC3_GEPHY2_TX_ARES 25 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26 +#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27 +#define NSS_CC_MAC3_RX_ARES 28 +#define NSS_CC_MAC3_GEPHY2_RX_ARES 29 +#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30 +#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31 +#define NSS_CC_MAC4_TX_ARES 32 +#define NSS_CC_MAC4_GEPHY3_TX_ARES 33 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34 +#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35 +#define NSS_CC_MAC4_RX_ARES 36 +#define NSS_CC_MAC4_GEPHY3_RX_ARES 37 +#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38 +#define NSS_CC_MAC5_TX_ARES 39 +#define NSS_CC_MAC5_TX_SRDS0_ARES 40 +#define NSS_CC_MAC5_RX_ARES 41 +#define NSS_CC_MAC5_RX_SRDS0_ARES 42 +#define NSS_CC_AHB_ARES 43 +#define NSS_CC_SEC_CTRL_AHB_ARES 44 +#define NSS_CC_TLMM_ARES 45 +#define NSS_CC_TLMM_AHB_ARES 46 +#define NSS_CC_CNOC_AHB_ARES 47 +#define NSS_CC_MDIO_AHB_ARES 48 +#define NSS_CC_MDIO_MASTER_AHB_ARES 49 +#define NSS_CC_SRDS0_SYS_ARES 50 +#define NSS_CC_SRDS1_SYS_ARES 51 +#define NSS_CC_GEPHY0_SYS_ARES 52 +#define NSS_CC_GEPHY1_SYS_ARES 53 +#define NSS_CC_GEPHY2_SYS_ARES 54 +#define NSS_CC_GEPHY3_SYS_ARES 55 +#define NSS_CC_SEC_CTRL_ARES 56 +#define NSS_CC_SEC_CTRL_SENSE_ARES 57 +#define NSS_CC_SLEEP_ARES 58 +#define NSS_CC_DEBUG_ARES 59 +#define NSS_CC_GEPHY0_ARES 60 +#define NSS_CC_GEPHY1_ARES 61 +#define NSS_CC_GEPHY2_ARES 62 +#define NSS_CC_GEPHY3_ARES 63 +#define NSS_CC_DSP_ARES 64 +#define NSS_CC_GEPHY_FULL_ARES 65 +#define NSS_CC_GLOBAL_ARES 66 +#define NSS_CC_XPCS_ARES 67 +#endif From 9f93a0a428606341da25bf2a00244701b58e08b9 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Wed, 5 Jun 2024 20:45:40 +0800 Subject: [PATCH 38/61] clk: qcom: common: commonize qcom_cc_really_probe The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by: Stephen Boyd Tested-by: Bryan O'Donoghue Reviewed-by: Bryan O'Donoghue Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20240605124541.2711467-4-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/apss-ipq6018.c | 2 +- drivers/clk/qcom/camcc-sc7180.c | 2 +- drivers/clk/qcom/camcc-sc7280.c | 2 +- drivers/clk/qcom/camcc-sc8280xp.c | 2 +- drivers/clk/qcom/camcc-sdm845.c | 2 +- drivers/clk/qcom/camcc-sm6350.c | 2 +- drivers/clk/qcom/camcc-sm7150.c | 2 +- drivers/clk/qcom/camcc-sm8250.c | 2 +- drivers/clk/qcom/camcc-sm8450.c | 2 +- drivers/clk/qcom/camcc-sm8550.c | 2 +- drivers/clk/qcom/camcc-x1e80100.c | 2 +- drivers/clk/qcom/common.c | 7 +++---- drivers/clk/qcom/common.h | 2 +- drivers/clk/qcom/dispcc-qcm2290.c | 2 +- drivers/clk/qcom/dispcc-sc7180.c | 2 +- drivers/clk/qcom/dispcc-sc7280.c | 2 +- drivers/clk/qcom/dispcc-sc8280xp.c | 2 +- drivers/clk/qcom/dispcc-sdm845.c | 2 +- drivers/clk/qcom/dispcc-sm6115.c | 2 +- drivers/clk/qcom/dispcc-sm6125.c | 2 +- drivers/clk/qcom/dispcc-sm6350.c | 2 +- drivers/clk/qcom/dispcc-sm6375.c | 2 +- drivers/clk/qcom/dispcc-sm7150.c | 2 +- drivers/clk/qcom/dispcc-sm8250.c | 2 +- drivers/clk/qcom/dispcc-sm8450.c | 2 +- drivers/clk/qcom/dispcc-sm8550.c | 2 +- drivers/clk/qcom/dispcc-sm8650.c | 2 +- drivers/clk/qcom/dispcc-x1e80100.c | 2 +- drivers/clk/qcom/ecpricc-qdu1000.c | 2 +- drivers/clk/qcom/gcc-ipq5018.c | 2 +- drivers/clk/qcom/gcc-ipq6018.c | 2 +- drivers/clk/qcom/gcc-ipq8074.c | 2 +- drivers/clk/qcom/gcc-mdm9607.c | 2 +- drivers/clk/qcom/gcc-mdm9615.c | 2 +- drivers/clk/qcom/gcc-msm8917.c | 2 +- drivers/clk/qcom/gcc-msm8939.c | 2 +- drivers/clk/qcom/gcc-msm8953.c | 2 +- drivers/clk/qcom/gcc-msm8976.c | 2 +- drivers/clk/qcom/gcc-msm8996.c | 2 +- drivers/clk/qcom/gcc-msm8998.c | 2 +- drivers/clk/qcom/gcc-qcm2290.c | 2 +- drivers/clk/qcom/gcc-qcs404.c | 2 +- drivers/clk/qcom/gcc-qdu1000.c | 2 +- drivers/clk/qcom/gcc-sa8775p.c | 2 +- drivers/clk/qcom/gcc-sc7180.c | 2 +- drivers/clk/qcom/gcc-sc7280.c | 2 +- drivers/clk/qcom/gcc-sc8180x.c | 2 +- drivers/clk/qcom/gcc-sc8280xp.c | 2 +- drivers/clk/qcom/gcc-sdm660.c | 2 +- drivers/clk/qcom/gcc-sdm845.c | 2 +- drivers/clk/qcom/gcc-sdx55.c | 2 +- drivers/clk/qcom/gcc-sdx65.c | 2 +- drivers/clk/qcom/gcc-sdx75.c | 2 +- drivers/clk/qcom/gcc-sm4450.c | 2 +- drivers/clk/qcom/gcc-sm6115.c | 2 +- drivers/clk/qcom/gcc-sm6125.c | 2 +- drivers/clk/qcom/gcc-sm6350.c | 2 +- drivers/clk/qcom/gcc-sm6375.c | 2 +- drivers/clk/qcom/gcc-sm7150.c | 2 +- drivers/clk/qcom/gcc-sm8150.c | 2 +- drivers/clk/qcom/gcc-sm8250.c | 2 +- drivers/clk/qcom/gcc-sm8350.c | 2 +- drivers/clk/qcom/gcc-sm8450.c | 2 +- drivers/clk/qcom/gcc-sm8550.c | 2 +- drivers/clk/qcom/gcc-sm8650.c | 2 +- drivers/clk/qcom/gcc-x1e80100.c | 2 +- drivers/clk/qcom/gpucc-msm8998.c | 2 +- drivers/clk/qcom/gpucc-sa8775p.c | 2 +- drivers/clk/qcom/gpucc-sc7180.c | 2 +- drivers/clk/qcom/gpucc-sc7280.c | 2 +- drivers/clk/qcom/gpucc-sc8280xp.c | 2 +- drivers/clk/qcom/gpucc-sdm660.c | 2 +- drivers/clk/qcom/gpucc-sdm845.c | 2 +- drivers/clk/qcom/gpucc-sm6115.c | 2 +- drivers/clk/qcom/gpucc-sm6125.c | 2 +- drivers/clk/qcom/gpucc-sm6350.c | 2 +- drivers/clk/qcom/gpucc-sm6375.c | 2 +- drivers/clk/qcom/gpucc-sm8150.c | 2 +- drivers/clk/qcom/gpucc-sm8250.c | 2 +- drivers/clk/qcom/gpucc-sm8350.c | 2 +- drivers/clk/qcom/gpucc-sm8450.c | 2 +- drivers/clk/qcom/gpucc-sm8550.c | 2 +- drivers/clk/qcom/gpucc-sm8650.c | 2 +- drivers/clk/qcom/gpucc-x1e80100.c | 2 +- drivers/clk/qcom/lcc-ipq806x.c | 2 +- drivers/clk/qcom/lcc-msm8960.c | 2 +- drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 ++-- drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +- drivers/clk/qcom/lpasscorecc-sc7280.c | 2 +- drivers/clk/qcom/mmcc-msm8960.c | 2 +- drivers/clk/qcom/mmcc-msm8974.c | 2 +- drivers/clk/qcom/mmcc-msm8994.c | 2 +- drivers/clk/qcom/mmcc-msm8996.c | 2 +- drivers/clk/qcom/mmcc-msm8998.c | 2 +- drivers/clk/qcom/mmcc-sdm660.c | 2 +- drivers/clk/qcom/tcsrcc-sm8550.c | 2 +- drivers/clk/qcom/videocc-sc7180.c | 2 +- drivers/clk/qcom/videocc-sc7280.c | 2 +- drivers/clk/qcom/videocc-sdm845.c | 2 +- drivers/clk/qcom/videocc-sm7150.c | 2 +- drivers/clk/qcom/videocc-sm8150.c | 2 +- drivers/clk/qcom/videocc-sm8250.c | 2 +- drivers/clk/qcom/videocc-sm8350.c | 2 +- drivers/clk/qcom/videocc-sm8450.c | 2 +- drivers/clk/qcom/videocc-sm8550.c | 2 +- 105 files changed, 108 insertions(+), 109 deletions(-) diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c index e6295b832686c..c89d126ebac3c 100644 --- a/drivers/clk/qcom/apss-ipq6018.c +++ b/drivers/clk/qcom/apss-ipq6018.c @@ -123,7 +123,7 @@ static int apss_ipq6018_probe(struct platform_device *pdev) if (!regmap) return -ENODEV; - ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &apss_ipq6018_desc, regmap); if (ret) return ret; diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index a78808b22b030..10e924cd533d1 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -1680,7 +1680,7 @@ static int cam_cc_sc7180_probe(struct platform_device *pdev) clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7180_desc, regmap); pm_runtime_put(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index da29d3b953eea..accd257632df3 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -2481,7 +2481,7 @@ static int cam_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7280_desc, regmap); } static struct platform_driver cam_cc_sc7280_driver = { diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c index d8de924a878a9..479964f916086 100644 --- a/drivers/clk/qcom/camcc-sc8280xp.c +++ b/drivers/clk/qcom/camcc-sc8280xp.c @@ -3034,7 +3034,7 @@ static int camcc_sc8280xp_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ - ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &camcc_sc8280xp_desc, regmap); if (ret) goto err_disable; diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index 8466d03e0d058..40022a10f8c0b 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -1735,7 +1735,7 @@ static int cam_cc_sdm845_probe(struct platform_device *pdev) cam_cc_pll_config.l = 0x14; clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config); - return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &cam_cc_sdm845_desc, regmap); } static struct platform_driver cam_cc_sdm845_driver = { diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c index c6fe684aa780d..f6634cc8663ef 100644 --- a/drivers/clk/qcom/camcc-sm6350.c +++ b/drivers/clk/qcom/camcc-sm6350.c @@ -1879,7 +1879,7 @@ static int camcc_sm6350_probe(struct platform_device *pdev) clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); - return qcom_cc_really_probe(pdev, &camcc_sm6350_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap); } static struct platform_driver camcc_sm6350_driver = { diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c index a81ce6ab8cd52..39033a6bb6160 100644 --- a/drivers/clk/qcom/camcc-sm7150.c +++ b/drivers/clk/qcom/camcc-sm7150.c @@ -2044,7 +2044,7 @@ static int camcc_sm7150_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */ - return qcom_cc_really_probe(pdev, &camcc_sm7150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &camcc_sm7150_desc, regmap); } static struct platform_driver camcc_sm7150_driver = { diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c index 96103eeda5864..34d2f17520dcc 100644 --- a/drivers/clk/qcom/camcc-sm8250.c +++ b/drivers/clk/qcom/camcc-sm8250.c @@ -2433,7 +2433,7 @@ static int cam_cc_sm8250_probe(struct platform_device *pdev) clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8250_desc, regmap); } static struct platform_driver cam_cc_sm8250_driver = { diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c index 51338a2884d2e..26b78eed15efd 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -2839,7 +2839,7 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); - return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap); } static struct platform_driver cam_cc_sm8450_driver = { diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c index 1ef59a96f664f..eac850bb690a2 100644 --- a/drivers/clk/qcom/camcc-sm8550.c +++ b/drivers/clk/qcom/camcc-sm8550.c @@ -3540,7 +3540,7 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ - ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c index 46bb225906bff..85e76c7712ad8 100644 --- a/drivers/clk/qcom/camcc-x1e80100.c +++ b/drivers/clk/qcom/camcc-x1e80100.c @@ -2466,7 +2466,7 @@ static int cam_cc_x1e80100_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ - ret = qcom_cc_really_probe(pdev, &cam_cc_x1e80100_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_x1e80100_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 1e79f05d52265..c92e10c603222 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -252,11 +252,10 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } -int qcom_cc_really_probe(struct platform_device *pdev, +int qcom_cc_really_probe(struct device *dev, const struct qcom_cc_desc *desc, struct regmap *regmap) { int i, ret; - struct device *dev = &pdev->dev; struct qcom_reset_controller *reset; struct qcom_cc *cc; struct gdsc_desc *scd; @@ -333,7 +332,7 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) if (IS_ERR(regmap)) return PTR_ERR(regmap); - return qcom_cc_really_probe(pdev, desc, regmap); + return qcom_cc_really_probe(&pdev->dev, desc, regmap); } EXPORT_SYMBOL_GPL(qcom_cc_probe); @@ -351,7 +350,7 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index, if (IS_ERR(regmap)) return PTR_ERR(regmap); - return qcom_cc_really_probe(pdev, desc, regmap); + return qcom_cc_really_probe(&pdev->dev, desc, regmap); } EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 2d4a8a837e6ce..d048bdeeba109 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -60,7 +60,7 @@ extern int qcom_cc_register_sleep_clk(struct device *dev); extern struct regmap *qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc); -extern int qcom_cc_really_probe(struct platform_device *pdev, +extern int qcom_cc_really_probe(struct device *dev, const struct qcom_cc_desc *desc, struct regmap *regmap); extern int qcom_cc_probe(struct platform_device *pdev, diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index 654a10d53e5c5..449ffea2295d3 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -522,7 +522,7 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); return ret; diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 38d7859981c7d..4710247be5306 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -713,7 +713,7 @@ static int disp_cc_sc7180_probe(struct platform_device *pdev) clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config); - return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7180_desc, regmap); } static struct platform_driver disp_cc_sc7180_driver = { diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c index fbeb8fccb99af..db0745954894d 100644 --- a/drivers/clk/qcom/dispcc-sc7280.c +++ b/drivers/clk/qcom/dispcc-sc7280.c @@ -881,7 +881,7 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */ - return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap); } static struct platform_driver disp_cc_sc7280_driver = { diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c index 91172f5b2f15b..f1ca9ae0b33f4 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3172,7 +3172,7 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev) clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config); clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config); - ret = qcom_cc_really_probe(pdev, desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register display clock controller\n"); goto out_pm_runtime_put; diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index b84fdd17c3d8c..e6139e8f74dc0 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -863,7 +863,7 @@ static int disp_cc_sdm845_probe(struct platform_device *pdev) /* Enable hardware clock gating for DSI and MDP clocks */ regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0); - return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sdm845_desc, regmap); } static struct platform_driver disp_cc_sdm845_driver = { diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index bd07f26af35a2..939887f82ecc3 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -586,7 +586,7 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6115_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); return ret; diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c index 85e07731cce2a..51c7492816fbd 100644 --- a/drivers/clk/qcom/dispcc-sm6125.c +++ b/drivers/clk/qcom/dispcc-sm6125.c @@ -682,7 +682,7 @@ static int disp_cc_sm6125_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6125_desc, regmap); } static struct platform_driver disp_cc_sm6125_driver = { diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c index f712cbef94564..50facb36701af 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -761,7 +761,7 @@ static int disp_cc_sm6350_probe(struct platform_device *pdev) clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6350_desc, regmap); } static struct platform_driver disp_cc_sm6350_driver = { diff --git a/drivers/clk/qcom/dispcc-sm6375.c b/drivers/clk/qcom/dispcc-sm6375.c index 2d42f85f184b8..167dd369a7943 100644 --- a/drivers/clk/qcom/dispcc-sm6375.c +++ b/drivers/clk/qcom/dispcc-sm6375.c @@ -583,7 +583,7 @@ static int disp_cc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6375_desc, regmap); } static struct platform_driver disp_cc_sm6375_driver = { diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c index 5c8ae95b67636..d32bd7df1433b 100644 --- a/drivers/clk/qcom/dispcc-sm7150.c +++ b/drivers/clk/qcom/dispcc-sm7150.c @@ -989,7 +989,7 @@ static int dispcc_sm7150_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x605c); /* DISPCC_XO_CLK */ - return qcom_cc_really_probe(pdev, &dispcc_sm7150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &dispcc_sm7150_desc, regmap); } static struct platform_driver dispcc_sm7150_driver = { diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 43307c8a342ca..5a09009b72891 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1366,7 +1366,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 5d028871624e9..d1d3f60789ee0 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1778,7 +1778,7 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap); if (ret) goto err_put_rpm; diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 88f9347ab77c2..31ae46f180a5c 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1771,7 +1771,7 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap); if (ret) goto err_put_rpm; diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index c0e1ea63166b4..c9d2751f5cb8c 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -1768,7 +1768,7 @@ static int disp_cc_sm8650_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8650_desc, regmap); if (ret) goto err_put_rpm; diff --git a/drivers/clk/qcom/dispcc-x1e80100.c b/drivers/clk/qcom/dispcc-x1e80100.c index 0b2ee6456762d..40069eba41f24 100644 --- a/drivers/clk/qcom/dispcc-x1e80100.c +++ b/drivers/clk/qcom/dispcc-x1e80100.c @@ -1680,7 +1680,7 @@ static int disp_cc_x1e80100_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0xe074); /* DISP_CC_SLEEP_CLK */ qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &disp_cc_x1e80100_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_x1e80100_desc, regmap); if (ret) goto err_put_rpm; diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-qdu1000.c index c628054a70251..dbc11260479b6 100644 --- a/drivers/clk/qcom/ecpricc-qdu1000.c +++ b/drivers/clk/qcom/ecpricc-qdu1000.c @@ -2439,7 +2439,7 @@ static int ecpri_cc_qdu1000_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&ecpri_cc_pll0, regmap, &ecpri_cc_pll0_config); clk_lucid_evo_pll_configure(&ecpri_cc_pll1, regmap, &ecpri_cc_pll1_config); - return qcom_cc_really_probe(pdev, &ecpri_cc_qdu1000_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &ecpri_cc_qdu1000_desc, regmap); } static struct platform_driver ecpri_cc_qdu1000_driver = { diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index c1732d70e3a23..70f5dcb96700f 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3698,7 +3698,7 @@ static int gcc_ipq5018_probe(struct platform_device *pdev) clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); - return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &ipq5018_desc, regmap); } static struct platform_driver gcc_ipq5018_driver = { diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 7e69de34c310c..9e58851013663 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -4642,7 +4642,7 @@ static int gcc_ipq6018_probe(struct platform_device *pdev) clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); - return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_ipq6018_desc, regmap); } static struct platform_driver gcc_ipq6018_driver = { diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index d2be56c5892d0..32fd01ef469a0 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4760,7 +4760,7 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); - return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = { diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c index fb290e73ce948..6e6068b168e66 100644 --- a/drivers/clk/qcom/gcc-mdm9607.c +++ b/drivers/clk/qcom/gcc-mdm9607.c @@ -1604,7 +1604,7 @@ static int gcc_mdm9607_probe(struct platform_device *pdev) /* Vote for GPLL0 to turn on. Needed by acpuclock. */ regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9607_desc, regmap); } static struct platform_driver gcc_mdm9607_driver = { diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index aec7c4a1d3dea..33987b9577371 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -1736,7 +1736,7 @@ static int gcc_mdm9615_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9615_desc, regmap); } static struct platform_driver gcc_mdm9615_driver = { diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c index f2b8729e4198d..3e2a2ae2ee6e9 100644 --- a/drivers/clk/qcom/gcc-msm8917.c +++ b/drivers/clk/qcom/gcc-msm8917.c @@ -3270,7 +3270,7 @@ static int gcc_msm8917_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config); - return qcom_cc_really_probe(pdev, gcc_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap); } static const struct of_device_id gcc_msm8917_match_table[] = { diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 7b9a3e99b5892..7431c9a65044f 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -4108,7 +4108,7 @@ static int gcc_msm8939_probe(struct platform_device *pdev) clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true); clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true); - return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_msm8939_desc, regmap); } static struct platform_driver gcc_msm8939_driver = { diff --git a/drivers/clk/qcom/gcc-msm8953.c b/drivers/clk/qcom/gcc-msm8953.c index 7563bff581186..855a61966f3ef 100644 --- a/drivers/clk/qcom/gcc-msm8953.c +++ b/drivers/clk/qcom/gcc-msm8953.c @@ -4220,7 +4220,7 @@ static int gcc_msm8953_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config); - return qcom_cc_really_probe(pdev, &gcc_msm8953_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_msm8953_desc, regmap); } static const struct of_device_id gcc_msm8953_match_table[] = { diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c index 7fac0ca594aaf..399f22033c29c 100644 --- a/drivers/clk/qcom/gcc-msm8976.c +++ b/drivers/clk/qcom/gcc-msm8976.c @@ -4129,7 +4129,7 @@ static int gcc_msm8976_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_msm8976_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_msm8976_desc, regmap); } static struct platform_driver gcc_msm8976_driver = { diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index e7b03a17514a5..4fc667b94cf23 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -3620,7 +3620,7 @@ static int gcc_msm8996_probe(struct platform_device *pdev) */ regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); - return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_msm8996_desc, regmap); } static struct platform_driver gcc_msm8996_driver = { diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 5f8c87c1793f3..90b66caba2cdf 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -3292,7 +3292,7 @@ static int gcc_msm8998_probe(struct platform_device *pdev) regmap_write(regmap, GCC_MMSS_MISC, 0x10003); regmap_write(regmap, GCC_GPU_MISC, 0x10003); - return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_msm8998_desc, regmap); } static const struct of_device_id gcc_msm8998_match_table[] = { diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 48995e50c6bd7..9a6703365e619 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -2994,7 +2994,7 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); - return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_qcm2290_desc, regmap); } static struct platform_driver gcc_qcm2290_driver = { diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index a39c4990b29db..c3cfd572e7c1e 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2824,7 +2824,7 @@ static int gcc_qcs404_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config); - return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_qcs404_desc, regmap); } static struct platform_driver gcc_qcs404_driver = { diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 9f42d2601464e..dbe9e9437939a 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -2674,7 +2674,7 @@ static int gcc_qdu1000_probe(struct platform_device *pdev) if (ret) return ret; - ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &gcc_qdu1000_desc, regmap); if (ret) return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n"); diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 5bcbfbf52cb9e..9f31ce4cea18b 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4753,7 +4753,7 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ - return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap); } static struct platform_driver gcc_sa8775p_driver = { diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index 6a5f785c0ced0..4a49ad7a9e5be 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -2458,7 +2458,7 @@ static int gcc_sc7180_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sc7180_desc, regmap); } static struct platform_driver gcc_sc7180_driver = { diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index b937d513b8148..4502926a2691a 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3481,7 +3481,7 @@ static int gcc_sc7280_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sc7280_desc, regmap); } static struct platform_driver gcc_sc7280_driver = { diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index ad905affd3766..ad135bfa4c768 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4623,7 +4623,7 @@ static int gcc_sc8180x_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap); } static struct platform_driver gcc_sc8180x_driver = { diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 082d7b5504ebb..5f11760cf73fa 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7558,7 +7558,7 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) if (ret) goto err_put_rpm; - ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &gcc_sc8280xp_desc, regmap); if (ret) goto err_put_rpm; diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index c4fe70871b6d4..df79298a1a253 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -2474,7 +2474,7 @@ static int gcc_sdm660_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sdm660_desc, regmap); } static struct platform_driver gcc_sdm660_driver = { diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index ea4c3bf4fb9bf..dc3aa7014c3ed 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -4011,7 +4011,7 @@ static int gcc_sdm845_probe(struct platform_device *pdev) return ret; gcc_desc = of_device_get_match_data(&pdev->dev); - return qcom_cc_really_probe(pdev, gcc_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap); } static struct platform_driver gcc_sdm845_driver = { diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index 26279b8d321a3..84c507656e8fe 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -1616,7 +1616,7 @@ static int gcc_sdx55_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ - return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sdx55_desc, regmap); } static struct platform_driver gcc_sdx55_driver = { diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c index 8fde6463574b9..fe297c606f97a 100644 --- a/drivers/clk/qcom/gcc-sdx65.c +++ b/drivers/clk/qcom/gcc-sdx65.c @@ -1580,7 +1580,7 @@ static int gcc_sdx65_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ - return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sdx65_desc, regmap); } static struct platform_driver gcc_sdx65_driver = { diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c index c51338f08ef16..453a6bf8e8786 100644 --- a/drivers/clk/qcom/gcc-sdx75.c +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -2940,7 +2940,7 @@ static int gcc_sdx75_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ - return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sdx75_desc, regmap); } static struct platform_driver gcc_sdx75_driver = { diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c index 062e55e981569..e2d9e4691c5b7 100644 --- a/drivers/clk/qcom/gcc-sm4450.c +++ b/drivers/clk/qcom/gcc-sm4450.c @@ -2861,7 +2861,7 @@ static int gcc_sm4450_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); - return qcom_cc_really_probe(pdev, &gcc_sm4450_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm4450_desc, regmap); } static struct platform_driver gcc_sm4450_driver = { diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 167e344ad3996..4c3804701e243 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -3513,7 +3513,7 @@ static int gcc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); - return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm6115_desc, regmap); } static struct platform_driver gcc_sm6115_driver = { diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c index da554efee2ce8..07bb1e5c4a303 100644 --- a/drivers/clk/qcom/gcc-sm6125.c +++ b/drivers/clk/qcom/gcc-sm6125.c @@ -4161,7 +4161,7 @@ static int gcc_sm6125_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm6125_desc, regmap); } static struct platform_driver gcc_sm6125_driver = { diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c index cf4a7b6e0b23a..0dcc8eeb77e69 100644 --- a/drivers/clk/qcom/gcc-sm6350.c +++ b/drivers/clk/qcom/gcc-sm6350.c @@ -2559,7 +2559,7 @@ static int gcc_sm6350_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm6350_desc, regmap); } static struct platform_driver gcc_sm6350_driver = { diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index ac1ed2d728f91..f47dc2808095e 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -3892,7 +3892,7 @@ static int gcc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); - return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm6375_desc, regmap); } static struct platform_driver gcc_sm6375_driver = { diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index b0c50ebb86bed..7eabaf0e1b57d 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -3017,7 +3017,7 @@ static int gcc_sm7150_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm7150_desc, regmap); } static struct platform_driver gcc_sm7150_driver = { diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 1f748141d12c6..cefceb780889e 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3797,7 +3797,7 @@ static int gcc_sm8150_probe(struct platform_device *pdev) if (ret) dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n"); - return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8150_desc, regmap); } static struct platform_driver gcc_sm8150_driver = { diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index e630bfa2d0c17..991cd8b8d5972 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -3656,7 +3656,7 @@ static int gcc_sm8250_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8250_desc, regmap); } static struct platform_driver gcc_sm8250_driver = { diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index fc0402e8a2a75..2d94f3046b711 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -3822,7 +3822,7 @@ static int gcc_sm8350_probe(struct platform_device *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); - return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8350_desc, regmap); } static struct platform_driver gcc_sm8350_driver = { diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index e86c58bc5e48b..639a9a955914f 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -3289,7 +3289,7 @@ static int gcc_sm8450_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ - return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8450_desc, regmap); } static struct platform_driver gcc_sm8450_driver = { diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 26d7349e76424..7944ddb4b47dc 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3364,7 +3364,7 @@ static int gcc_sm8550_probe(struct platform_device *pdev) /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52024, 0x0); - return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8550_desc, regmap); } static struct platform_driver gcc_sm8550_driver = { diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index 9d1cbdf860fb3..9bc19bea0c97c 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3822,7 +3822,7 @@ static int gcc_sm8650_probe(struct platform_device *pdev) /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52150, 0x0); - return qcom_cc_really_probe(pdev, &gcc_sm8650_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm8650_desc, regmap); } static struct platform_driver gcc_sm8650_driver = { diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c index 1404017be9180..eb7e36ebd7ae5 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -6781,7 +6781,7 @@ static int gcc_x1e80100_probe(struct platform_device *pdev) /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52224, 0x0); - return qcom_cc_really_probe(pdev, &gcc_x1e80100_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap); } static struct platform_driver gcc_x1e80100_driver = { diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c index 7b1cb44e31b21..9efeab2691ba9 100644 --- a/drivers/clk/qcom/gpucc-msm8998.c +++ b/drivers/clk/qcom/gpucc-msm8998.c @@ -334,7 +334,7 @@ static int gpucc_msm8998_probe(struct platform_device *pdev) /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */ regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); - return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpucc_msm8998_desc, regmap); } static struct platform_driver gpucc_msm8998_driver = { diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c index 1167c42da39db..ac7552b146c77 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -598,7 +598,7 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sa8775p_desc, regmap); } static struct platform_driver gpu_cc_sa8775p_driver = { diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index 66f5b48cbf879..08f3983d016f3 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -241,7 +241,7 @@ static int gpu_cc_sc7180_probe(struct platform_device *pdev) value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; regmap_update_bits(regmap, 0x1098, mask, value); - return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7180_desc, regmap); } static struct platform_driver gpu_cc_sc7180_driver = { diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index ebda57eac979d..bd699a6245178 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -469,7 +469,7 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */ regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); - return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7280_desc, regmap); } static struct platform_driver gpu_cc_sc7280_driver = { diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 3611d2d1823db..c96be61e3f479 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -449,7 +449,7 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ - ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc8280xp_desc, regmap); pm_runtime_put(&pdev->dev); return ret; diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index a52d98b7cf4c2..3ae1b80e38d9a 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -330,7 +330,7 @@ static int gpucc_sdm660_probe(struct platform_device *pdev) gpu_pll_config.alpha_hi = 0x8a; clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config); - return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpucc_sdm660_desc, regmap); } static struct platform_driver gpucc_sdm660_driver = { diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index c87c3215dfe35..ef26690cf5042 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -192,7 +192,7 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev) value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; regmap_update_bits(regmap, 0x1098, mask, value); - return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap); } static struct platform_driver gpu_cc_sdm845_driver = { diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index 9793dd9a25967..d43c86cf73a52 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -488,7 +488,7 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); - return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6115_desc, regmap); } static struct platform_driver gpu_cc_sm6115_driver = { diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c index b719a48fe706c..ed6a6e505801e 100644 --- a/drivers/clk/qcom/gpucc-sm6125.c +++ b/drivers/clk/qcom/gpucc-sm6125.c @@ -409,7 +409,7 @@ static int gpu_cc_sm6125_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); - return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6125_desc, regmap); } static struct platform_driver gpu_cc_sm6125_driver = { diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index 0bcbba2a29436..1e12ad8948dbd 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -502,7 +502,7 @@ static int gpu_cc_sm6350_probe(struct platform_device *pdev) value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; regmap_update_bits(regmap, 0x1098, mask, value); - return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6350_desc, regmap); } static struct platform_driver gpu_cc_sm6350_driver = { diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index 4e9a30a080d39..41f59024143ea 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -455,7 +455,7 @@ static int gpucc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); - ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &gpucc_sm6375_desc, regmap); pm_runtime_put(&pdev->dev); return ret; diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c index 135601629cba7..d711464a71b6d 100644 --- a/drivers/clk/qcom/gpucc-sm8150.c +++ b/drivers/clk/qcom/gpucc-sm8150.c @@ -304,7 +304,7 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev) clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8150_desc, regmap); } static struct platform_driver gpu_cc_sm8150_driver = { diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c index 012bd1380f555..113b486a6d2fb 100644 --- a/drivers/clk/qcom/gpucc-sm8250.c +++ b/drivers/clk/qcom/gpucc-sm8250.c @@ -320,7 +320,7 @@ static int gpu_cc_sm8250_probe(struct platform_device *pdev) value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; regmap_update_bits(regmap, 0x1098, mask, value); - return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8250_desc, regmap); } static struct platform_driver gpu_cc_sm8250_driver = { diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c index 9437d316d145c..f6bb8244dd404 100644 --- a/drivers/clk/qcom/gpucc-sm8350.c +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -604,7 +604,7 @@ static int gpu_cc_sm8350_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8350_desc, regmap); } static const struct of_device_id gpu_cc_sm8350_match_table[] = { diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c index 7b329a8032892..b3c5d6923cd20 100644 --- a/drivers/clk/qcom/gpucc-sm8450.c +++ b/drivers/clk/qcom/gpucc-sm8450.c @@ -751,7 +751,7 @@ static int gpu_cc_sm8450_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap); } static struct platform_driver gpu_cc_sm8450_driver = { diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 4fc69c6026e5e..7486edf561606 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -579,7 +579,7 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ - return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8550_desc, regmap); } static struct platform_driver gpu_cc_sm8550_driver = { diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c index c53306d3093f7..f15aeecc512d5 100644 --- a/drivers/clk/qcom/gpucc-sm8650.c +++ b/drivers/clk/qcom/gpucc-sm8650.c @@ -647,7 +647,7 @@ static int gpu_cc_sm8650_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - return qcom_cc_really_probe(pdev, &gpu_cc_sm8650_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8650_desc, regmap); } static struct platform_driver gpu_cc_sm8650_driver = { diff --git a/drivers/clk/qcom/gpucc-x1e80100.c b/drivers/clk/qcom/gpucc-x1e80100.c index b7e79d118d6ef..2eec20dd0254c 100644 --- a/drivers/clk/qcom/gpucc-x1e80100.c +++ b/drivers/clk/qcom/gpucc-x1e80100.c @@ -640,7 +640,7 @@ static int gpu_cc_x1e80100_probe(struct platform_device *pdev) /* Keep clocks always enabled */ qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ - return qcom_cc_really_probe(pdev, &gpu_cc_x1e80100_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gpu_cc_x1e80100_desc, regmap); } static struct platform_driver gpu_cc_x1e80100_driver = { diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c index fa8cda63cf204..bf5320a43e8c2 100644 --- a/drivers/clk/qcom/lcc-ipq806x.c +++ b/drivers/clk/qcom/lcc-ipq806x.c @@ -454,7 +454,7 @@ static int lcc_ipq806x_probe(struct platform_device *pdev) /* Enable PLL4 source on the LPASS Primary PLL Mux */ regmap_write(regmap, 0xc4, 0x1); - return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &lcc_ipq806x_desc, regmap); } static struct platform_driver lcc_ipq806x_driver = { diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c index e725e7b9c456d..d53bf315e9c33 100644 --- a/drivers/clk/qcom/lcc-msm8960.c +++ b/drivers/clk/qcom/lcc-msm8960.c @@ -481,7 +481,7 @@ static int lcc_msm8960_probe(struct platform_device *pdev) /* Enable PLL4 source on the LPASS Primary PLL Mux */ regmap_write(regmap, 0xc4, 0x1); - return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &lcc_msm8960_desc, regmap); } static struct platform_driver lcc_msm8960_driver = { diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c index c43d0b1af7f7e..45e7264770866 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -772,7 +772,7 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev) regmap_write(regmap, 0x4, 0x3b); regmap_write(regmap, 0x8, 0xff05); - ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &lpass_audio_cc_sc7280_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n"); goto exit; @@ -847,7 +847,7 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config); - ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &lpass_aon_cc_sc7280_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n"); goto exit; diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c index 8ac72d26087e2..726c6378752f8 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -411,7 +411,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev) clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap, &lpass_lpaaudio_dig_pll_config); - ret = qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7180_desc, regmap); pm_runtime_mark_last_busy(&pdev->dev); exit: diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c index a2f1e6ad6da40..b0888cd2460b3 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7280.c +++ b/drivers/clk/qcom/lpasscorecc-sc7280.c @@ -406,7 +406,7 @@ static int lpass_core_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config); - return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7280_desc, regmap); } static struct platform_driver lpass_core_cc_sc7280_driver = { diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 50638ab341eca..1061322534c41 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -3122,7 +3122,7 @@ static int mmcc_msm8960_probe(struct platform_device *pdev) clk_pll_configure_sr(&pll15, regmap, &pll15_config, false); - return qcom_cc_really_probe(pdev, desc, regmap); + return qcom_cc_really_probe(&pdev->dev, desc, regmap); } static struct platform_driver mmcc_msm8960_driver = { diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 36f460b78be2c..d5bcb09ebd0cc 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -2768,7 +2768,7 @@ static int mmcc_msm8974_probe(struct platform_device *pdev) msm8226_clock_override(); } - return qcom_cc_really_probe(pdev, desc, regmap); + return qcom_cc_really_probe(&pdev->dev, desc, regmap); } static struct platform_driver mmcc_msm8974_driver = { diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c index f19080cf715bc..78e5083eaf0f6 100644 --- a/drivers/clk/qcom/mmcc-msm8994.c +++ b/drivers/clk/qcom/mmcc-msm8994.c @@ -2602,7 +2602,7 @@ static int mmcc_msm8994_probe(struct platform_device *pdev) clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config); clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config); - return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8994_desc, regmap); } static struct platform_driver mmcc_msm8994_driver = { diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 92287d40c3a5f..1a32c6eb82178 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -3626,7 +3626,7 @@ static int mmcc_msm8996_probe(struct platform_device *pdev) /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ regmap_update_bits(regmap, 0x5054, BIT(15), 0); - return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8996_desc, regmap); } static struct platform_driver mmcc_msm8996_driver = { diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c index 275fb3b71ede4..5738445a8656f 100644 --- a/drivers/clk/qcom/mmcc-msm8998.c +++ b/drivers/clk/qcom/mmcc-msm8998.c @@ -2866,7 +2866,7 @@ static int mmcc_msm8998_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8998_desc, regmap); } static struct platform_driver mmcc_msm8998_driver = { diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c index 4b8380c2d6485..98ba5b4518fb3 100644 --- a/drivers/clk/qcom/mmcc-sdm660.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -2847,7 +2847,7 @@ static int mmcc_660_probe(struct platform_device *pdev) clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config); clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config); - return qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &mmcc_660_desc, regmap); } static struct platform_driver mmcc_660_driver = { diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c index 552a3eb1fd910..e5e8f2e82b949 100644 --- a/drivers/clk/qcom/tcsrcc-sm8550.c +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -166,7 +166,7 @@ static int tcsr_cc_sm8550_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &tcsr_cc_sm8550_desc, regmap); } static struct platform_driver tcsr_cc_sm8550_driver = { diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index ae0f812f83e8e..d7f8454803969 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -226,7 +226,7 @@ static int video_cc_sc7180_probe(struct platform_device *pdev) /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */ regmap_update_bits(regmap, 0x984, 0x1, 0x1); - return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &video_cc_sc7180_desc, regmap); } static struct platform_driver video_cc_sc7180_driver = { diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c index 119a3ed6eb6ad..317b325d6dafe 100644 --- a/drivers/clk/qcom/videocc-sc7280.c +++ b/drivers/clk/qcom/videocc-sc7280.c @@ -305,7 +305,7 @@ static int video_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); - return qcom_cc_really_probe(pdev, &video_cc_sc7280_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &video_cc_sc7280_desc, regmap); } static struct platform_driver video_cc_sc7280_driver = { diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c index 80095a283a86c..f77a077794777 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -329,7 +329,7 @@ static int video_cc_sdm845_probe(struct platform_device *pdev) clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); - return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &video_cc_sdm845_desc, regmap); } static struct platform_driver video_cc_sdm845_driver = { diff --git a/drivers/clk/qcom/videocc-sm7150.c b/drivers/clk/qcom/videocc-sm7150.c index 64f6b03996fc9..14ef7f5617537 100644 --- a/drivers/clk/qcom/videocc-sm7150.c +++ b/drivers/clk/qcom/videocc-sm7150.c @@ -341,7 +341,7 @@ static int videocc_sm7150_probe(struct platform_device *pdev) /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x984); /* VIDEOCC_XO_CLK */ - return qcom_cc_really_probe(pdev, &videocc_sm7150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &videocc_sm7150_desc, regmap); } static struct platform_driver videocc_sm7150_driver = { diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index 554631aa279b5..daab3237eec19 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -262,7 +262,7 @@ static int video_cc_sm8150_probe(struct platform_device *pdev) /* Keep VIDEO_CC_XO_CLK ALWAYS-ON */ regmap_update_bits(regmap, 0x984, 0x1, 0x1); - ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8150_desc, regmap); pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 914eddd0ae152..d7e0c32284c1a 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -387,7 +387,7 @@ static int video_cc_sm8250_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8250_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index f7aec28d4c872..5bd6fe3e12988 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -562,7 +562,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); return ret; diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index 67df40f164231..ed9163d642441 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -428,7 +428,7 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d24740..4d36362db1d04 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -433,7 +433,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ - ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); + ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap); pm_runtime_put(&pdev->dev); From 2441b965c4c7adae0b4a7825f7acb67d44c3cd38 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Wed, 5 Jun 2024 20:45:41 +0800 Subject: [PATCH 39/61] clk: qcom: add clock controller driver for qca8386/qca8084 The clock controller driver of qca8386/qca8084 is registered as the MDIO device, the hardware register is accessed by MDIO bus that is normally used to access general PHY device, which is different from the current existed qcom clock controller drivers using ioremap to access hardware clock registers, nsscc-qca8k is accessed via an MDIO bus. MDIO bus is commonly utilized by both qca8386/qca8084 and other PHY devices, so the mutex lock mdio_bus->mdio_lock should be used instead of using the mutex lock of remap. To access the hardware clock registers of qca8386/qca8084, there is a special MDIO frame sequence, which needs to be sent to the device. Enable the reference clock before resetting the clock controller, the reference clock rate is fixed to 50MHZ. Reviewed-by: Bryan O'Donoghue Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20240605124541.2711467-5-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-qca8k.c | 2221 ++++++++++++++++++++++++++++++++ 3 files changed, 2231 insertions(+) create mode 100644 drivers/clk/qcom/nsscc-qca8k.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 20ba2eeb24ec0..4432b1cce478c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -249,6 +249,15 @@ config IPQ_GCC_9574 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9574. +config IPQ_NSSCC_QCA8K + tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" + depends on MDIO_BUS || COMPILE_TEST + help + Support for NSS(Network SubSystem) clock controller on + qca8386/qca8084 chip. + Say Y or M if you want to use network features of switch or + PHY device. Select this for the root clock of qca8k. + config MSM_GCC_8660 tristate "MSM8660 Global Clock Controller" depends on ARM || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b7de8600dc3d8..0241f00689bc0 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o +obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o diff --git a/drivers/clk/qcom/nsscc-qca8k.c b/drivers/clk/qcom/nsscc-qca8k.c new file mode 100644 index 0000000000000..5c8324e2bccae --- /dev/null +++ b/drivers/clk/qcom/nsscc-qca8k.c @@ -0,0 +1,2221 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +#define QCA8K_CLK_REG_BASE 0x800000 +#define QCA8K_HIGH_ADDR_PREFIX 0x18 +#define QCA8K_LOW_ADDR_PREFIX 0x10 +#define QCA8K_CFG_PAGE_REG 0xc +#define QCA8K_CLK_REG_MASK GENMASK(4, 0) +#define QCA8K_CLK_PHY_ADDR_MASK GENMASK(7, 5) +#define QCA8K_CLK_PAGE_MASK GENMASK(23, 8) +#define QCA8K_REG_DATA_UPPER_16_BITS BIT(1) + +enum { + DT_XO, + DT_UNIPHY0_RX_CLK, + DT_UNIPHY0_TX_CLK, + DT_UNIPHY1_RX_CLK, + DT_UNIPHY1_TX_CLK, + DT_UNIPHY1_RX312P5M_CLK, + DT_UNIPHY1_TX312P5M_CLK, +}; + +enum { + P_XO, + P_UNIPHY0_RX, + P_UNIPHY0_TX, + P_UNIPHY1_RX, + P_UNIPHY1_TX, + P_UNIPHY1_RX312P5M, + P_UNIPHY1_TX312P5M, + P_MAC4_RX_DIV, + P_MAC4_TX_DIV, + P_MAC5_RX_DIV, + P_MAC5_TX_DIV, +}; + +static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY1_TX312P5M_CLK }, +}; + +static const struct parent_map nss_cc_uniphy1_tx312p5m_map[] = { + { P_XO, 0 }, + { P_UNIPHY1_TX312P5M, 1 }, +}; + +static struct clk_rcg2 nss_cc_switch_core_clk_src = { + .cmd_rcgr = 0x0, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_tx312p5m_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_switch_core_clk_src", + .parent_data = nss_cc_uniphy1_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data), + .ops = &clk_rcg2_mux_closest_ops, + }, +}; + +static struct clk_branch nss_cc_switch_core_clk = { + .halt_reg = 0x8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_switch_core_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_switch_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_apb_bridge_clk = { + .halt_reg = 0x10, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_apb_bridge_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_switch_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy1_tx_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY1_TX_CLK }, +}; + +static const struct parent_map nss_cc_uniphy1_tx_map[] = { + { P_XO, 0 }, + { P_UNIPHY1_TX, 2 }, +}; + +static struct clk_rcg2 nss_cc_mac0_tx_clk_src = { + .cmd_rcgr = 0x14, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_tx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_tx_clk_src", + .parent_data = nss_cc_uniphy1_tx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx_data), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_mux_closest_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac0_tx_div_clk_src = { + .reg = 0x1c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac0_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac0_tx_clk = { + .halt_reg = 0x20, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac0_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac0_tx_srds1_clk = { + .halt_reg = 0x24, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x24, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_tx_srds1_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac0_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy1_rx_tx_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY1_RX_CLK }, + { .index = DT_UNIPHY1_TX_CLK }, +}; + +static const struct parent_map nss_cc_uniphy1_rx_tx_map[] = { + { P_XO, 0 }, + { P_UNIPHY1_RX, 1 }, + { P_UNIPHY1_TX, 2 }, +}; + +static struct clk_rcg2 nss_cc_mac0_rx_clk_src = { + .cmd_rcgr = 0x28, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_rx_tx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_rx_clk_src", + .parent_data = nss_cc_uniphy1_rx_tx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx_data), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_mux_closest_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac0_rx_div_clk_src = { + .reg = 0x30, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac0_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac0_rx_clk = { + .halt_reg = 0x34, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x34, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac0_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac0_rx_srds1_clk = { + .halt_reg = 0x3c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac0_rx_srds1_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac0_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy1_rx_tx312p5m_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY1_TX312P5M_CLK }, + { .index = DT_UNIPHY1_RX312P5M_CLK }, +}; + +static const struct parent_map nss_cc_uniphy1_rx_tx312p5m_map[] = { + { P_XO, 0 }, + { P_UNIPHY1_TX312P5M, 6 }, + { P_UNIPHY1_RX312P5M, 7 }, +}; + +static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_25[] = { + C(P_UNIPHY1_TX312P5M, 12.5, 0, 0), + C(P_UNIPHY1_RX312P5M, 12.5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_125[] = { + C(P_UNIPHY1_TX312P5M, 2.5, 0, 0), + C(P_UNIPHY1_RX312P5M, 2.5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_312p5[] = { + C(P_UNIPHY1_TX312P5M, 1, 0, 0), + C(P_UNIPHY1_RX312P5M, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_mac1_tx_clk_src[] = { + FM(25000000, ftbl_nss_cc_mac1_tx_clk_src_25), + FMS(50000000, P_XO, 1, 0, 0), + FM(125000000, ftbl_nss_cc_mac1_tx_clk_src_125), + FM(312500000, ftbl_nss_cc_mac1_tx_clk_src_312p5), + { } +}; + +static struct clk_rcg2 nss_cc_mac1_tx_clk_src = { + .cmd_rcgr = 0x40, + .freq_multi_tbl = ftbl_nss_cc_mac1_tx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_rx_tx312p5m_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_tx_clk_src", + .parent_data = nss_cc_uniphy1_rx_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac1_tx_div_clk_src = { + .reg = 0x48, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src = { + .reg = 0x4c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_srds1_ch0_rx_clk = { + .halt_reg = 0x50, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_srds1_ch0_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_tx_clk = { + .halt_reg = 0x54, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x54, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_gephy0_tx_clk = { + .halt_reg = 0x58, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_gephy0_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_rx_clk = { + .halt_reg = 0x5c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_srds1_ch0_xgmii_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_prx_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY1_TX312P5M_CLK }, +}; + +static const struct parent_map nss_cc_uniphy1_tx312p5m_prx_map[] = { + { P_XO, 0 }, + { P_UNIPHY1_TX312P5M, 6 }, +}; + +static const struct freq_tbl ftbl_nss_cc_mac1_rx_clk_src[] = { + F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0), + F(50000000, P_XO, 1, 0, 0), + F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0), + F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_mac1_rx_clk_src = { + .cmd_rcgr = 0x60, + .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_tx312p5m_prx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_rx_clk_src", + .parent_data = nss_cc_uniphy1_tx312p5m_prx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac1_rx_div_clk_src = { + .reg = 0x68, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src = { + .reg = 0x6c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_srds1_ch0_tx_clk = { + .halt_reg = 0x70, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x70, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_srds1_ch0_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_rx_clk = { + .halt_reg = 0x74, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x74, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_gephy0_rx_clk = { + .halt_reg = 0x78, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x78, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_gephy0_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_tx_clk = { + .halt_reg = 0x7c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac1_srds1_ch0_xgmii_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_rcg2 nss_cc_mac2_tx_clk_src = { + .cmd_rcgr = 0x80, + .freq_multi_tbl = ftbl_nss_cc_mac1_tx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_rx_tx312p5m_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_tx_clk_src", + .parent_data = nss_cc_uniphy1_rx_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac2_tx_div_clk_src = { + .reg = 0x88, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src = { + .reg = 0x8c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_srds1_ch1_rx_clk = { + .halt_reg = 0x90, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x90, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_srds1_ch1_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_tx_clk = { + .halt_reg = 0x94, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x94, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_gephy1_tx_clk = { + .halt_reg = 0x98, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x98, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_gephy1_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_rx_clk = { + .halt_reg = 0x9c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_srds1_ch1_xgmii_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_rcg2 nss_cc_mac2_rx_clk_src = { + .cmd_rcgr = 0xa0, + .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_tx312p5m_prx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_rx_clk_src", + .parent_data = nss_cc_uniphy1_tx312p5m_prx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac2_rx_div_clk_src = { + .reg = 0xa8, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src = { + .reg = 0xac, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_srds1_ch1_tx_clk = { + .halt_reg = 0xb0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_srds1_ch1_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_rx_clk = { + .halt_reg = 0xb4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_gephy1_rx_clk = { + .halt_reg = 0xb8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_gephy1_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_tx_clk = { + .halt_reg = 0xbc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xbc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac2_srds1_ch1_xgmii_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_rcg2 nss_cc_mac3_tx_clk_src = { + .cmd_rcgr = 0xc0, + .freq_multi_tbl = ftbl_nss_cc_mac1_tx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_rx_tx312p5m_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_tx_clk_src", + .parent_data = nss_cc_uniphy1_rx_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac3_tx_div_clk_src = { + .reg = 0xc8, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src = { + .reg = 0xcc, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_srds1_ch2_rx_clk = { + .halt_reg = 0xd0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_srds1_ch2_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_tx_clk = { + .halt_reg = 0xd4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_gephy2_tx_clk = { + .halt_reg = 0xd8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_gephy2_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_rx_clk = { + .halt_reg = 0xdc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xdc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_srds1_ch2_xgmii_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_rcg2 nss_cc_mac3_rx_clk_src = { + .cmd_rcgr = 0xe0, + .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_tx312p5m_prx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_rx_clk_src", + .parent_data = nss_cc_uniphy1_tx312p5m_prx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac3_rx_div_clk_src = { + .reg = 0xe8, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src = { + .reg = 0xec, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_srds1_ch2_tx_clk = { + .halt_reg = 0xf0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_srds1_ch2_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_rx_clk = { + .halt_reg = 0xf4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_gephy2_rx_clk = { + .halt_reg = 0xf8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_gephy2_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_tx_clk = { + .halt_reg = 0xfc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xfc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac3_srds1_ch2_xgmii_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY0_RX_CLK }, + { .index = DT_UNIPHY1_TX312P5M_CLK }, + { .index = DT_UNIPHY1_RX312P5M_CLK }, +}; + +static const struct parent_map nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map[] = { + { P_XO, 0 }, + { P_UNIPHY0_RX, 1 }, + { P_UNIPHY1_TX312P5M, 3 }, + { P_UNIPHY1_RX312P5M, 7 }, +}; + +static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_25[] = { + C(P_UNIPHY0_RX, 12.5, 0, 0), + C(P_UNIPHY0_RX, 5, 0, 0), + C(P_UNIPHY1_TX312P5M, 12.5, 0, 0), + C(P_UNIPHY1_RX312P5M, 12.5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_125[] = { + C(P_UNIPHY0_RX, 1, 0, 0), + C(P_UNIPHY0_RX, 2.5, 0, 0), + C(P_UNIPHY1_TX312P5M, 2.5, 0, 0), + C(P_UNIPHY1_RX312P5M, 2.5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_312p5[] = { + C(P_UNIPHY0_RX, 1, 0, 0), + C(P_UNIPHY1_TX312P5M, 1, 0, 0), + C(P_UNIPHY1_RX312P5M, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_mac4_tx_clk_src[] = { + FM(25000000, ftbl_nss_cc_mac4_tx_clk_src_25), + FMS(50000000, P_XO, 1, 0, 0), + FM(125000000, ftbl_nss_cc_mac4_tx_clk_src_125), + FM(312500000, ftbl_nss_cc_mac4_tx_clk_src_312p5), + { } +}; + +static struct clk_rcg2 nss_cc_mac4_tx_clk_src = { + .cmd_rcgr = 0x100, + .freq_multi_tbl = ftbl_nss_cc_mac4_tx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_tx_clk_src", + .parent_data = nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac4_tx_div_clk_src = { + .reg = 0x108, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src = { + .reg = 0x10c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_srds1_ch3_rx_clk = { + .halt_reg = 0x110, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x110, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_srds1_ch3_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_tx_clk = { + .halt_reg = 0x114, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x114, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_gephy3_tx_clk = { + .halt_reg = 0x118, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x118, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_gephy3_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_rx_clk = { + .halt_reg = 0x11c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_srds1_ch3_xgmii_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy0_tx_uniphy1_tx312p5m_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY0_TX_CLK }, + { .index = DT_UNIPHY1_TX312P5M_CLK }, +}; + +static const struct parent_map nss_cc_uniphy0_tx_uniphy1_tx312p5m_map[] = { + { P_XO, 0 }, + { P_UNIPHY0_TX, 2 }, + { P_UNIPHY1_TX312P5M, 3 }, +}; + +static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_25[] = { + C(P_UNIPHY0_TX, 12.5, 0, 0), + C(P_UNIPHY0_TX, 5, 0, 0), + C(P_UNIPHY1_TX312P5M, 12.5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_125[] = { + C(P_UNIPHY0_TX, 1, 0, 0), + C(P_UNIPHY0_TX, 2.5, 0, 0), + C(P_UNIPHY1_TX312P5M, 2.5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_312p5[] = { + C(P_UNIPHY0_TX, 1, 0, 0), + C(P_UNIPHY1_TX312P5M, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_mac4_rx_clk_src[] = { + FM(25000000, ftbl_nss_cc_mac4_rx_clk_src_25), + FMS(50000000, P_XO, 1, 0, 0), + FM(125000000, ftbl_nss_cc_mac4_rx_clk_src_125), + FM(312500000, ftbl_nss_cc_mac4_rx_clk_src_312p5), + { } +}; + +static struct clk_rcg2 nss_cc_mac4_rx_clk_src = { + .cmd_rcgr = 0x120, + .freq_multi_tbl = ftbl_nss_cc_mac4_rx_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy0_tx_uniphy1_tx312p5m_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_rx_clk_src", + .parent_data = nss_cc_uniphy0_tx_uniphy1_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy0_tx_uniphy1_tx312p5m_data), + .ops = &clk_rcg2_fm_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac4_rx_div_clk_src = { + .reg = 0x128, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src = { + .reg = 0x12c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_srds1_ch3_tx_clk = { + .halt_reg = 0x130, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_srds1_ch3_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_rx_clk = { + .halt_reg = 0x134, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_gephy3_rx_clk = { + .halt_reg = 0x138, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x138, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_gephy3_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_tx_clk = { + .halt_reg = 0x13c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac4_srds1_ch3_xgmii_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy0_tx_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY0_TX_CLK }, +}; + +static const struct parent_map nss_cc_uniphy0_tx_map[] = { + { P_XO, 0 }, + { P_UNIPHY0_TX, 2 }, +}; + +static struct clk_rcg2 nss_cc_mac5_tx_clk_src = { + .cmd_rcgr = 0x140, + .hid_width = 5, + .parent_map = nss_cc_uniphy0_tx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_tx_clk_src", + .parent_data = nss_cc_uniphy0_tx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy0_tx_data), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_mux_closest_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac5_tx_div_clk_src = { + .reg = 0x148, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac5_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac5_tx_clk = { + .halt_reg = 0x14c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_tx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac5_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_uniphy0_rx_tx_data[] = { + { .index = DT_XO }, + { .index = DT_UNIPHY0_RX_CLK }, + { .index = DT_UNIPHY0_TX_CLK }, +}; + +static const struct parent_map nss_cc_uniphy0_rx_tx_map[] = { + { P_XO, 0 }, + { P_UNIPHY0_RX, 1 }, + { P_UNIPHY0_TX, 2 }, +}; + +static struct clk_rcg2 nss_cc_mac5_rx_clk_src = { + .cmd_rcgr = 0x154, + .hid_width = 5, + .parent_map = nss_cc_uniphy0_rx_tx_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_rx_clk_src", + .parent_data = nss_cc_uniphy0_rx_tx_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy0_rx_tx_data), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_mux_closest_ops, + }, +}; + +static struct clk_regmap_div nss_cc_mac5_rx_div_clk_src = { + .reg = 0x15c, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac5_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac5_rx_clk = { + .halt_reg = 0x160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_rx_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac5_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct parent_map nss_cc_mac4_rx_div_mac5_tx_div_map[] = { + { P_MAC4_RX_DIV, 0 }, + { P_MAC5_TX_DIV, 1 }, +}; + +static struct clk_regmap_mux nss_cc_mac5_tx_srds0_clk_src = { + .reg = 0x300, + .shift = 0, + .width = 1, + .parent_map = nss_cc_mac4_rx_div_mac5_tx_div_map, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_tx_srds0_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_rx_div_clk_src.clkr.hw, + &nss_cc_mac5_tx_div_clk_src.clkr.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac5_tx_srds0_clk = { + .halt_reg = 0x150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_tx_srds0_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac5_tx_srds0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct parent_map nss_cc_mac4_tx_div_mac5_rx_div_map[] = { + { P_MAC4_TX_DIV, 0 }, + { P_MAC5_RX_DIV, 1 }, +}; + +static struct clk_regmap_mux nss_cc_mac5_rx_srds0_clk_src = { + .reg = 0x300, + .shift = 1, + .width = 1, + .parent_map = nss_cc_mac4_tx_div_mac5_rx_div_map, + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_rx_srds0_clk_src", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac4_tx_div_clk_src.clkr.hw, + &nss_cc_mac5_rx_div_clk_src.clkr.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mac5_rx_srds0_clk = { + .halt_reg = 0x164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mac5_rx_srds0_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_mac5_rx_srds0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct parent_map nss_cc_uniphy1_tx312p5m_map2[] = { + { P_XO, 0 }, + { P_UNIPHY1_TX312P5M, 2 }, +}; + +static const struct freq_tbl ftbl_nss_cc_ahb_clk_src[] = { + F(50000000, P_XO, 1, 0, 0), + F(104170000, P_UNIPHY1_TX312P5M, 3, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_ahb_clk_src = { + .cmd_rcgr = 0x168, + .freq_tbl = ftbl_nss_cc_ahb_clk_src, + .hid_width = 5, + .parent_map = nss_cc_uniphy1_tx312p5m_map2, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ahb_clk_src", + .parent_data = nss_cc_uniphy1_tx312p5m_data, + .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch nss_cc_ahb_clk = { + .halt_reg = 0x170, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x170, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_sec_ctrl_ahb_clk = { + .halt_reg = 0x174, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x174, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_sec_ctrl_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_tlmm_clk = { + .halt_reg = 0x178, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x178, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_tlmm_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_tlmm_ahb_clk = { + .halt_reg = 0x190, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x190, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_tlmm_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_cnoc_ahb_clk = { + .halt_reg = 0x194, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x194, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_cnoc_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mdio_ahb_clk = { + .halt_reg = 0x198, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x198, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mdio_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_mdio_master_ahb_clk = { + .halt_reg = 0x19c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_mdio_master_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static const struct clk_parent_data nss_cc_xo_data[] = { + { .index = DT_XO }, +}; + +static const struct parent_map nss_cc_xo_map[] = { + { P_XO, 0 }, +}; + +static const struct freq_tbl ftbl_nss_cc_sys_clk_src[] = { + F(25000000, P_XO, 2, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_sys_clk_src = { + .cmd_rcgr = 0x1a0, + .freq_tbl = ftbl_nss_cc_sys_clk_src, + .hid_width = 5, + .parent_map = nss_cc_xo_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_sys_clk_src", + .parent_data = nss_cc_xo_data, + .num_parents = ARRAY_SIZE(nss_cc_xo_data), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch nss_cc_srds0_sys_clk = { + .halt_reg = 0x1a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_srds0_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_sys_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_srds1_sys_clk = { + .halt_reg = 0x1ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_srds1_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_sys_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_gephy0_sys_clk = { + .halt_reg = 0x1b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_gephy0_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_sys_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_gephy1_sys_clk = { + .halt_reg = 0x1b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_gephy1_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_sys_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_gephy2_sys_clk = { + .halt_reg = 0x1b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_gephy2_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_sys_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_branch nss_cc_gephy3_sys_clk = { + .halt_reg = 0x1bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "nss_cc_gephy3_sys_clk", + .parent_hws = (const struct clk_hw *[]) { + &nss_cc_sys_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_prepare_ops, + }, + }, +}; + +static struct clk_regmap *nss_cc_qca8k_clocks[] = { + [NSS_CC_SWITCH_CORE_CLK_SRC] = &nss_cc_switch_core_clk_src.clkr, + [NSS_CC_SWITCH_CORE_CLK] = &nss_cc_switch_core_clk.clkr, + [NSS_CC_APB_BRIDGE_CLK] = &nss_cc_apb_bridge_clk.clkr, + [NSS_CC_MAC0_TX_CLK_SRC] = &nss_cc_mac0_tx_clk_src.clkr, + [NSS_CC_MAC0_TX_DIV_CLK_SRC] = &nss_cc_mac0_tx_div_clk_src.clkr, + [NSS_CC_MAC0_TX_CLK] = &nss_cc_mac0_tx_clk.clkr, + [NSS_CC_MAC0_TX_SRDS1_CLK] = &nss_cc_mac0_tx_srds1_clk.clkr, + [NSS_CC_MAC0_RX_CLK_SRC] = &nss_cc_mac0_rx_clk_src.clkr, + [NSS_CC_MAC0_RX_DIV_CLK_SRC] = &nss_cc_mac0_rx_div_clk_src.clkr, + [NSS_CC_MAC0_RX_CLK] = &nss_cc_mac0_rx_clk.clkr, + [NSS_CC_MAC0_RX_SRDS1_CLK] = &nss_cc_mac0_rx_srds1_clk.clkr, + [NSS_CC_MAC1_TX_CLK_SRC] = &nss_cc_mac1_tx_clk_src.clkr, + [NSS_CC_MAC1_TX_DIV_CLK_SRC] = &nss_cc_mac1_tx_div_clk_src.clkr, + [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC] = + &nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src.clkr, + [NSS_CC_MAC1_SRDS1_CH0_RX_CLK] = &nss_cc_mac1_srds1_ch0_rx_clk.clkr, + [NSS_CC_MAC1_TX_CLK] = &nss_cc_mac1_tx_clk.clkr, + [NSS_CC_MAC1_GEPHY0_TX_CLK] = &nss_cc_mac1_gephy0_tx_clk.clkr, + [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK] = &nss_cc_mac1_srds1_ch0_xgmii_rx_clk.clkr, + [NSS_CC_MAC1_RX_CLK_SRC] = &nss_cc_mac1_rx_clk_src.clkr, + [NSS_CC_MAC1_RX_DIV_CLK_SRC] = &nss_cc_mac1_rx_div_clk_src.clkr, + [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC] = + &nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src.clkr, + [NSS_CC_MAC1_SRDS1_CH0_TX_CLK] = &nss_cc_mac1_srds1_ch0_tx_clk.clkr, + [NSS_CC_MAC1_RX_CLK] = &nss_cc_mac1_rx_clk.clkr, + [NSS_CC_MAC1_GEPHY0_RX_CLK] = &nss_cc_mac1_gephy0_rx_clk.clkr, + [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK] = &nss_cc_mac1_srds1_ch0_xgmii_tx_clk.clkr, + [NSS_CC_MAC2_TX_CLK_SRC] = &nss_cc_mac2_tx_clk_src.clkr, + [NSS_CC_MAC2_TX_DIV_CLK_SRC] = &nss_cc_mac2_tx_div_clk_src.clkr, + [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC] = + &nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src.clkr, + [NSS_CC_MAC2_SRDS1_CH1_RX_CLK] = &nss_cc_mac2_srds1_ch1_rx_clk.clkr, + [NSS_CC_MAC2_TX_CLK] = &nss_cc_mac2_tx_clk.clkr, + [NSS_CC_MAC2_GEPHY1_TX_CLK] = &nss_cc_mac2_gephy1_tx_clk.clkr, + [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK] = &nss_cc_mac2_srds1_ch1_xgmii_rx_clk.clkr, + [NSS_CC_MAC2_RX_CLK_SRC] = &nss_cc_mac2_rx_clk_src.clkr, + [NSS_CC_MAC2_RX_DIV_CLK_SRC] = &nss_cc_mac2_rx_div_clk_src.clkr, + [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC] = + &nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src.clkr, + [NSS_CC_MAC2_SRDS1_CH1_TX_CLK] = &nss_cc_mac2_srds1_ch1_tx_clk.clkr, + [NSS_CC_MAC2_RX_CLK] = &nss_cc_mac2_rx_clk.clkr, + [NSS_CC_MAC2_GEPHY1_RX_CLK] = &nss_cc_mac2_gephy1_rx_clk.clkr, + [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK] = &nss_cc_mac2_srds1_ch1_xgmii_tx_clk.clkr, + [NSS_CC_MAC3_TX_CLK_SRC] = &nss_cc_mac3_tx_clk_src.clkr, + [NSS_CC_MAC3_TX_DIV_CLK_SRC] = &nss_cc_mac3_tx_div_clk_src.clkr, + [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC] = + &nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src.clkr, + [NSS_CC_MAC3_SRDS1_CH2_RX_CLK] = &nss_cc_mac3_srds1_ch2_rx_clk.clkr, + [NSS_CC_MAC3_TX_CLK] = &nss_cc_mac3_tx_clk.clkr, + [NSS_CC_MAC3_GEPHY2_TX_CLK] = &nss_cc_mac3_gephy2_tx_clk.clkr, + [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK] = &nss_cc_mac3_srds1_ch2_xgmii_rx_clk.clkr, + [NSS_CC_MAC3_RX_CLK_SRC] = &nss_cc_mac3_rx_clk_src.clkr, + [NSS_CC_MAC3_RX_DIV_CLK_SRC] = &nss_cc_mac3_rx_div_clk_src.clkr, + [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC] = + &nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src.clkr, + [NSS_CC_MAC3_SRDS1_CH2_TX_CLK] = &nss_cc_mac3_srds1_ch2_tx_clk.clkr, + [NSS_CC_MAC3_RX_CLK] = &nss_cc_mac3_rx_clk.clkr, + [NSS_CC_MAC3_GEPHY2_RX_CLK] = &nss_cc_mac3_gephy2_rx_clk.clkr, + [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK] = &nss_cc_mac3_srds1_ch2_xgmii_tx_clk.clkr, + [NSS_CC_MAC4_TX_CLK_SRC] = &nss_cc_mac4_tx_clk_src.clkr, + [NSS_CC_MAC4_TX_DIV_CLK_SRC] = &nss_cc_mac4_tx_div_clk_src.clkr, + [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC] = + &nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src.clkr, + [NSS_CC_MAC4_SRDS1_CH3_RX_CLK] = &nss_cc_mac4_srds1_ch3_rx_clk.clkr, + [NSS_CC_MAC4_TX_CLK] = &nss_cc_mac4_tx_clk.clkr, + [NSS_CC_MAC4_GEPHY3_TX_CLK] = &nss_cc_mac4_gephy3_tx_clk.clkr, + [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK] = &nss_cc_mac4_srds1_ch3_xgmii_rx_clk.clkr, + [NSS_CC_MAC4_RX_CLK_SRC] = &nss_cc_mac4_rx_clk_src.clkr, + [NSS_CC_MAC4_RX_DIV_CLK_SRC] = &nss_cc_mac4_rx_div_clk_src.clkr, + [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC] = + &nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src.clkr, + [NSS_CC_MAC4_SRDS1_CH3_TX_CLK] = &nss_cc_mac4_srds1_ch3_tx_clk.clkr, + [NSS_CC_MAC4_RX_CLK] = &nss_cc_mac4_rx_clk.clkr, + [NSS_CC_MAC4_GEPHY3_RX_CLK] = &nss_cc_mac4_gephy3_rx_clk.clkr, + [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK] = &nss_cc_mac4_srds1_ch3_xgmii_tx_clk.clkr, + [NSS_CC_MAC5_TX_CLK_SRC] = &nss_cc_mac5_tx_clk_src.clkr, + [NSS_CC_MAC5_TX_DIV_CLK_SRC] = &nss_cc_mac5_tx_div_clk_src.clkr, + [NSS_CC_MAC5_TX_SRDS0_CLK] = &nss_cc_mac5_tx_srds0_clk.clkr, + [NSS_CC_MAC5_TX_CLK] = &nss_cc_mac5_tx_clk.clkr, + [NSS_CC_MAC5_RX_CLK_SRC] = &nss_cc_mac5_rx_clk_src.clkr, + [NSS_CC_MAC5_RX_DIV_CLK_SRC] = &nss_cc_mac5_rx_div_clk_src.clkr, + [NSS_CC_MAC5_RX_SRDS0_CLK] = &nss_cc_mac5_rx_srds0_clk.clkr, + [NSS_CC_MAC5_RX_CLK] = &nss_cc_mac5_rx_clk.clkr, + [NSS_CC_MAC5_TX_SRDS0_CLK_SRC] = &nss_cc_mac5_tx_srds0_clk_src.clkr, + [NSS_CC_MAC5_RX_SRDS0_CLK_SRC] = &nss_cc_mac5_rx_srds0_clk_src.clkr, + [NSS_CC_AHB_CLK_SRC] = &nss_cc_ahb_clk_src.clkr, + [NSS_CC_AHB_CLK] = &nss_cc_ahb_clk.clkr, + [NSS_CC_SEC_CTRL_AHB_CLK] = &nss_cc_sec_ctrl_ahb_clk.clkr, + [NSS_CC_TLMM_CLK] = &nss_cc_tlmm_clk.clkr, + [NSS_CC_TLMM_AHB_CLK] = &nss_cc_tlmm_ahb_clk.clkr, + [NSS_CC_CNOC_AHB_CLK] = &nss_cc_cnoc_ahb_clk.clkr, + [NSS_CC_MDIO_AHB_CLK] = &nss_cc_mdio_ahb_clk.clkr, + [NSS_CC_MDIO_MASTER_AHB_CLK] = &nss_cc_mdio_master_ahb_clk.clkr, + [NSS_CC_SYS_CLK_SRC] = &nss_cc_sys_clk_src.clkr, + [NSS_CC_SRDS0_SYS_CLK] = &nss_cc_srds0_sys_clk.clkr, + [NSS_CC_SRDS1_SYS_CLK] = &nss_cc_srds1_sys_clk.clkr, + [NSS_CC_GEPHY0_SYS_CLK] = &nss_cc_gephy0_sys_clk.clkr, + [NSS_CC_GEPHY1_SYS_CLK] = &nss_cc_gephy1_sys_clk.clkr, + [NSS_CC_GEPHY2_SYS_CLK] = &nss_cc_gephy2_sys_clk.clkr, + [NSS_CC_GEPHY3_SYS_CLK] = &nss_cc_gephy3_sys_clk.clkr, +}; + +static const struct qcom_reset_map nss_cc_qca8k_resets[] = { + [NSS_CC_SWITCH_CORE_ARES] = { 0xc, 2 }, + [NSS_CC_APB_BRIDGE_ARES] = { 0x10, 2 }, + [NSS_CC_MAC0_TX_ARES] = { 0x20, 2 }, + [NSS_CC_MAC0_TX_SRDS1_ARES] = { 0x24, 2 }, + [NSS_CC_MAC0_RX_ARES] = { 0x34, 2 }, + [NSS_CC_MAC0_RX_SRDS1_ARES] = { 0x3c, 2 }, + [NSS_CC_MAC1_SRDS1_CH0_RX_ARES] = { 0x50, 2 }, + [NSS_CC_MAC1_TX_ARES] = { 0x54, 2 }, + [NSS_CC_MAC1_GEPHY0_TX_ARES] = { 0x58, 2 }, + [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES] = { 0x5c, 2 }, + [NSS_CC_MAC1_SRDS1_CH0_TX_ARES] = { 0x70, 2 }, + [NSS_CC_MAC1_RX_ARES] = { 0x74, 2 }, + [NSS_CC_MAC1_GEPHY0_RX_ARES] = { 0x78, 2 }, + [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES] = { 0x7c, 2 }, + [NSS_CC_MAC2_SRDS1_CH1_RX_ARES] = { 0x90, 2 }, + [NSS_CC_MAC2_TX_ARES] = { 0x94, 2 }, + [NSS_CC_MAC2_GEPHY1_TX_ARES] = { 0x98, 2 }, + [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES] = { 0x9c, 2 }, + [NSS_CC_MAC2_SRDS1_CH1_TX_ARES] = { 0xb0, 2 }, + [NSS_CC_MAC2_RX_ARES] = { 0xb4, 2 }, + [NSS_CC_MAC2_GEPHY1_RX_ARES] = { 0xb8, 2 }, + [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES] = { 0xbc, 2 }, + [NSS_CC_MAC3_SRDS1_CH2_RX_ARES] = { 0xd0, 2 }, + [NSS_CC_MAC3_TX_ARES] = { 0xd4, 2 }, + [NSS_CC_MAC3_GEPHY2_TX_ARES] = { 0xd8, 2 }, + [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES] = { 0xdc, 2 }, + [NSS_CC_MAC3_SRDS1_CH2_TX_ARES] = { 0xf0, 2 }, + [NSS_CC_MAC3_RX_ARES] = { 0xf4, 2 }, + [NSS_CC_MAC3_GEPHY2_RX_ARES] = { 0xf8, 2 }, + [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES] = { 0xfc, 2 }, + [NSS_CC_MAC4_SRDS1_CH3_RX_ARES] = { 0x110, 2 }, + [NSS_CC_MAC4_TX_ARES] = { 0x114, 2 }, + [NSS_CC_MAC4_GEPHY3_TX_ARES] = { 0x118, 2 }, + [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES] = { 0x11c, 2 }, + [NSS_CC_MAC4_SRDS1_CH3_TX_ARES] = { 0x130, 2 }, + [NSS_CC_MAC4_RX_ARES] = { 0x134, 2 }, + [NSS_CC_MAC4_GEPHY3_RX_ARES] = { 0x138, 2 }, + [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES] = { 0x13c, 2 }, + [NSS_CC_MAC5_TX_ARES] = { 0x14c, 2 }, + [NSS_CC_MAC5_TX_SRDS0_ARES] = { 0x150, 2 }, + [NSS_CC_MAC5_RX_ARES] = { 0x160, 2 }, + [NSS_CC_MAC5_RX_SRDS0_ARES] = { 0x164, 2 }, + [NSS_CC_AHB_ARES] = { 0x170, 2 }, + [NSS_CC_SEC_CTRL_AHB_ARES] = { 0x174, 2 }, + [NSS_CC_TLMM_ARES] = { 0x178, 2 }, + [NSS_CC_TLMM_AHB_ARES] = { 0x190, 2 }, + [NSS_CC_CNOC_AHB_ARES] = { 0x194, 2 }, /* reset CNOC AHB & APB */ + [NSS_CC_MDIO_AHB_ARES] = { 0x198, 2 }, + [NSS_CC_MDIO_MASTER_AHB_ARES] = { 0x19c, 2 }, + [NSS_CC_SRDS0_SYS_ARES] = { 0x1a8, 2 }, + [NSS_CC_SRDS1_SYS_ARES] = { 0x1ac, 2 }, + [NSS_CC_GEPHY0_SYS_ARES] = { 0x1b0, 2 }, + [NSS_CC_GEPHY1_SYS_ARES] = { 0x1b4, 2 }, + [NSS_CC_GEPHY2_SYS_ARES] = { 0x1b8, 2 }, + [NSS_CC_GEPHY3_SYS_ARES] = { 0x1bc, 2 }, + [NSS_CC_SEC_CTRL_ARES] = { 0x1c8, 2 }, + [NSS_CC_SEC_CTRL_SENSE_ARES] = { 0x1d0, 2 }, + [NSS_CC_SLEEP_ARES] = { 0x1e0, 2 }, + [NSS_CC_DEBUG_ARES] = { 0x1e8, 2 }, + [NSS_CC_GEPHY0_ARES] = { 0x304, 0 }, + [NSS_CC_GEPHY1_ARES] = { 0x304, 1 }, + [NSS_CC_GEPHY2_ARES] = { 0x304, 2 }, + [NSS_CC_GEPHY3_ARES] = { 0x304, 3 }, + [NSS_CC_DSP_ARES] = { 0x304, 4 }, + [NSS_CC_GEPHY_FULL_ARES] = { .reg = 0x304, .bitmask = GENMASK(4, 0) }, + [NSS_CC_GLOBAL_ARES] = { 0x308, 0 }, + [NSS_CC_XPCS_ARES] = { 0x30c, 0 }, +}; + +/* For each read/write operation of clock register, there are three MDIO frames + * sent to the device. + * + * 1. The high address part[23:8] of register is packaged into the first MDIO frame + * for selecting page. + * 2. The low address part[7:0] of register is packaged into the second MDIO frame + * with the low 16bit data to read/write. + * 3. The low address part[7:0] of register is packaged into the last MDIO frame + * with the high 16bit data to read/write. + * + * The clause22 MDIO frame format used by device is as below. + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | ST| OP| ADDR | REG | TA| DATA | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +static inline void convert_reg_to_mii_addr(u32 regaddr, u16 *reg, u16 *phy_addr, u16 *page) +{ + *reg = FIELD_GET(QCA8K_CLK_REG_MASK, regaddr); + *phy_addr = FIELD_GET(QCA8K_CLK_PHY_ADDR_MASK, regaddr) | QCA8K_LOW_ADDR_PREFIX; + *page = FIELD_GET(QCA8K_CLK_PAGE_MASK, regaddr); +} + +static int qca8k_mii_read(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 *val) +{ + int ret, data; + + ret = __mdiobus_read(bus, switch_phy_id, reg); + if (ret >= 0) { + data = ret; + + ret = __mdiobus_read(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS)); + if (ret >= 0) + *val = data | ret << 16; + } + + if (ret < 0) + dev_err_ratelimited(&bus->dev, "fail to read qca8k mii register\n"); + + return ret < 0 ? ret : 0; +} + +static void qca8k_mii_write(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 val) +{ + int ret; + + ret = __mdiobus_write(bus, switch_phy_id, reg, lower_16_bits(val)); + if (ret >= 0) + ret = __mdiobus_write(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS), + upper_16_bits(val)); + + if (ret < 0) + dev_err_ratelimited(&bus->dev, "fail to write qca8k mii register\n"); +} + +static int qca8k_mii_page_set(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u16 page) +{ + int ret; + + ret = __mdiobus_write(bus, switch_phy_id, reg, page); + if (ret < 0) + dev_err_ratelimited(&bus->dev, "fail to set page\n"); + + return ret; +} + +static int qca8k_regmap_read(void *context, unsigned int regaddr, unsigned int *val) +{ + struct mii_bus *bus = context; + u16 reg, phy_addr, page; + int ret; + + regaddr += QCA8K_CLK_REG_BASE; + convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); + + mutex_lock(&bus->mdio_lock); + ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); + if (ret < 0) + goto qca8k_read_exit; + + ret = qca8k_mii_read(bus, phy_addr, reg, val); + +qca8k_read_exit: + mutex_unlock(&bus->mdio_lock); + return ret; +}; + +static int qca8k_regmap_write(void *context, unsigned int regaddr, unsigned int val) +{ + struct mii_bus *bus = context; + u16 reg, phy_addr, page; + int ret; + + regaddr += QCA8K_CLK_REG_BASE; + convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); + + mutex_lock(&bus->mdio_lock); + ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); + if (ret < 0) + goto qca8k_write_exit; + + qca8k_mii_write(bus, phy_addr, reg, val); + +qca8k_write_exit: + mutex_unlock(&bus->mdio_lock); + return ret; +}; + +static int qca8k_regmap_update_bits(void *context, unsigned int regaddr, + unsigned int mask, unsigned int value) +{ + struct mii_bus *bus = context; + u16 reg, phy_addr, page; + int ret; + u32 val; + + regaddr += QCA8K_CLK_REG_BASE; + convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); + + mutex_lock(&bus->mdio_lock); + ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); + if (ret < 0) + goto qca8k_update_exit; + + ret = qca8k_mii_read(bus, phy_addr, reg, &val); + if (ret < 0) + goto qca8k_update_exit; + + val &= ~mask; + val |= value; + qca8k_mii_write(bus, phy_addr, reg, val); + +qca8k_update_exit: + mutex_unlock(&bus->mdio_lock); + return ret; +} + +static const struct regmap_config nss_cc_qca8k_regmap_config = { + .reg_bits = 12, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x30c, + .reg_read = qca8k_regmap_read, + .reg_write = qca8k_regmap_write, + .reg_update_bits = qca8k_regmap_update_bits, + .disable_locking = true, +}; + +static const struct qcom_cc_desc nss_cc_qca8k_desc = { + .config = &nss_cc_qca8k_regmap_config, + .clks = nss_cc_qca8k_clocks, + .num_clks = ARRAY_SIZE(nss_cc_qca8k_clocks), + .resets = nss_cc_qca8k_resets, + .num_resets = ARRAY_SIZE(nss_cc_qca8k_resets), +}; + +/* + * The reference clock of QCA8k NSSCC needs to be enabled to make sure + * the GPIO reset taking effect. + */ +static int nss_cc_qca8k_clock_enable_and_reset(struct device *dev) +{ + struct gpio_desc *gpiod; + struct clk *clk; + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(gpiod)) { + return PTR_ERR(gpiod); + } else if (gpiod) { + msleep(100); + gpiod_set_value_cansleep(gpiod, 0); + } + + return 0; +} + +static int nss_cc_qca8k_probe(struct mdio_device *mdiodev) +{ + struct regmap *regmap; + int ret; + + ret = nss_cc_qca8k_clock_enable_and_reset(&mdiodev->dev); + if (ret) + return dev_err_probe(&mdiodev->dev, ret, "Fail to reset NSSCC\n"); + + regmap = devm_regmap_init(&mdiodev->dev, NULL, mdiodev->bus, nss_cc_qca8k_desc.config); + if (IS_ERR(regmap)) + return dev_err_probe(&mdiodev->dev, PTR_ERR(regmap), "Failed to init regmap\n"); + + return qcom_cc_really_probe(&mdiodev->dev, &nss_cc_qca8k_desc, regmap); +} + +static const struct of_device_id nss_cc_qca8k_match_table[] = { + { .compatible = "qcom,qca8084-nsscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nss_cc_qca8k_match_table); + +static struct mdio_driver nss_cc_qca8k_driver = { + .mdiodrv.driver = { + .name = "qcom,qca8k-nsscc", + .of_match_table = nss_cc_qca8k_match_table, + }, + .probe = nss_cc_qca8k_probe, +}; + +mdio_module_driver(nss_cc_qca8k_driver); + +MODULE_DESCRIPTION("QCOM NSS_CC QCA8K Driver"); +MODULE_LICENSE("GPL"); From 525b42832bd333e3e7ccb0efceb41b47347beab5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jun 2024 13:36:00 +0200 Subject: [PATCH 40/61] dt-bindings: clock: Add Qcom QCM2290 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,qcm2290-gpucc.yaml | 77 +++++++++++++++++++ .../dt-bindings/clock/qcom,qcm2290-gpucc.h | 32 ++++++++ 2 files changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,qcm2290-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml new file mode 100644 index 0000000000000..734880805c1b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCM2290 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,qcm2290-gpucc.h + +properties: + compatible: + const: qcom,qcm2290-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required CX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcm2290-gpucc.h b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h new file mode 100644 index 0000000000000..7c76dd05278fe --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_GFX3D_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GFX3D_CLK 8 +#define GPU_CC_GX_GFX3D_CLK_SRC 9 +#define GPU_CC_PLL0 10 +#define GPU_CC_SLEEP_CLK 11 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From d4d74e4b305bf69ad82b8253ae38fdf54214c5ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jun 2024 13:36:01 +0200 Subject: [PATCH 41/61] clk: qcom: clk-alpha-pll: Add HUAYRA_2290 support Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-2-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-alpha-pll.c | 47 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 3 ++ 2 files changed, 50 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index d4227909d1fe1..08e39334b196f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -93,6 +93,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL] = 0x30, [PLL_OFF_TEST_CTL_U] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_CONFIG_CTL_U1] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_TEST_CTL_U1] = 0x24, + [PLL_OFF_OPMODE] = 0x28, + [PLL_OFF_STATUS] = 0x38, + }, [CLK_ALPHA_PLL_TYPE_BRAMMO] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -788,6 +801,40 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, return clamp(rate, min_freq, max_freq); } +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 val; + + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); + clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); + clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); + clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); + clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); + + /* Set PLL_BYPASSNL */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); + regmap_read(regmap, PLL_MODE(pll), &val); + + /* Wait 5 us between setting BYPASS and deasserting reset */ + udelay(5); + + /* Take PLL out from reset state */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); + regmap_read(regmap, PLL_MODE(pll), &val); + + /* Wait 50us for PLL_LOCK_DET bit to go high */ + usleep_range(50, 55); + + /* Enable PLL output */ + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); +} +EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); + static unsigned long alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index c7055b6c42f1d..df8f0fe155313 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -16,6 +16,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT, CLK_ALPHA_PLL_TYPE_HUAYRA, CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, + CLK_ALPHA_PLL_TYPE_HUAYRA_2290, CLK_ALPHA_PLL_TYPE_BRAMMO, CLK_ALPHA_PLL_TYPE_FABIA, CLK_ALPHA_PLL_TYPE_TRION, @@ -194,6 +195,8 @@ extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); +void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, From 8cab033628b12c6f55aea4170dfe565761336a95 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jun 2024 13:36:02 +0200 Subject: [PATCH 42/61] clk: qcom: Add QCM2290 GPU clock controller driver Add a driver for the GPU clock controller block found on the QCM2290 SoC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-3-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-qcm2290.c | 423 +++++++++++++++++++++++++++++++ 3 files changed, 433 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-qcm2290.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 4432b1cce478c..f72838aa573b6 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -65,6 +65,15 @@ config CLK_X1E80100_TCSRCC Support for the TCSR clock controller on X1E80100 devices. Say Y if you want to use peripheral devices such as SD/UFS. +config CLK_QCM2290_GPUCC + tristate "QCM2290 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_QCM2290_GCC + help + Support for the graphics clock controller on QCM2290 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config QCOM_A53PLL tristate "MSM8916 A53 PLL" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 0241f00689bc0..d52c04f35e740 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o +obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c new file mode 100644 index 0000000000000..dc369dff882e6 --- /dev/null +++ b/drivers/clk/qcom/gpucc-qcm2290.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_GCC_AHB_CLK, + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_AUX, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, +}; + +static const struct pll_vco huayra_vco[] = { + { 600000000, 3300000000, 0 }, + { 600000000, 2200000000, 1 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x25, + .config_ctl_val = 0x200d4828, + .config_ctl_hi_val = 0x6, + .test_ctl_val = GENMASK(28, 26), + .test_ctl_hi_val = BIT(14), + .user_ctl_val = 0xf, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = huayra_vco, + .num_vco = ARRAY_SIZE(huayra_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC, }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC, }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL0_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .hw = &gpu_cc_pll0.clkr.hw, }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC, }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0), + F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR }, + .reset_count = 1, + .pd = { + .name = "gpu_gx_gdsc", + }, + .parent = &gpu_cx_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | AON_RESET | SW_RESET, +}; + +static struct clk_regmap *gpu_cc_qcm2290_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_qcm2290_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, +}; + +static struct gdsc *gpu_cc_qcm2290_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_qcm2290_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + + +static const struct qcom_cc_desc gpu_cc_qcm2290_desc = { + .config = &gpu_cc_qcm2290_regmap_config, + .clks = gpu_cc_qcm2290_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_qcm2290_clocks), + .resets = gpu_cc_qcm2290_resets, + .num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets), + .gdscs = gpu_cc_qcm2290_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs), +}; + +static const struct of_device_id gpu_cc_qcm2290_match_table[] = { + { .compatible = "qcom,qcm2290-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table); + +static int gpu_cc_qcm2290_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = devm_pm_clk_create(&pdev->dev); + if (ret) + return ret; + + ret = pm_clk_add(&pdev->dev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire ahb clock\n"); + return ret; + } + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + + regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */ + + ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register display clock controller\n"); + goto out_pm_runtime_put; + } + +out_pm_runtime_put: + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static struct platform_driver gpu_cc_qcm2290_driver = { + .probe = gpu_cc_qcm2290_probe, + .driver = { + .name = "gpucc-qcm2290", + .of_match_table = gpu_cc_qcm2290_match_table, + }, +}; +module_platform_driver(gpu_cc_qcm2290_driver); + +MODULE_DESCRIPTION("QTI QCM2290 GPU clock controller driver"); +MODULE_LICENSE("GPL"); From e429be706f2a1bd0c9a780793fff6b3784fb4204 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Wed, 19 Jun 2024 08:41:52 -0700 Subject: [PATCH 43/61] clk: qcom: Remove QCOM_RPMCC symbol This symbol is selected by a couple drivers, but isn't used by anyone and hasn't been for years now. Drop it. No functional change intended. Signed-off-by: Elliot Berman Reviewed-by: Mike Tipton Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240619-drop-qcom-rpmcc-v1-1-b487c95162ef@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f72838aa573b6..67c9188d53cb5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -7,9 +7,6 @@ config QCOM_GDSC bool select PM_GENERIC_DOMAINS if PM -config QCOM_RPMCC - bool - menuconfig COMMON_CLK_QCOM tristate "Support for Qualcomm's clock controllers" depends on OF @@ -122,7 +119,6 @@ config QCOM_CLK_APCS_SDX55 config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on MFD_QCOM_RPM - select QCOM_RPMCC help The RPM (Resource Power Manager) is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power @@ -135,7 +131,6 @@ config QCOM_CLK_RPM config QCOM_CLK_SMD_RPM tristate "RPM over SMD based Clock Controller" depends on QCOM_SMD_RPM - select QCOM_RPMCC help The RPM (Resource Power Manager) is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power From f8d1dca6c44dff362102b1f535b6dab552edb760 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 20 Jun 2024 22:14:31 +0200 Subject: [PATCH 44/61] clk: qcom: select right config in CLK_QCM2290_GPUCC definition Commit 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") adds the config CLK_QCM2290_GPUCC, which intends to select the support for the QCM2290 Global Clock Controller. It however selects the non-existing config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock Controller is named QCM_GCC_2290. Adjust the config to the intended one. Signed-off-by: Lukas Bulwahn Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240620201431.93254-1-lukas.bulwahn@redhat.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 67c9188d53cb5..6810291d41a5d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -65,7 +65,7 @@ config CLK_X1E80100_TCSRCC config CLK_QCM2290_GPUCC tristate "QCM2290 Graphics Clock Controller" depends on ARM64 || COMPILE_TEST - select CLK_QCM2290_GCC + select QCM_GCC_2290 help Support for the graphics clock controller on QCM2290 devices. Say Y if you want to support graphics controller devices and From b45120fbd39825ca0d32e39309c30a9e9d567cd8 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Mon, 17 Jun 2024 17:38:06 +0800 Subject: [PATCH 45/61] clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issue The clock controller driver of QCA8K depends on MDIO_BUS because of mdio_module_driver used to register the driver. This patch fixes the following undefined symbols. ERROR: modpost: "mdio_driver_register" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "mdio_driver_unregister" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_write" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_read" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406161634.B27sOs8B-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406162047.QkUMa2fG-lkp@intel.com/ Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20240617093806.3461165-1-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6810291d41a5d..69a3d00c8d573 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -255,7 +255,7 @@ config IPQ_GCC_9574 config IPQ_NSSCC_QCA8K tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" - depends on MDIO_BUS || COMPILE_TEST + depends on MDIO_BUS help Support for NSS(Network SubSystem) clock controller on qca8386/qca8084 chip. From 313e2909023bef36ef7b6d1d9ff2d98febcaa28d Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 21 Jun 2024 17:34:23 +0530 Subject: [PATCH 46/61] clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disable The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Fixes: 160758b05ab1 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov # SM8350-HDK Link: https://lore.kernel.org/r/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sm8350.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c index f6bb8244dd404..f3b6bdc24485b 100644 --- a/drivers/clk/qcom/gpucc-sm8350.c +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -147,7 +148,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .parent_data = gpu_cc_parent_data_0, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -169,7 +170,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = { .parent_data = gpu_cc_parent_data_1, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; From d3b33848627d2b0e02bfcd74ea1671d0d6df3aec Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 12 Jun 2024 16:38:21 +0530 Subject: [PATCH 47/61] clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks The UFS hw ctl clocks are not used by any consumers on SA8775P, and these clocks are not using the correct clock ops to manage the hw ctl of the branch clock, hence remove these clocks. Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-1-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sa8775p.c | 111 +-------------------------------- 1 file changed, 2 insertions(+), 109 deletions(-) diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 9f31ce4cea18b..ec4d842b57123 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -1,14 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2023, Linaro Limited */ -#include #include -#include -#include #include +#include #include #include #include @@ -1737,26 +1735,6 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { }, }; -static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x830d4, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x830d4, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x830d4, - .enable_mask = BIT(1), - .hw.init = &(const struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_aggre_usb2_prim_axi_clk = { .halt_reg = 0x1c05c, .halt_check = BRANCH_HALT_VOTED, @@ -3809,26 +3787,6 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { }, }; -static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { - .halt_reg = 0x83018, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x83018, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x83018, - .enable_mask = BIT(1), - .hw.init = &(const struct clk_init_data){ - .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_ufs_phy_axi_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_ufs_phy_ice_core_clk = { .halt_reg = 0x8306c, .halt_check = BRANCH_HALT_VOTED, @@ -3849,26 +3807,6 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { }, }; -static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { - .halt_reg = 0x8306c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8306c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x8306c, - .enable_mask = BIT(1), - .hw.init = &(const struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_ufs_phy_ice_core_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .halt_reg = 0x830a4, .halt_check = BRANCH_HALT_VOTED, @@ -3889,26 +3827,6 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { }, }; -static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { - .halt_reg = 0x830a4, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x830a4, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x830a4, - .enable_mask = BIT(1), - .hw.init = &(const struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .halt_reg = 0x83028, .halt_check = BRANCH_HALT_DELAY, @@ -3983,26 +3901,6 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { }, }; -static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { - .halt_reg = 0x83064, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x83064, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x83064, - .enable_mask = BIT(1), - .hw.init = &(const struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ - &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_usb20_master_clk = { .halt_reg = 0x1c018, .halt_check = BRANCH_HALT, @@ -4379,7 +4277,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = { [GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr, [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr, [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, @@ -4569,13 +4466,10 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = { [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, @@ -4584,7 +4478,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = { [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr, [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, From be208c0ccf7d861fc6109ca06c1a773512739af9 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 12 Jun 2024 16:38:22 +0530 Subject: [PATCH 48/61] clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags Update the GDSC wait_val fields as per the default hardware values as otherwise they would lead to GDSC FSM state to be stuck and causing failures to power on/off. Also add the GDSC flags as applicable and add support to control PCIE GDSC's using collapse vote registers. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-2-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sa8775p.c | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index ec4d842b57123..b27174b1e2c35 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4203,74 +4203,114 @@ static struct clk_branch gcc_video_axi1_clk = { static struct gdsc pcie_0_gdsc = { .gdscr = 0xa9004, + .collapse_ctrl = 0x4b104, + .collapse_mask = BIT(0), + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "pcie_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc pcie_1_gdsc = { .gdscr = 0x77004, + .collapse_ctrl = 0x4b104, + .collapse_mask = BIT(1), + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "pcie_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc ufs_card_gdsc = { .gdscr = 0x81004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ufs_card_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc ufs_phy_gdsc = { .gdscr = 0x83004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc usb20_prim_gdsc = { .gdscr = 0x1c004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "usb20_prim_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc usb30_prim_gdsc = { .gdscr = 0x1b004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "usb30_prim_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc usb30_sec_gdsc = { .gdscr = 0x2f004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "usb30_sec_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc emac0_gdsc = { .gdscr = 0xb6004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "emac0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct gdsc emac1_gdsc = { .gdscr = 0xb4004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "emac1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; static struct clk_regmap *gcc_sa8775p_clocks[] = { From 955606a7b073d724a50a6ab1119987e189fc3e36 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 12 Jun 2024 16:38:23 +0530 Subject: [PATCH 49/61] clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sa8775p.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index b27174b1e2c35..e7425e82c54f2 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4686,6 +4686,9 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap); } From e69386d4a42afa5da6bfdcd4ac5ec61e1db04c61 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 12 Jun 2024 16:38:24 +0530 Subject: [PATCH 50/61] clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags The GPU clocks/GDSCs have been marked critical from the clock driver but the GPU driver votes on these resources as per the HW requirement. In the case where these clocks & GDSCs are left enabled, would have power impact and also cause GPU stability/corruptions. Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON flags for the GPU GDSCs. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-4-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sa8775p.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c index ac7552b146c77..72920f537f77e 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2023, Linaro Limited */ @@ -280,7 +280,7 @@ static struct clk_branch gpu_cc_ahb_clk = { &gpu_cc_hub_ahb_div_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -294,7 +294,6 @@ static struct clk_branch gpu_cc_cb_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gpu_cc_cb_clk", - .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -312,7 +311,7 @@ static struct clk_branch gpu_cc_crc_ahb_clk = { &gpu_cc_hub_ahb_div_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -330,7 +329,7 @@ static struct clk_branch gpu_cc_cx_ff_clk = { &gpu_cc_ff_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -348,7 +347,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_aon_ops, }, }, @@ -362,7 +361,6 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gpu_cc_cx_snoc_dvm_clk", - .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -380,7 +378,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = { &gpu_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -398,7 +396,7 @@ static struct clk_branch gpu_cc_cxo_clk = { &gpu_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -416,7 +414,7 @@ static struct clk_branch gpu_cc_demet_clk = { &gpu_cc_demet_div_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_aon_ops, }, }, @@ -430,7 +428,6 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", - .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -448,7 +445,7 @@ static struct clk_branch gpu_cc_hub_aon_clk = { &gpu_cc_hub_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_aon_ops, }, }, @@ -466,7 +463,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = { &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_aon_ops, }, }, @@ -480,7 +477,6 @@ static struct clk_branch gpu_cc_memnoc_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gpu_cc_memnoc_gfx_clk", - .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -494,7 +490,6 @@ static struct clk_branch gpu_cc_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gpu_cc_sleep_clk", - .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -533,7 +528,7 @@ static struct gdsc cx_gdsc = { .name = "cx_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE, }; static struct gdsc gx_gdsc = { From dff68b2f74547617dbb75d0d12f404877ec8f8ce Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 12 Jun 2024 16:38:25 +0530 Subject: [PATCH 51/61] clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Also gpu_cc_cb_clk is recommended to be kept always ON, hence use clk_branch2_aon_ops to keep the clock always ON. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sa8775p.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c index 72920f537f77e..6abcdf357c341 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -161,7 +161,7 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = { .name = "gpu_cc_ff_clk_src", .parent_data = gpu_cc_parent_data_0, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -181,7 +181,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .parent_data = gpu_cc_parent_data_1, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -200,7 +200,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = { .name = "gpu_cc_hub_clk_src", .parent_data = gpu_cc_parent_data_2, .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -294,7 +294,7 @@ static struct clk_branch gpu_cc_cb_clk = { .enable_mask = BIT(0), .hw.init = &(const struct clk_init_data){ .name = "gpu_cc_cb_clk", - .ops = &clk_branch2_ops, + .ops = &clk_branch2_aon_ops, }, }, }; From 211681998d706d1e0fff6b62f89efcdf29c24978 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 12 Jun 2024 16:38:26 +0530 Subject: [PATCH 52/61] clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's Update wait_val fields as per the default hardware values of the GDSC as otherwise it would lead to GDSC FSM state stuck causing power on/off failures of the GSDC. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-6-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gpucc-sa8775p.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c index 6abcdf357c341..f8a8ac343d70a 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -523,6 +523,9 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { static struct gdsc cx_gdsc = { .gdscr = 0x9108, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .gds_hw_ctrl = 0x953c, .pd = { .name = "cx_gdsc", @@ -533,6 +536,9 @@ static struct gdsc cx_gdsc = { static struct gdsc gx_gdsc = { .gdscr = 0x905c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gx_gdsc", .power_on = gdsc_gx_do_nothing_enable, From 213e1b58475096e234abf6772183d23513782b5f Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:32 +0530 Subject: [PATCH 53/61] dt-bindings: clock: qcom: Update SM8450 videocc header file name Correct the videocc header file name in SM8450 videocc bindings. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240602114439.1611-2-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d31..b135aa2e9f06b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + See also: include/dt-bindings/clock/qcom,sm8450-videocc.h properties: compatible: From a6a61b9701d1add3bb6d86d8e259d833ea91a1a6 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:33 +0530 Subject: [PATCH 54/61] dt-bindings: clock: qcom: Add SM8650 video clock controller SM8650 video clock controller has most clocks same as SM8450, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm SM8650 platform by defining these additional clocks and resets on top of SM8450. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Reviewed-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-videocc.yaml | 6 ++++- .../dt-bindings/clock/qcom,sm8650-videocc.h | 23 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index b135aa2e9f06b..8ce5972a65d52 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das + - Jagadeesh Kona description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also: include/dt-bindings/clock/qcom,sm8450-videocc.h + See also: + include/dt-bindings/clock/qcom,sm8450-videocc.h + include/dt-bindings/clock/qcom,sm8650-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h new file mode 100644 index 0000000000000..4e3c2d87280fb --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H + +#include "qcom,sm8450-videocc.h" + +/* SM8650 introduces below new clocks and resets compared to SM8450 */ + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_SHIFT_CLK 12 +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 + +/* VIDEO_CC resets */ +#define VIDEO_CC_XO_CLK_ARES 7 + +#endif From 6e18795a6acfd04cec3af23680e9051237d4fa94 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:34 +0530 Subject: [PATCH 55/61] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares Add support for videocc XO clk ares for consumer drivers to be able to request this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240602114439.1611-4-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8550.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d24740..25133cf5a2b82 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = { From da1f361c887c17e34a8c440690a5b3f347802ff7 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:35 +0530 Subject: [PATCH 56/61] clk: qcom: videocc-sm8550: Add SM8650 video clock controller Add support to the SM8650 video clock controller by extending the SM8550 video clock controller, which is mostly identical but SM8650 has few additional clocks and minor differences. Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240602114439.1611-5-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8550.c | 153 +++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index 25133cf5a2b82..c601c35e67248 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = { { 249600000, 2300000000, 0 }, }; -static const struct alpha_pll_config video_cc_pll0_config = { +static struct alpha_pll_config video_cc_pll0_config = { .l = 0x25, .alpha = 0x8000, .config_ctl_val = 0x20485699, @@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = { }, }; -static const struct alpha_pll_config video_cc_pll1_config = { +static struct alpha_pll_config video_cc_pll1_config = { .l = 0x36, .alpha = 0xb000, .config_ctl_val = 0x20485699, @@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = { { .hw = &video_cc_pll1.clkr.hw }, }; +static const struct parent_map video_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, +}; + static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), @@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = { + F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs0_clk_src = { .cmd_rcgr = 0x8000, .mnd_width = 0, @@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = { + F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs1_clk_src = { .cmd_rcgr = 0x8018, .mnd_width = 0, @@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = { }, }; +static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_xo_clk_src = { + .cmd_rcgr = 0x810c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_2, + .freq_tbl = ftbl_video_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_xo_clk_src", + .parent_data = video_cc_parent_data_2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + static struct clk_regmap_div video_cc_mvs0_div_clk_src = { .reg = 0x80c4, .shift = 0, @@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = { }, }; +static struct clk_branch video_cc_mvs0_shift_clk = { + .halt_reg = 0x8128, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8128, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8128, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs0c_clk = { .halt_reg = 0x8064, .halt_check = BRANCH_HALT, @@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = { }, }; +static struct clk_branch video_cc_mvs0c_shift_clk = { + .halt_reg = 0x812c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x812c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x812c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs1_clk = { .halt_reg = 0x80e0, .halt_check = BRANCH_HALT_SKIP, @@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = { }, }; +static struct clk_branch video_cc_mvs1_shift_clk = { + .halt_reg = 0x8130, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8130, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs1c_clk = { .halt_reg = 0x8090, .halt_check = BRANCH_HALT, @@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = { }, }; +static struct clk_branch video_cc_mvs1c_shift_clk = { + .halt_reg = 0x8134, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8134, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc video_cc_mvs0c_gdsc = { .gdscr = 0x804c, .en_rest_wait_val = 0x2, @@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = { [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, + [VIDEO_CC_XO_CLK_SRC] = NULL, }; static struct gdsc *video_cc_sm8550_gdscs[] = { @@ -403,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = { static const struct of_device_id video_cc_sm8550_match_table[] = { { .compatible = "qcom,sm8550-videocc" }, + { .compatible = "qcom,sm8650-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); @@ -411,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; + u32 sleep_clk_offset = 0x8140; ret = devm_pm_runtime_enable(&pdev->dev); if (ret) @@ -426,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) return PTR_ERR(regmap); } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { + sleep_clk_offset = 0x8150; + video_cc_pll0_config.l = 0x1e; + video_cc_pll0_config.alpha = 0xa000; + video_cc_pll1_config.l = 0x2b; + video_cc_pll1_config.alpha = 0xc000; + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650; + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650; + video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; + } + clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */ qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); From 2bce2ce7ab20f85a33c3e45cb57fe8e400d4f2b0 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:36 +0530 Subject: [PATCH 57/61] dt-bindings: clock: qcom: Update the order of SC8280XP camcc header Update the order of SC8280XP camcc header file in SM8450 camcc bindings. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20240602114439.1611-6-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index fa0e5b6b02b81..645080b848f00 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -13,10 +13,10 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8450. - See also:: + See also: + include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h - include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: From 1ae3f0578e0e623e774db45870c0e34c47d8dd15 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:37 +0530 Subject: [PATCH 58/61] dt-bindings: clock: qcom: Add SM8650 camera clock controller Add device tree bindings for the camera clock controller on Qualcomm SM8650 platform. Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski Acked-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20240602114439.1611-7-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-camcc.yaml | 3 + include/dt-bindings/clock/qcom,sm8650-camcc.h | 195 ++++++++++++++++++ 2 files changed, 198 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8650-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 645080b848f00..f58edfc10f4c7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -8,6 +8,7 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450 maintainers: - Vladimir Zapolskiy + - Jagadeesh Kona description: | Qualcomm camera clock control module provides the clocks, resets and power @@ -17,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h + include/dt-bindings/clock/qcom,sm8650-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -28,6 +30,7 @@ properties: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc + - qcom,sm8650-camcc - qcom,x1e80100-camcc clocks: diff --git a/include/dt-bindings/clock/qcom,sm8650-camcc.h b/include/dt-bindings/clock/qcom,sm8650-camcc.h new file mode 100644 index 0000000000000..df73bf35f4bf8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_BPS_SHIFT_CLK 4 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK 6 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7 +#define CAM_CC_CAMNOC_DCD_XO_CLK 8 +#define CAM_CC_CAMNOC_XO_CLK 9 +#define CAM_CC_CCI_0_CLK 10 +#define CAM_CC_CCI_0_CLK_SRC 11 +#define CAM_CC_CCI_1_CLK 12 +#define CAM_CC_CCI_1_CLK_SRC 13 +#define CAM_CC_CCI_2_CLK 14 +#define CAM_CC_CCI_2_CLK_SRC 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPAS_AHB_CLK 17 +#define CAM_CC_CPAS_BPS_CLK 18 +#define CAM_CC_CPAS_CRE_CLK 19 +#define CAM_CC_CPAS_FAST_AHB_CLK 20 +#define CAM_CC_CPAS_IFE_0_CLK 21 +#define CAM_CC_CPAS_IFE_1_CLK 22 +#define CAM_CC_CPAS_IFE_2_CLK 23 +#define CAM_CC_CPAS_IFE_LITE_CLK 24 +#define CAM_CC_CPAS_IPE_NPS_CLK 25 +#define CAM_CC_CPAS_SBI_CLK 26 +#define CAM_CC_CPAS_SFE_0_CLK 27 +#define CAM_CC_CPAS_SFE_1_CLK 28 +#define CAM_CC_CPAS_SFE_2_CLK 29 +#define CAM_CC_CPHY_RX_CLK_SRC 30 +#define CAM_CC_CRE_AHB_CLK 31 +#define CAM_CC_CRE_CLK 32 +#define CAM_CC_CRE_CLK_SRC 33 +#define CAM_CC_CSI0PHYTIMER_CLK 34 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI1PHYTIMER_CLK 36 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI2PHYTIMER_CLK 38 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI3PHYTIMER_CLK 40 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSI4PHYTIMER_CLK 42 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43 +#define CAM_CC_CSI5PHYTIMER_CLK 44 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45 +#define CAM_CC_CSI6PHYTIMER_CLK 46 +#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47 +#define CAM_CC_CSI7PHYTIMER_CLK 48 +#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49 +#define CAM_CC_CSID_CLK 50 +#define CAM_CC_CSID_CLK_SRC 51 +#define CAM_CC_CSID_CSIPHY_RX_CLK 52 +#define CAM_CC_CSIPHY0_CLK 53 +#define CAM_CC_CSIPHY1_CLK 54 +#define CAM_CC_CSIPHY2_CLK 55 +#define CAM_CC_CSIPHY3_CLK 56 +#define CAM_CC_CSIPHY4_CLK 57 +#define CAM_CC_CSIPHY5_CLK 58 +#define CAM_CC_CSIPHY6_CLK 59 +#define CAM_CC_CSIPHY7_CLK 60 +#define CAM_CC_DRV_AHB_CLK 61 +#define CAM_CC_DRV_XO_CLK 62 +#define CAM_CC_FAST_AHB_CLK_SRC 63 +#define CAM_CC_GDSC_CLK 64 +#define CAM_CC_ICP_AHB_CLK 65 +#define CAM_CC_ICP_CLK 66 +#define CAM_CC_ICP_CLK_SRC 67 +#define CAM_CC_IFE_0_CLK 68 +#define CAM_CC_IFE_0_CLK_SRC 69 +#define CAM_CC_IFE_0_FAST_AHB_CLK 70 +#define CAM_CC_IFE_0_SHIFT_CLK 71 +#define CAM_CC_IFE_1_CLK 72 +#define CAM_CC_IFE_1_CLK_SRC 73 +#define CAM_CC_IFE_1_FAST_AHB_CLK 74 +#define CAM_CC_IFE_1_SHIFT_CLK 75 +#define CAM_CC_IFE_2_CLK 76 +#define CAM_CC_IFE_2_CLK_SRC 77 +#define CAM_CC_IFE_2_FAST_AHB_CLK 78 +#define CAM_CC_IFE_2_SHIFT_CLK 79 +#define CAM_CC_IFE_LITE_AHB_CLK 80 +#define CAM_CC_IFE_LITE_CLK 81 +#define CAM_CC_IFE_LITE_CLK_SRC 82 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_CSID_CLK 84 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85 +#define CAM_CC_IPE_NPS_AHB_CLK 86 +#define CAM_CC_IPE_NPS_CLK 87 +#define CAM_CC_IPE_NPS_CLK_SRC 88 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89 +#define CAM_CC_IPE_PPS_CLK 90 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91 +#define CAM_CC_IPE_SHIFT_CLK 92 +#define CAM_CC_JPEG_1_CLK 93 +#define CAM_CC_JPEG_CLK 94 +#define CAM_CC_JPEG_CLK_SRC 95 +#define CAM_CC_MCLK0_CLK 96 +#define CAM_CC_MCLK0_CLK_SRC 97 +#define CAM_CC_MCLK1_CLK 98 +#define CAM_CC_MCLK1_CLK_SRC 99 +#define CAM_CC_MCLK2_CLK 100 +#define CAM_CC_MCLK2_CLK_SRC 101 +#define CAM_CC_MCLK3_CLK 102 +#define CAM_CC_MCLK3_CLK_SRC 103 +#define CAM_CC_MCLK4_CLK 104 +#define CAM_CC_MCLK4_CLK_SRC 105 +#define CAM_CC_MCLK5_CLK 106 +#define CAM_CC_MCLK5_CLK_SRC 107 +#define CAM_CC_MCLK6_CLK 108 +#define CAM_CC_MCLK6_CLK_SRC 109 +#define CAM_CC_MCLK7_CLK 110 +#define CAM_CC_MCLK7_CLK_SRC 111 +#define CAM_CC_PLL0 112 +#define CAM_CC_PLL0_OUT_EVEN 113 +#define CAM_CC_PLL0_OUT_ODD 114 +#define CAM_CC_PLL1 115 +#define CAM_CC_PLL1_OUT_EVEN 116 +#define CAM_CC_PLL2 117 +#define CAM_CC_PLL3 118 +#define CAM_CC_PLL3_OUT_EVEN 119 +#define CAM_CC_PLL4 120 +#define CAM_CC_PLL4_OUT_EVEN 121 +#define CAM_CC_PLL5 122 +#define CAM_CC_PLL5_OUT_EVEN 123 +#define CAM_CC_PLL6 124 +#define CAM_CC_PLL6_OUT_EVEN 125 +#define CAM_CC_PLL7 126 +#define CAM_CC_PLL7_OUT_EVEN 127 +#define CAM_CC_PLL8 128 +#define CAM_CC_PLL8_OUT_EVEN 129 +#define CAM_CC_PLL9 130 +#define CAM_CC_PLL9_OUT_EVEN 131 +#define CAM_CC_PLL9_OUT_ODD 132 +#define CAM_CC_PLL10 133 +#define CAM_CC_PLL10_OUT_EVEN 134 +#define CAM_CC_QDSS_DEBUG_CLK 135 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 136 +#define CAM_CC_QDSS_DEBUG_XO_CLK 137 +#define CAM_CC_SBI_CLK 138 +#define CAM_CC_SBI_FAST_AHB_CLK 139 +#define CAM_CC_SBI_SHIFT_CLK 140 +#define CAM_CC_SFE_0_CLK 141 +#define CAM_CC_SFE_0_CLK_SRC 142 +#define CAM_CC_SFE_0_FAST_AHB_CLK 143 +#define CAM_CC_SFE_0_SHIFT_CLK 144 +#define CAM_CC_SFE_1_CLK 145 +#define CAM_CC_SFE_1_CLK_SRC 146 +#define CAM_CC_SFE_1_FAST_AHB_CLK 147 +#define CAM_CC_SFE_1_SHIFT_CLK 148 +#define CAM_CC_SFE_2_CLK 149 +#define CAM_CC_SFE_2_CLK_SRC 150 +#define CAM_CC_SFE_2_FAST_AHB_CLK 151 +#define CAM_CC_SFE_2_SHIFT_CLK 152 +#define CAM_CC_SLEEP_CLK 153 +#define CAM_CC_SLEEP_CLK_SRC 154 +#define CAM_CC_SLOW_AHB_CLK_SRC 155 +#define CAM_CC_TITAN_TOP_SHIFT_CLK 156 +#define CAM_CC_XO_CLK_SRC 157 + +/* CAM_CC power domains */ +#define CAM_CC_TITAN_TOP_GDSC 0 +#define CAM_CC_BPS_GDSC 1 +#define CAM_CC_IFE_0_GDSC 2 +#define CAM_CC_IFE_1_GDSC 3 +#define CAM_CC_IFE_2_GDSC 4 +#define CAM_CC_IPE_0_GDSC 5 +#define CAM_CC_SBI_GDSC 6 +#define CAM_CC_SFE_0_GDSC 7 +#define CAM_CC_SFE_1_GDSC 8 +#define CAM_CC_SFE_2_GDSC 9 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_DRV_BCR 1 +#define CAM_CC_ICP_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_QDSS_DEBUG_BCR 7 +#define CAM_CC_SBI_BCR 8 +#define CAM_CC_SFE_0_BCR 9 +#define CAM_CC_SFE_1_BCR 10 +#define CAM_CC_SFE_2_BCR 11 + +#endif From 09ea421652a832083ea380a72addf383965f3682 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Sun, 2 Jun 2024 17:14:38 +0530 Subject: [PATCH 59/61] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8650 platform. Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20240602114439.1611-8-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sm8650.c | 3591 +++++++++++++++++++++++++++++++ 3 files changed, 3600 insertions(+) create mode 100644 drivers/clk/qcom/camcc-sm8650.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1bb51a0588726..46369edfc07ab 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -827,6 +827,14 @@ config SM_CAMCC_8550 Support for the camera clock controller on SM8550 devices. Say Y if you want to support camera devices and camera functionality. +config SM_CAMCC_8650 + tristate "SM8650 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8650 + help + Support for the camera clock controller on SM8650 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_DISPCC_6115 tristate "SM6115 Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec5b6db6860c..28bffa1eb8dd5 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o +obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm8650.c new file mode 100644 index 0000000000000..a37e52a67ed4d --- /dev/null +++ b/drivers/clk/qcom/camcc-sm8650.c @@ -0,0 +1,3591 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL7_OUT_EVEN, + P_CAM_CC_PLL8_OUT_EVEN, + P_CAM_CC_PLL9_OUT_EVEN, + P_CAM_CC_PLL9_OUT_ODD, + P_CAM_CC_PLL10_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco rivian_ole_vco[] = { + { 777000000, 1285000000, 0 }, +}; + +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x31, + .alpha = 0x7aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x10000030, + .config_ctl_hi_val = 0x80890263, + .config_ctl_hi1_val = 0x00000217, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .vco_table = rivian_ole_vco, + .num_vco = ARRAY_SIZE(rivian_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll5_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll5 = { + .offset = 0x5000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { + .offset = 0x5000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll5_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll6_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll6 = { + .offset = 0x6000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { + .offset = 0x6000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll7_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll7 = { + .offset = 0x7000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { + .offset = 0x7000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll7_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll8_config = { + .l = 0x14, + .alpha = 0xd555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll8 = { + .offset = 0x8000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { + .offset = 0x8000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll8_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll9_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll9 = { + .offset = 0x9000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = { + .offset = 0x9000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll9_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = { + .offset = 0x9000, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll9_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll10_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll10 = { + .offset = 0xa000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll10", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = { + .offset = 0xa000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll10_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll10_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll10.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL9_OUT_ODD, 4 }, + { P_CAM_CC_PLL9_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll9_out_odd.clkr.hw }, + { .hw = &cam_cc_pll9_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2.clkr.hw }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL8_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll8_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL7_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll7_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL10_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll10_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_10[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_10[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_11_ao[] = { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_11_ao[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x10050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { + .cmd_rcgr = 0x1325c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x131cc, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x131e8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src = { + .cmd_rcgr = 0x13204, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x1104c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cre_clk_src = { + .cmd_rcgr = 0x13144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cre_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x150e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x15104, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x15124, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x15144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x15164, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { + .cmd_rcgr = 0x15184, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = { + .cmd_rcgr = 0x151a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi6phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = { + .cmd_rcgr = 0x151c4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi7phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x13238, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x10018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0x131a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_icp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src = { + .cmd_rcgr = 0x12018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_2_clk_src = { + .cmd_rcgr = 0x12068, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_ife_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x13028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { + F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { + .cmd_rcgr = 0x10094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6, + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk_src", + .parent_data = cam_cc_parent_data_6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0x13168, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4), + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x15000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x1501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x15038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x15054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x15070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x1508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x150a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk7_clk_src = { + .cmd_rcgr = 0x150c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x1329c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { + F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_0_clk_src = { + .cmd_rcgr = 0x1306c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_7, + .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk_src", + .parent_data = cam_cc_parent_data_7, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { + F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_1_clk_src = { + .cmd_rcgr = 0x130bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_8, + .freq_tbl = ftbl_cam_cc_sfe_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk_src", + .parent_data = cam_cc_parent_data_8, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = { + F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_2_clk_src = { + .cmd_rcgr = 0x1310c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_9, + .freq_tbl = ftbl_cam_cc_sfe_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_clk_src", + .parent_data = cam_cc_parent_data_9, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x132f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_10, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_10, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x10034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x132d4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_11_ao, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_11_ao, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x1004c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1004c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x10068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_fast_ahb_clk = { + .halt_reg = 0x10030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_shift_clk = { + .halt_reg = 0x10078, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x10078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { + .halt_reg = 0x13284, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13284, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_nrt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_rt_clk = { + .halt_reg = 0x13274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x13290, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13290, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk = { + .halt_reg = 0x13294, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13294, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x131e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x13200, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13200, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk = { + .halt_reg = 0x1321c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1321c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0x132d0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x132d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0x13220, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13220, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_bps_clk = { + .halt_reg = 0x10074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_cre_clk = { + .halt_reg = 0x13160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_cre_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { + .halt_reg = 0x1322c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1322c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk = { + .halt_reg = 0x1103c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1103c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_1_clk = { + .halt_reg = 0x1203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1203c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_2_clk = { + .halt_reg = 0x1208c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1208c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk = { + .halt_reg = 0x13024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { + .halt_reg = 0x100b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sbi_clk = { + .halt_reg = 0x10104, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10104, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sbi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_0_clk = { + .halt_reg = 0x13090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_1_clk = { + .halt_reg = 0x130e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_2_clk = { + .halt_reg = 0x13130, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_ahb_clk = { + .halt_reg = 0x13164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_clk = { + .halt_reg = 0x1315c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1315c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x150f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x1511c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1511c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x1513c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1513c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x1515c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1515c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x1517c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1517c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk = { + .halt_reg = 0x1519c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1519c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi6phytimer_clk = { + .halt_reg = 0x151bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi6phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi6phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi7phytimer_clk = { + .halt_reg = 0x151dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi7phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi7phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x13250, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13250, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x150fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x15140, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x15160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x15180, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15180, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk = { + .halt_reg = 0x151a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy6_clk = { + .halt_reg = 0x151c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy7_clk = { + .halt_reg = 0x151e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0x131c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0x131bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0x11030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { + .halt_reg = 0x11048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_shift_clk = { + .halt_reg = 0x11064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x11064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk = { + .halt_reg = 0x12030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { + .halt_reg = 0x12048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_shift_clk = { + .halt_reg = 0x1204c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1204c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_clk = { + .halt_reg = 0x12080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_fast_ahb_clk = { + .halt_reg = 0x12098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_shift_clk = { + .halt_reg = 0x1209c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1209c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x13018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x1304c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1304c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x13040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { + .halt_reg = 0x100d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk = { + .halt_reg = 0x100ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { + .halt_reg = 0x100d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk = { + .halt_reg = 0x100bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { + .halt_reg = 0x100d8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_shift_clk = { + .halt_reg = 0x100dc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x100dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_1_clk = { + .halt_reg = 0x1318c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1318c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0x13180, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13180, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x15018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x15034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x15050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x1506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1506c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x15088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x150a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x150c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk7_clk = { + .halt_reg = 0x150dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x132b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x132b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_clk = { + .halt_reg = 0x100f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_fast_ahb_clk = { + .halt_reg = 0x10108, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10108, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_shift_clk = { + .halt_reg = 0x1010c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1010c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_clk = { + .halt_reg = 0x13084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { + .halt_reg = 0x1309c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1309c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_shift_clk = { + .halt_reg = 0x130a0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x130a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_clk = { + .halt_reg = 0x130d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = { + .halt_reg = 0x130ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_shift_clk = { + .halt_reg = 0x130f0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x130f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_clk = { + .halt_reg = 0x13124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13124, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = { + .halt_reg = 0x1313c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1313c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_shift_clk = { + .halt_reg = 0x13140, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x13140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_titan_top_shift_clk = { + .halt_reg = 0x1330c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1330c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_titan_top_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc = { + .gdscr = 0x132bc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_bps_gdsc = { + .gdscr = 0x10004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_bps_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc = { + .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_1_gdsc = { + .gdscr = 0x12004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_2_gdsc = { + .gdscr = 0x12054, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc = { + .gdscr = 0x10080, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sbi_gdsc = { + .gdscr = 0x100e4, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sbi_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_0_gdsc = { + .gdscr = 0x13058, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_1_gdsc = { + .gdscr = 0x130a8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_2_gdsc = { + .gdscr = 0x130f8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_sm8650_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, + [CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr, + [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, + [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, + [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, + [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr, + [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, + [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr, + [CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, + [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, + [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr, + [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr, + [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr, + [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, + [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr, + [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr, + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr, + [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, + [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, + [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr, + [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL7] = &cam_cc_pll7.clkr, + [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, + [CAM_CC_PLL8] = &cam_cc_pll8.clkr, + [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, + [CAM_CC_PLL9] = &cam_cc_pll9.clkr, + [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr, + [CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr, + [CAM_CC_PLL10] = &cam_cc_pll10.clkr, + [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, + [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr, + [CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr, + [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, + [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, + [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr, + [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr, + [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr, + [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr, + [CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr, + [CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr, + [CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr, + [CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr, + [CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_sm8650_gdscs[] = { + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, + [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, + [CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc, + [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, + [CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc, + [CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc, +}; + +static const struct qcom_reset_map cam_cc_sm8650_resets[] = { + [CAM_CC_BPS_BCR] = { 0x10000 }, + [CAM_CC_DRV_BCR] = { 0x13310 }, + [CAM_CC_ICP_BCR] = { 0x131a0 }, + [CAM_CC_IFE_0_BCR] = { 0x11000 }, + [CAM_CC_IFE_1_BCR] = { 0x12000 }, + [CAM_CC_IFE_2_BCR] = { 0x12050 }, + [CAM_CC_IPE_0_BCR] = { 0x1007c }, + [CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 }, + [CAM_CC_SBI_BCR] = { 0x100e0 }, + [CAM_CC_SFE_0_BCR] = { 0x13054 }, + [CAM_CC_SFE_1_BCR] = { 0x130a4 }, + [CAM_CC_SFE_2_BCR] = { 0x130f4 }, +}; + +static const struct regmap_config cam_cc_sm8650_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1603c, + .fast_io = true, +}; + +static struct qcom_cc_desc cam_cc_sm8650_desc = { + .config = &cam_cc_sm8650_regmap_config, + .clks = cam_cc_sm8650_clocks, + .num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks), + .resets = cam_cc_sm8650_resets, + .num_resets = ARRAY_SIZE(cam_cc_sm8650_resets), + .gdscs = cam_cc_sm8650_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs), +}; + +static const struct of_device_id cam_cc_sm8650_match_table[] = { + { .compatible = "qcom,sm8650-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table); + +static int cam_cc_sm8650_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); + clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); + clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); + clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); + clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); + + /* Keep clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */ + + ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver cam_cc_sm8650_driver = { + .probe = cam_cc_sm8650_probe, + .driver = { + .name = "camcc-sm8650", + .of_match_table = cam_cc_sm8650_match_table, + }, +}; + +module_platform_driver(cam_cc_sm8650_driver); + +MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver"); +MODULE_LICENSE("GPL"); From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 20 Jun 2024 23:01:21 +0800 Subject: [PATCH 60/61] clk: qcom: gcc-ipq6018: update sdcc max clock frequency The mmc controller of the IPQ6018 does not support HS400 mode. So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq6018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 9e58851013663..2e411d874662c 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { F(96000000, P_GPLL2, 12, 0, 0), F(177777778, P_GPLL0, 4.5, 0, 0), F(192000000, P_GPLL2, 6, 0, 0), - F(384000000, P_GPLL2, 3, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), { } }; From f27e42c7d3ff8ddfc57273efd1e8642ea89bad90 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 28 Jun 2024 11:08:00 +0300 Subject: [PATCH 61/61] clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks In case of all pipe clocks, there is a QMP PHY clock that is feeding them. If, for whatever reason, the clock from the PHY is not enabled, halt bit will not get set, and the clock controller driver will assume the clock is stuck in a specific state. The way this is supposed to be properly fixed is to defer the checking of the halt bit until after the PHY clock has been initialized, but doing so complicates the clock controller driver. In fact, since these pipe clocks are consumed by the PHY, while the PHY is also the one providing the source, if clock gets stuck, the PHY driver would be to blame. So instead of checking the halt bit in here, just skip it and assume the PHY driver is handling the source clock correctly. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by: Abel Vesa Reviewed-by: Taniya Das Link: https://lore.kernel.org/r/20240628-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v2-1-db3be54b1143@linaro.org Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-x1e80100.c | 44 ++++++++++++++++----------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c index eb7e36ebd7ae5..fc80011342dae 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -2812,7 +2812,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0xa0044, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52010, .enable_mask = BIT(25), @@ -2901,7 +2901,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x2c044, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52020, .enable_mask = BIT(30), @@ -2990,7 +2990,7 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { static struct clk_branch gcc_pcie_2_pipe_clk = { .halt_reg = 0x13044, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52020, .enable_mask = BIT(23), @@ -3110,7 +3110,7 @@ static struct clk_branch gcc_pcie_3_phy_rchng_clk = { static struct clk_branch gcc_pcie_3_pipe_clk = { .halt_reg = 0x58050, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52020, .enable_mask = BIT(3), @@ -3235,7 +3235,7 @@ static struct clk_branch gcc_pcie_4_phy_rchng_clk = { static struct clk_branch gcc_pcie_4_pipe_clk = { .halt_reg = 0x6b044, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52008, .enable_mask = BIT(4), @@ -3360,7 +3360,7 @@ static struct clk_branch gcc_pcie_5_phy_rchng_clk = { static struct clk_branch gcc_pcie_5_pipe_clk = { .halt_reg = 0x2f044, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52018, .enable_mask = BIT(17), @@ -3498,7 +3498,7 @@ static struct clk_branch gcc_pcie_6a_phy_rchng_clk = { static struct clk_branch gcc_pcie_6a_pipe_clk = { .halt_reg = 0x31050, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52018, .enable_mask = BIT(26), @@ -3636,7 +3636,7 @@ static struct clk_branch gcc_pcie_6b_phy_rchng_clk = { static struct clk_branch gcc_pcie_6b_pipe_clk = { .halt_reg = 0x8d050, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(30), @@ -5109,7 +5109,7 @@ static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = { static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { .halt_reg = 0x17290, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x17290, .enable_mask = BIT(0), @@ -5122,7 +5122,7 @@ static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = { static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = { .halt_reg = 0x17298, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x17298, .enable_mask = BIT(0), @@ -5186,7 +5186,7 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { .halt_reg = 0x39068, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .hwcg_reg = 0x39068, .hwcg_bit = 1, .clkr = { @@ -5257,7 +5257,7 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { .halt_reg = 0xa1068, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .hwcg_reg = 0xa1068, .hwcg_bit = 1, .clkr = { @@ -5327,7 +5327,7 @@ static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = { static struct clk_branch gcc_usb3_tert_phy_pipe_clk = { .halt_reg = 0xa2068, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .hwcg_reg = 0xa2068, .hwcg_bit = 1, .clkr = { @@ -5405,7 +5405,7 @@ static struct clk_branch gcc_usb4_0_master_clk = { static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { .halt_reg = 0x9f0d8, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x9f0d8, .enable_mask = BIT(0), @@ -5418,7 +5418,7 @@ static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = { static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = { .halt_reg = 0x9f048, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52010, .enable_mask = BIT(19), @@ -5457,7 +5457,7 @@ static struct clk_branch gcc_usb4_0_phy_rx1_clk = { static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = { .halt_reg = 0x9f0a4, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .hwcg_reg = 0x9f0a4, .hwcg_bit = 1, .clkr = { @@ -5582,7 +5582,7 @@ static struct clk_branch gcc_usb4_1_master_clk = { static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { .halt_reg = 0x2b0d8, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x2b0d8, .enable_mask = BIT(0), @@ -5595,7 +5595,7 @@ static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = { static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = { .halt_reg = 0x2b048, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52028, .enable_mask = BIT(0), @@ -5634,7 +5634,7 @@ static struct clk_branch gcc_usb4_1_phy_rx1_clk = { static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = { .halt_reg = 0x2b0a4, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .hwcg_reg = 0x2b0a4, .hwcg_bit = 1, .clkr = { @@ -5759,7 +5759,7 @@ static struct clk_branch gcc_usb4_2_master_clk = { static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { .halt_reg = 0x110d8, - .halt_check = BRANCH_HALT, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x110d8, .enable_mask = BIT(0), @@ -5772,7 +5772,7 @@ static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = { static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = { .halt_reg = 0x11048, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52028, .enable_mask = BIT(1), @@ -5811,7 +5811,7 @@ static struct clk_branch gcc_usb4_2_phy_rx1_clk = { static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = { .halt_reg = 0x110a4, - .halt_check = BRANCH_HALT_VOTED, + .halt_check = BRANCH_HALT_SKIP, .hwcg_reg = 0x110a4, .hwcg_bit = 1, .clkr = {