From f0f838fd8cd53d8df8220b4081d7dec042ac9dd7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:37 -0700 Subject: [PATCH 01/14] ARM: dts: Add missing dma hwmods property for omap3 On omap3, we are missing a ti,hwmods property for dma that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index bdaf30c8c4057..90b5c7148feb5 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -215,6 +215,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <96>; + ti,hwmods = "dma"; }; gpio1: gpio@48310000 { From b0142a10db149daadbc2cc94c890dd00b3fa58ad Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:38 -0700 Subject: [PATCH 02/14] ARM: dts: Configure pmu without interrupt for omap4430 On omap4430, the PMU is not configure unlike on omap4460 because of the missing handling. The missing pmu node with the missing ti,hwmods entry will cause boot time errors when the legacy platform data is removed as the SoC interconnect code needs it. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's fix the issue by configuring PMU but without the interrupts. Then when cross trigger interface (CTI) is supported, we can add interrupts also for omap4430. Cc: Jon Hunter Cc: Will Deacon Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 64d00f5893a63..47bc41954e2ed 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -51,6 +51,17 @@ }; }; + /* + * Note that 4430 needs cross trigger interface (CTI) supported + * before we can configure the interrupts. This means sampling + * events are not supported for pmu. Note that 4460 does not use + * CTI, see also 4460.dtsi. + */ + pmu { + compatible = "arm,cortex-a9-pmu"; + ti,hwmods = "debugss"; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; From 1d6a332ae8b7d8eacb9fe4c0a09370550f0b3eee Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:39 -0700 Subject: [PATCH 03/14] ARM: dts: Add missing properties for omap4 control modules On omap4, we are missing several ti,hwmods properties and IO ranges for system control modules. These are needed by the SoC interconnect code. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. In order to add these, we need to move omap4_pmx_wkup to be a child of omap4_padconf_wkup. On omap4 there are separate modules for control module and control module pads. For control module core, we have this already configured except for the missing ti,hwmods and reg entries. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/arm/omap/ctrl.txt | 2 + arch/arm/boot/dts/omap4.dtsi | 39 ++++++++++++++----- 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index 3a4e5901ce31b..ce8dabf8c0f97 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -21,6 +21,8 @@ Required properties: "ti,omap3-scm" "ti,omap4-scm-core" "ti,omap4-scm-padconf-core" + "ti,omap4-scm-wkup" + "ti,omap4-scm-padconf-wkup" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" "ti,dra7-scm-core" diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 47bc41954e2ed..16ec0bd292098 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -174,6 +174,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x1000>; + ti,hwmods = "ctrl_module_core"; scm_conf: scm_conf@0 { compatible = "syscon"; @@ -186,9 +187,11 @@ omap4_padconf_core: scm@100000 { compatible = "ti,omap4-scm-padconf-core", "simple-bus"; + reg = <0x100000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x100000 0x1000>; + ti,hwmods = "ctrl_module_pad_core"; omap4_pmx_core: pinmux@40 { compatible = "ti,omap4-padconf", @@ -263,17 +266,33 @@ }; }; - omap4_pmx_wkup: pinmux@1e040 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x1e040 0x0038>; + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + ti,hwmods = "ctrl_module_wkup"; + }; + + omap4_padconf_wkup: padconf@1e000 { + compatible = "ti,omap4-scm-padconf-wkup", + "simple-bus"; + reg = <0x1e000 0x1000>; #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; + #size-cells = <1>; + ranges = <0 0x1e000 0x1000>; + ti,hwmods = "ctrl_module_pad_wkup"; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; }; From 370ad6b4670adfc3c5c7d5aad63347e8db839762 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:40 -0700 Subject: [PATCH 04/14] ARM: dts: Add missing hwmods property for omap4 dma On omap4, we are missing a ti,hwmods property for dma that the that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 16ec0bd292098..24a3f70f1eef3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -312,6 +312,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4a310000 { From 514b2da46fcc10bd5f42446b9fa746ba2c80aaf1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:41 -0700 Subject: [PATCH 05/14] ARM: dts: Add missing smartreflex node and binding for omap4 We are missing smartreflex device tree nodes for omap4 with their related "ti,hwmods" properties that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. And since we're missing the device tree binding for smartreflex, let's also add it and document the existing omap3 use too. Note that the related driver also needs to be updated to probe using device tree and get the platform data passed to it using auxdata with arch/arm/mach-omap2/pdata-quirks.c. Cc: Mark Rutland Cc: Nishanth Menon Cc: Rafael J. Wysocki Cc: Tero Kristo Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../bindings/power/ti-smartreflex.txt | 47 +++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 21 +++++++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/ti-smartreflex.txt diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt new file mode 100644 index 0000000000000..9780957c91153 --- /dev/null +++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt @@ -0,0 +1,47 @@ +Texas Instruments SmartReflex binding + +SmartReflex is used to set and adjust the SoC operating points. + + +Required properties: + +compatible: Shall be one of the following: + "ti,omap3-smartreflex-core" + "ti,omap3-smartreflex-iva" + "ti,omap4-smartreflex-core" + "ti,omap4-smartreflex-mpu" + "ti,omap4-smartreflex-iva" + +reg: Shall contain the device instance IO range + +interrupts: Shall contain the device instance interrupt + + +Optional properties: + +ti,hwmods: Shall contain the TI interconnect module name if needed + by the SoC + + +Example: + + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_mpu"; + }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 24a3f70f1eef3..c48b7e8713ca5 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -442,6 +442,27 @@ clock-frequency = <48000000>; }; + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = ; + ti,hwmods = "smartreflex_mpu"; + }; + hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; From d6e1a2381694c9a15f5a2ea9877fd20017470e95 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:43 -0700 Subject: [PATCH 06/14] ARM: dts: Add missing onewire node for omap4 On omap4 we're missing the onewire node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index c48b7e8713ca5..69d129b420e01 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -541,6 +541,13 @@ dma-names = "tx0", "rx0", "tx1", "rx1"; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = ; + ti,hwmods = "hdq1w"; + }; + mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; From 8be8576fcf2d90a8bc679bfb25a4121d0eebe0de Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 13:25:20 -0700 Subject: [PATCH 07/14] ARM: dts: Add missing hsi node for omap4 On omap4 we're missing the hsi node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's also update the binding accrodingly while at it. Cc: Mark Rutland Cc: Rob Herring Reviewed-by: Sebastian Reichel Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/hsi/omap-ssi.txt | 13 +++++-- arch/arm/boot/dts/omap4.dtsi | 34 +++++++++++++++++++ 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/hsi/omap-ssi.txt b/Documentation/devicetree/bindings/hsi/omap-ssi.txt index b8eca3c7810df..955e335e7e569 100644 --- a/Documentation/devicetree/bindings/hsi/omap-ssi.txt +++ b/Documentation/devicetree/bindings/hsi/omap-ssi.txt @@ -1,10 +1,12 @@ OMAP SSI controller bindings -OMAP Synchronous Serial Interface (SSI) controller implements a legacy -variant of MIPI's High Speed Synchronous Serial Interface (HSI). +OMAP3's Synchronous Serial Interface (SSI) controller implements a +legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI), +while the controller found inside OMAP4 is supposed to be fully compliant +with the HSI standard. Required properties: -- compatible: Should include "ti,omap3-ssi". +- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi" - reg-names: Contains the values "sys" and "gdd" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device. Required Port sub-node properties: - compatible: Should be set to the following value ti,omap3-ssi-port (applicable to OMAP34xx devices) + ti,omap4-hsi-port (applicable to OMAP44xx devices) - reg-names: Contains the values "tx" and "rx" (in this order). - reg: Contains a matching register specifier for each entry in reg-names. @@ -38,6 +41,10 @@ Required Port sub-node properties: property. If it's missing the port will not be enabled. +Optional properties: +- ti,hwmods: Shall contain TI interconnect module name if needed + by the SoC + Example for Nokia N900: ssi-controller@48058000 { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 69d129b420e01..a3c4d3541e3d3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -624,6 +624,40 @@ dma-names = "tx", "rx"; }; + hsi: hsi@4a058000 { + compatible = "ti,omap4-hsi"; + reg = <0x4a058000 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + ti,hwmods = "hsi"; + + clocks = <&hsi_fck>; + clock-names = "hsi_fck"; + + interrupts = ; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a058000 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = ; + }; + }; + mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; From 5750d6717b54ac9461912264710a3b60cda153bb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:46 -0700 Subject: [PATCH 08/14] ARM: dts: Add missing wdt3 node for omap4 On omap4 we're missing the wdt3 node with it's related "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index a3c4d3541e3d3..70ecd840772d5 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -682,6 +682,14 @@ ti,hwmods = "wd_timer2"; }; + wdt3: wdt@40130000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x40130000 0x80>, /* MPU private access */ + <0x49030000 0x80>; /* L3 Interconnect */ + interrupts = ; + ti,hwmods = "wd_timer3"; + }; + mcpdm: mcpdm@40132000 { compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ From ef90bfb8be2b0f7f1d9308ff3defa1b441c661f9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:51 -0700 Subject: [PATCH 09/14] ARM: dts: Add missing dma hwmod property for omap5 On omap5 we're missing the dma "ti,hwmods" property that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index eaff2a5751ddc..b86ac7df620d5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -295,6 +295,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4ae10000 { From cd57dc5a2099a43c99fb39cb7c953246149db816 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:52 -0700 Subject: [PATCH 10/14] ARM: dts: Add missing hwmod related nodes for am33xx On am33xx we're missing the pmu and emif nodes with their related "ti,hwmods" properties that the SoC interconnect code needs. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's also update the related binding documentation while at it. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/memory-controllers/ti/emif.txt | 6 ++++-- arch/arm/boot/dts/am33xx.dtsi | 10 +++++++++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 0db60470ebb6a..fd823d6091b29 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it. Required properties: - compatible : Should be of the form "ti,emif-" where - is the IP revision of the specific EMIF instance. - For am437x should be ti,emif-am4372. + is the IP revision of the specific EMIF instance. For newer controllers, + compatible should be one of the following: + "ti,emif-am3352" + "ti,emif-am4372" - phy-type : indicating the DDR phy type. Following are the allowed values diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7d7ca054c557b..08653552db713 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -128,9 +128,11 @@ }; }; - pmu { + pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; + reg = <0x4b000000 0x1000000>; + ti,hwmods = "debugss"; }; /* @@ -927,6 +929,12 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; From 288cdbbff2dcfc5188a708a9a3e7aaedc41512f1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 30 Aug 2017 08:19:53 -0700 Subject: [PATCH 11/14] ARM: dts: Add missing hwmod related properties for dra7 On dra7 we're missing two "ti,hwmods" properties that the SoC interconnect code needs. For hdq 1-wire, we need to add the node for that. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Cc: Nishanth Menon Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 02a136a4661aa..a33023ca4390a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -457,6 +457,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; edma: edma@43300000 { @@ -1069,6 +1070,13 @@ max-frequency = <192000000>; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = ; + ti,hwmods = "hdq1w"; + }; + mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; From b6891523fe9915dfa868773db638832454316788 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 10 Oct 2017 14:14:40 -0700 Subject: [PATCH 12/14] dt-bindings: bus: Minimal TI sysc interconnect target module binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the recently introduced omap clkctrl module binding, we can start moving omap hwmod data to device tree and drivers from arch/arm/mach-omap2. To start doing this, let's introduce a device tree binding for TI sysc interconnect target module hardware. The sysc manages module clocks, idlemodes and interconnect level resets. Each interconnect target module can have one or more child devices connected to it. TI sysc interconnect target module hardware is independent of the interconnect. It is used at least with TI L3 interconnect (Arteris NoC) and TI L4 interconnect (Sonics s3220). The sysc is mostly used for interaction between module and PRCM. It participates in the OCP Disconnect Protocol but other than that is mostly indepenent of the interconnect. As all the features may not be supported for a given sysc module, we need to use device tree configuration for the revision of the interconnect target module. Note that the interconnect target module control registers are always sprinked at varying locations in the unused address space of the first child device IP block. To avoid device tree reg conflicts, the sysc device provides ranges for it's children. For a non-intrusive transition from static hwmod data to using device tree defined TI interconnect target module binding, we can keep things working with static hwmod data if device tree property "ti,hwmods" is specified for the the interconnect target module. Note that additional properties for sysc capabilities will be added later on. For now, we can already use this binding for interconnect target modules that do not have any child device drivers available. This allows us to idle the unused interconnect target modules during init without the need for legacy hwmod platform data for doing it. Cc: Benoît Cousson Cc: Dave Gerlach Cc: Laurent Pinchart Cc: Liam Girdwood Cc: Mark Brown Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Nishanth Menon Cc: Matthijs van Duin Cc: Paul Walmsley Cc: Peter Ujfalusi Cc: Sakari Ailus Cc: Suman Anna Cc: Tero Kristo Cc: Tomi Valkeinen Reviewed-by: Rob Herring Signed-off-by: Tony Lindgren --- .../devicetree/bindings/bus/ti-sysc.txt | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.txt diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt new file mode 100644 index 0000000000000..fb1790e39398a --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -0,0 +1,93 @@ +Texas Instruments sysc interconnect target module wrapper binding + +Texas Instruments SoCs can have a generic interconnect target module +hardware for devices connected to various interconnects such as L3 +interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc +is mostly used for interaction between module and PRCM. It participates +in the OCP Disconnect Protocol but other than that is mostly independent +of the interconnect. + +Each interconnect target module can have one or more devices connected to +it. There is a set of control registers for managing interconnect target +module clocks, idle modes and interconnect level resets for the module. + +These control registers are sprinkled into the unused register address +space of the first child device IP block managed by the interconnect +target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. + +Required standard properties: + +- compatible shall be one of the following generic types: + + "ti,sysc-omap2" + "ti,sysc-omap4" + "ti,sysc-omap4-simple" + + or one of the following derivative types for hardware + needing special workarounds: + + "ti,sysc-omap3430-sr" + "ti,sysc-omap3630-sr" + "ti,sysc-omap4-sr" + "ti,sysc-omap3-sham" + "ti,sysc-omap-aes" + "ti,sysc-mcasp" + "ti,sysc-usb-host-fs" + +- reg shall have register areas implemented for the interconnect + target module in question such as revision, sysc and syss + +- reg-names shall contain the register names implemented for the + interconnect target module in question such as + "rev, "sysc", and "syss" + +- ranges shall contain the interconnect target module IO range + available for one or more child device IP blocks managed + by the interconnect target module, the ranges may include + multiple ranges such as device L4 range for control and + parent L3 range for DMA access + +Optional properties: + +- clocks clock specifier for each name in the clock-names as + specified in the binding documentation for ti-clkctrl, + typically available for all interconnect targets on TI SoCs + based on omap4 except if it's read-only register in hwauto + mode as for example omap4 L4_CFG_CLKCTRL + +- clock-names should contain at least "fck", and optionally also "ick" + depending on the SoC and the interconnect target module + +- ti,hwmods optional TI interconnect module name to use legacy + hwmod platform data + + +Example: Single instance of MUSB controller on omap4 using interconnect ranges +using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): + + target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ + compatible = "ti,sysc-omap2"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + + usb_otg_hs: otg@0 { + compatible = "ti,omap4-musb"; + reg = <0x0 0x7ff>; + interrupts = , + ; + usb-phy = <&usb2_phy>; + ... + }; + }; + +Note that other SoCs, such as am335x can have multipe child devices. On am335x +there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA +instance as children of a single interconnet target module. From d23a163ebe5aab85fb66fd6b1256bed34a18a269 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 10 Oct 2017 14:14:50 -0700 Subject: [PATCH 13/14] ARM: dts: Add nodes for missing omap4 interconnect target modules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On omap4 we are missing dts nodes for several interconnect target modules that we are idling on init. This currently works with the legacy platform data still around. To fix this, let's add the interconnect target modules so we can idle the unused interconnect target module on init. Also note that adding the interconnect target module node does not necessarily mean that there is a driver available for the child IP block, or that the child IP block is even functional. In the SGX case, the PowerVR driver is closed source. And McASP on omap4 has at least the TX path disabled and is not supported by the davinci-mcasp driver. For AESS there is old Android 3.4 kernel driver available. For smarflex, we are still probing with platform data and the driver needs more work before we can add the device ip child nodes. And finally, we're not yet using the interconnet ranges. I will be posting separate patches for those later on. Cc: Benoît Cousson Cc: Laurent Pinchart Cc: Liam Girdwood Cc: Mark Brown Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Nishanth Menon Cc: Matthijs van Duin Cc: Paul Walmsley Cc: Peter Ujfalusi Cc: Rob Herring Cc: Sakari Ailus Cc: Tero Kristo Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 159 ++++++++++++++++++++++++++++++++--- 1 file changed, 147 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 70ecd840772d5..f69de916b06a3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -382,6 +382,19 @@ #interrupt-cells = <2>; }; + target-module@48076000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "slimbus2"; + reg = <0x48076000 0x4>, + <0x48076010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48076000 0x001000>; + + /* No child device binding or driver in mainline */ + }; + elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0x2000>; @@ -442,25 +455,55 @@ clock-frequency = <48000000>; }; - smartreflex_iva: smartreflex@4a0db000 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0x4a0db000 0x80>; - interrupts = ; + target-module@4a0db000 { + compatible = "ti,sysc-sr"; ti,hwmods = "smartreflex_iva"; + reg = <0x4a0db000 0x4>, + <0x4a0db008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0db000 0x001000>; + + smartreflex_iva: smartreflex@0 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0 0x80>; + interrupts = ; + }; }; - smartreflex_core: smartreflex@4a0dd000 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0x4a0dd000 0x80>; - interrupts = ; + target-module@4a0dd000 { + compatible = "ti,sysc-sr"; ti,hwmods = "smartreflex_core"; + reg = <0x4a0dd000 0x4>, + <0x4a0dd008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0dd000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0 0x80>; + interrupts = ; + }; }; - smartreflex_mpu: smartreflex@4a0d9000 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0x4a0d9000 0x80>; - interrupts = ; + target-module@4a0d9000 { + compatible = "ti,sysc-sr"; ti,hwmods = "smartreflex_mpu"; + reg = <0x4a0d9000 0x4>, + <0x4a0d9008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0d9000 0x001000>; + + smartreflex_mpu: smartreflex@0 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0 0x80>; + interrupts = ; + }; }; hwspinlock: spinlock@4a0f6000 { @@ -666,6 +709,19 @@ #iommu-cells = <0>; }; + target-module@52000000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "iss"; + reg = <0x52000000 0x4>, + <0x52000010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x52000000 0x1000000>; + + /* No child device binding, driver in staging */ + }; + mmu_ipu: mmu@55082000 { compatible = "ti,omap4-iommu"; reg = <0x55082000 0x100>; @@ -760,6 +816,56 @@ status = "disabled"; }; + target-module@40128000 { + compatible = "ti,sysc-mcasp"; + ti,hwmods = "mcasp"; + reg = <0x40128004 0x4>; + reg-names = "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ + <0x49028000 0x49028000 0x1000>; /* L3 */ + + /* + * Child device unsupported by davinci-mcasp. At least + * TX path is disabled for omap4, and only DIT mode + * works with no I2S. See also old Android kernel + * omap-mcasp driver for more information. + */ + }; + + target-module@4012c000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "slimbus1"; + reg = <0x4012c000 0x4>, + <0x4012c010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ + <0x4902c000 0x4902c000 0x1000>; /* L3 */ + + /* No child device binding or driver in mainline */ + }; + + target-module@401f1000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "aess"; + reg = <0x401f1000 0x4>, + <0x401f1010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ + <0x490f1000 0x490f1000 0x1000>; /* L3 */ + + /* + * No child device binding or driver in mainline. + * See Android tree and related upstreaming efforts + * for the old driver. + */ + }; + mcbsp4: mcbsp@48096000 { compatible = "ti,omap4-mcbsp"; reg = <0x48096000 0xff>; /* L4 Interconnect */ @@ -848,6 +954,19 @@ }; }; + target-module@4a10a000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "fdif"; + reg = <0x4a10a000 0x4>, + <0x4a10a010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a10a000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + timer1: timer@4a318000 { compatible = "ti,omap3430-timer"; reg = <0x4a318000 0x80>; @@ -1063,6 +1182,22 @@ status = "disabled"; }; + target-module@56000000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "gpu"; + reg = <0x5601fc00 0x4>, + <0x5601fc10 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + dss: dss@58000000 { compatible = "ti,omap4-dss"; reg = <0x58000000 0x80>; From 160ec89ac3460c0c529582adb7fc4eb3d4f4fafa Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 10 Oct 2017 14:15:04 -0700 Subject: [PATCH 14/14] ARM: dts: Configure SmartReflex only to idle the interconnect target module The TRM has marked dra7 SmartReflex as reserved and we should not touch those registers as pointed out by Nishanth Menon . We do still want to idle the related interconnect target modules on init though. Let's do this by only configuring the generic interconnect target modules and not add the child SmartReflex devices. Cc: Lokesh Vutla Cc: Nishanth Menon Cc: Paul Walmsley Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a33023ca4390a..92b5cb40a9d51 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1497,6 +1497,32 @@ }; }; + target-module@4a0dd000 { + compatible = "ti,sysc-omap4-sr"; + ti,hwmods = "smartreflex_core"; + reg = <0x4a0dd000 0x4>, + <0x4a0dd008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0dd000 0x001000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + + target-module@4a0d9000 { + compatible = "ti,sysc-omap4-sr"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x4a0d9000 0x4>, + <0x4a0d9008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0d9000 0x001000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + omap_dwc3_1: omap_dwc3_1@48880000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1";