---

yaml
---
r: 91158
b: refs/heads/master
c: fdb72fd
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c34002c102880bfac5b449b41e5313dcda186db8
+refs/heads/master: fdb72fd84c26438a7dd754a1cc74890aca7f1b77

trunk/arch/arm/mach-iop32x/Kconfig

@@ -34,6 +34,14 @@ config MACH_N2100
 	  Say Y here if you want to run your kernel on the Thecus n2100
 	  NAS appliance.
 
+config IOP3XX_ATU
+        bool "Enable the PCI Controller"
+        default y
+        help
+          Say Y here if you want the IOP to initialize its PCI Controller.
+          Say N if the IOP is an add in card, the host system owns the PCI
+          bus in this case.
+
 config MACH_EM7210
 	bool "Enable support for the Lanner EM7210"
 	help

trunk/arch/arm/mach-iop32x/iq31244.c

@@ -178,9 +178,10 @@ static struct hw_pci iq31244_pci __initdata = {
 
 static int __init iq31244_pci_init(void)
 {
-	if (is_ep80219())
-		pci_common_init(&ep80219_pci);
-	else if (machine_is_iq31244()) {
+	if (is_ep80219()) {
+		if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
+			pci_common_init(&ep80219_pci);
+	} else if (machine_is_iq31244()) {
 		if (is_80219()) {
 			printk("note: iq31244 board type has been selected\n");
 			printk("note: to select ep80219 operation:\n");
@@ -189,7 +190,9 @@ static int __init iq31244_pci_init(void)
 			printk("\t2/ update boot loader to pass"
 				" the ep80219 id: %d\n", MACH_TYPE_EP80219);
 		}
-		pci_common_init(&iq31244_pci);
+
+		if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
+			pci_common_init(&iq31244_pci);
 	}
 
 	return 0;

trunk/arch/arm/mach-iop32x/iq80321.c

@@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = {
 	.swizzle	= pci_std_swizzle,
 	.nr_controllers = 1,
 	.setup		= iop3xx_pci_setup,
-	.preinit	= iop3xx_pci_preinit_cond,
+	.preinit	= iop3xx_pci_preinit,
 	.scan		= iop3xx_pci_scan_bus,
 	.map_irq	= iq80321_pci_map_irq,
 };

trunk/arch/arm/mach-iop33x/Kconfig

@@ -16,6 +16,14 @@ config MACH_IQ80332
 	  Say Y here if you want to run your kernel on the Intel IQ80332
 	  evaluation kit for the IOP332 chipset.
 
+config IOP3XX_ATU
+	bool "Enable the PCI Controller"
+	default y
+	help
+	  Say Y here if you want the IOP to initialize its PCI Controller.
+	  Say N if the IOP is an add in card, the host system owns the PCI
+	  bus in this case.
+
 endmenu
 
 endif

trunk/arch/arm/mach-iop33x/iq80331.c

@@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = {
 	.swizzle	= pci_std_swizzle,
 	.nr_controllers = 1,
 	.setup		= iop3xx_pci_setup,
-	.preinit	= iop3xx_pci_preinit_cond,
+	.preinit	= iop3xx_pci_preinit,
 	.scan		= iop3xx_pci_scan_bus,
 	.map_irq	= iq80331_pci_map_irq,
 };

trunk/arch/arm/mach-iop33x/iq80332.c

@@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = {
 	.swizzle	= pci_std_swizzle,
 	.nr_controllers = 1,
 	.setup		= iop3xx_pci_setup,
-	.preinit	= iop3xx_pci_preinit_cond,
+	.preinit	= iop3xx_pci_preinit,
 	.scan		= iop3xx_pci_scan_bus,
 	.map_irq	= iq80332_pci_map_irq,
 };

trunk/arch/arm/mach-ks8695/Makefile

@@ -11,5 +11,8 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)		+= pci.o
 
+# LEDs
+obj-$(CONFIG_LEDS)		+= leds.o
+
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)	+= board-micrel.o

trunk/arch/arm/mach-ks8695/devices.c

@@ -176,6 +176,27 @@ static void __init ks8695_add_device_watchdog(void) {}
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+short ks8695_leds_cpu = -1;
+short ks8695_leds_timer = -1;
+
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
+{
+	/* Enable GPIO to access the LEDs */
+	gpio_direction_output(cpu_led, 1);
+	gpio_direction_output(timer_led, 1);
+
+	ks8695_leds_cpu   = cpu_led;
+	ks8695_leds_timer = timer_led;
+}
+#else
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
 /* -------------------------------------------------------------------- */
 
 /*

trunk/arch/arm/mach-ks8695/leds.c

@@ -0,0 +1,94 @@
+/*
+ * LED driver for KS8695-based boards.
+ *
+ * Copyright (C) Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/leds.h>
+#include <asm/arch/devices.h>
+#include <asm/arch/gpio.h>
+
+
+static inline void ks8695_led_on(unsigned int led)
+{
+	gpio_set_value(led, 0);
+}
+
+static inline void ks8695_led_off(unsigned int led)
+{
+	gpio_set_value(led, 1);
+}
+
+static inline void ks8695_led_toggle(unsigned int led)
+{
+	unsigned long is_off = gpio_get_value(led);
+	if (is_off)
+		ks8695_led_on(led);
+	else
+		ks8695_led_off(led);
+}
+
+
+/*
+ * Handle LED events.
+ */
+static void ks8695_leds_event(led_event_t evt)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	switch(evt) {
+	case led_start:		/* System startup */
+		ks8695_led_on(ks8695_leds_cpu);
+		break;
+
+	case led_stop:		/* System stop / suspend */
+		ks8695_led_off(ks8695_leds_cpu);
+		break;
+
+#ifdef CONFIG_LEDS_TIMER
+	case led_timer:		/* Every 50 timer ticks */
+		ks8695_led_toggle(ks8695_leds_timer);
+		break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+	case led_idle_start:	/* Entering idle state */
+		ks8695_led_off(ks8695_leds_cpu);
+		break;
+
+	case led_idle_end:	/* Exit idle state */
+		ks8695_led_on(ks8695_leds_cpu);
+		break;
+#endif
+
+	default:
+		break;
+	}
+
+	local_irq_restore(flags);
+}
+
+
+static int __init leds_init(void)
+{
+	if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
+		return -ENODEV;
+
+	leds_event = ks8695_leds_event;
+
+	leds_event(led_start);
+	return 0;
+}
+
+__initcall(leds_init);

trunk/arch/arm/plat-iop/pci.c

@@ -24,7 +24,6 @@
 #include <asm/hardware.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/iop3xx.h>
-#include <asm/mach-types.h>
 
 // #define DEBUG
 
@@ -210,11 +209,8 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
 	res[1].flags = IORESOURCE_MEM;
 	request_resource(&iomem_resource, &res[1]);
 
-	/*
-	 * Use whatever translation is already setup.
-	 */
-	sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
-	sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
+	sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
+	sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
 
 	sys->resource[0] = &res[0];
 	sys->resource[1] = &res[1];
@@ -254,11 +250,11 @@ void __init iop3xx_atu_setup(void)
 	*IOP3XX_IATVR2 = PHYS_OFFSET;
 
 	/* Outbound window 0 */
-	*IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
+	*IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
 	*IOP3XX_OUMWTVR0 = 0;
 
 	/* Outbound window 1 */
-	*IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE;
+	*IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
 	*IOP3XX_OUMWTVR1 = 0;
 
 	/* BAR 3 ( Disabled ) */
@@ -269,7 +265,7 @@ void __init iop3xx_atu_setup(void)
 
 	/* Setup the I/O Bar
 	 */
-	*IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
+	*IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
 
 	/* Enable inbound and outbound cycles
 	 */
@@ -326,57 +322,32 @@ void __init iop3xx_atu_disable(void)
 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
 int init_atu;
 
-int iop3xx_get_init_atu(void) {
-	/* check if default has been overridden */
-	if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
-		return init_atu;
-	else
-		return IOP3XX_INIT_ATU_DISABLE;
-}
-
-static void __init iop3xx_atu_debug(void)
-{
-	DBG("PCI: Intel IOP3xx PCI init.\n");
-	DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
-		*IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
-	DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
-		*IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
-	DBG("PCI: Outbound IO window: PCI 0x%08x\n",
-		*IOP3XX_OIOWTVR);
-
-	DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
-		*IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
-	DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
-		*IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
-	DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
-		*IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
-	DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
-		*IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
-
-	DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
-		0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
-
-	DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
-	DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
-
-	hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
-}
-
-/* for platforms that might be host-bus-adapters */
-void __init iop3xx_pci_preinit_cond(void)
+void __init iop3xx_pci_preinit(void)
 {
 	if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
 		iop3xx_atu_disable();
 		iop3xx_atu_setup();
-		iop3xx_atu_debug();
 	}
-}
 
-void __init iop3xx_pci_preinit(void)
-{
-	iop3xx_atu_disable();
-	iop3xx_atu_setup();
-	iop3xx_atu_debug();
+	DBG("PCI:  Intel 803xx PCI init code.\n");
+	DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
+	DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
+			*IOP3XX_OMWTVR0,
+			*IOP3XX_OIOWTVR);
+	DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
+	DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
+			*IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
+	DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
+	DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
+			*IOP3XX_IABAR1, *IOP3XX_IALR1);
+	DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
+			*IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
+	DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
+			*IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
+	DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
+			*IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
+
+	hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
 }
 
 /* allow init_atu to be user overridden */

trunk/drivers/pci/setup-bus.c

@@ -486,7 +486,12 @@ void __ref pci_bus_size_bridges(struct pci_bus *bus)
 		break;
 
 	case PCI_CLASS_BRIDGE_PCI:
+		/* don't size subtractive decoding (transparent)
+		 * PCI-to-PCI bridges */
+		if (bus->self->transparent)
+			break;
 		pci_bridge_check_ranges(bus);
+		/* fall through */
 	default:
 		pbus_size_io(bus);
 		/* If the bridge supports prefetchable range, size it

trunk/include/asm-arm/arch-ks8695/devices.h

@@ -18,6 +18,11 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
 
+ /* LEDs */
+extern short ks8695_leds_cpu;
+extern short ks8695_leds_timer;
+extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
+
  /* PCI */
 #define KS8695_MODE_PCI		0
 #define KS8695_MODE_MINIPCI	1

trunk/include/asm-arm/hardware/iop3xx.h

@@ -29,7 +29,6 @@ extern void gpio_line_config(int line, int direction);
 extern int  gpio_line_get(int line);
 extern void gpio_line_set(int line, int value);
 extern int init_atu;
-extern int iop3xx_get_init_atu(void);
 #endif
 
 
@@ -113,6 +112,14 @@ extern int iop3xx_get_init_atu(void);
 #define IOP3XX_INIT_ATU_DISABLE -1
 #define IOP3XX_INIT_ATU_ENABLE	 1
 
+#ifdef CONFIG_IOP3XX_ATU
+#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
+				IOP3XX_INIT_ATU_ENABLE : init_atu)
+#else
+#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
+				IOP3XX_INIT_ATU_DISABLE : init_atu)
+#endif
+
 /* Messaging Unit  */
 #define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
 #define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)

trunk/include/asm-arm/mach/pci.h

@@ -55,7 +55,6 @@ void pci_common_init(struct hw_pci *);
 extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
 extern void iop3xx_pci_preinit(void);
-extern void iop3xx_pci_preinit_cond(void);
 
 extern int dc21285_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);