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yaml
---
r: 77695
b: refs/heads/master
c: cdcc970
h: refs/heads/master
i:
  77693: 1cc9d5f
  77691: 74831c8
  77687: ef16f83
  77679: 9fb8f7a
  77663: 4812d91
  77631: 8d3c7ac
  77567: 29a7615
v: v3
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Paul Mundt committed Jan 28, 2008
1 parent 7c7eeaf commit 010fc00
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Showing 6 changed files with 174 additions and 272 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 9085fa1255fc16bf0dbd217e9f4cdccf16f064d3
refs/heads/master: cdcc970829e81da3445346cb71b2ea264c9952b9
27 changes: 27 additions & 0 deletions trunk/include/asm-sh/cpu-sh5/mmu_context.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H

/* Common defines */
#define TLB_STEP 0x00000010
#define TLB_PTEH 0x00000000
#define TLB_PTEL 0x00000008

/* PTEH defines */
#define PTEH_ASID_SHIFT 2
#define PTEH_VALID 0x0000000000000001
#define PTEH_SHARED 0x0000000000000002
#define PTEH_MATCH_ASID 0x00000000000003ff

#ifndef __ASSEMBLY__
/* This has to be a common function because the next location to fill
* information is shared. */
extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);

/* Profiling counter. */
#ifdef CONFIG_SH64_PROC_TLB
extern unsigned long long calls_to_do_fast_page_fault;
#endif

#endif /* __ASSEMBLY__ */

#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
87 changes: 24 additions & 63 deletions trunk/include/asm-sh/mmu_context.h
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
/*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 - 2006 Paul Mundt
* Copyright (C) 2003 - 2007 Paul Mundt
*
* ASID handling idea taken from MIPS implementation.
*/
#ifndef __ASM_SH_MMU_CONTEXT_H
#define __ASM_SH_MMU_CONTEXT_H
#ifdef __KERNEL__

#ifdef __KERNEL__
#include <asm/cpu/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/uaccess.h>
Expand All @@ -19,7 +19,6 @@
* (a) TLB cache version (or round, cycle whatever expression you like)
* (b) ASID (Address Space IDentifier)
*/

#define MMU_CONTEXT_ASID_MASK 0x000000ff
#define MMU_CONTEXT_VERSION_MASK 0xffffff00
#define MMU_CONTEXT_FIRST_VERSION 0x00000100
Expand All @@ -28,17 +27,24 @@
/* ASID is 8-bit value, so it can't be 0x100 */
#define MMU_NO_ASID 0x100

#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & \
MMU_CONTEXT_ASID_MASK)
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
#define cpu_context(cpu, mm) ((mm)->context.id[cpu])

#define cpu_asid(cpu, mm) \
(cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)

/*
* Virtual Page Number mask
*/
#define MMU_VPN_MASK 0xfffff000

#ifdef CONFIG_MMU
#if defined(CONFIG_SUPERH32)
#include "mmu_context_32.h"
#else
#include "mmu_context_64.h"
#endif

/*
* Get MMU context if needed.
*/
Expand All @@ -59,6 +65,14 @@ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
*/
flush_tlb_all();

#ifdef CONFIG_SUPERH64
/*
* The SH-5 cache uses the ASIDs, requiring both the I and D
* cache to be flushed when the ASID is exhausted. Weak.
*/
flush_cache_all();
#endif

/*
* Fix version; Note that we avoid version #0
* to distingush NO_CONTEXT.
Expand All @@ -85,39 +99,6 @@ static inline int init_new_context(struct task_struct *tsk,
return 0;
}

/*
* Destroy context related info for an mm_struct that is about
* to be put to rest.
*/
static inline void destroy_context(struct mm_struct *mm)
{
/* Do nothing */
}

static inline void set_asid(unsigned long asid)
{
unsigned long __dummy;

__asm__ __volatile__ ("mov.l %2, %0\n\t"
"and %3, %0\n\t"
"or %1, %0\n\t"
"mov.l %0, %2"
: "=&r" (__dummy)
: "r" (asid), "m" (__m(MMU_PTEH)),
"r" (0xffffff00));
}

static inline unsigned long get_asid(void)
{
unsigned long asid;

__asm__ __volatile__ ("mov.l %1, %0"
: "=r" (asid)
: "m" (__m(MMU_PTEH)));
asid &= MMU_CONTEXT_ASID_MASK;
return asid;
}

/*
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
Expand All @@ -128,17 +109,6 @@ static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
set_asid(cpu_asid(cpu, mm));
}

/* MMU_TTB is used for optimizing the fault handling. */
static inline void set_TTB(pgd_t *pgd)
{
ctrl_outl((unsigned long)pgd, MMU_TTB);
}

static inline pgd_t *get_TTB(void)
{
return (pgd_t *)ctrl_inl(MMU_TTB);
}

static inline void switch_mm(struct mm_struct *prev,
struct mm_struct *next,
struct task_struct *tsk)
Expand All @@ -153,17 +123,7 @@ static inline void switch_mm(struct mm_struct *prev,
if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
activate_context(next, cpu);
}

#define deactivate_mm(tsk,mm) do { } while (0)

#define activate_mm(prev, next) \
switch_mm((prev),(next),NULL)

static inline void
enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
#else /* !CONFIG_MMU */
#else
#define get_mmu_context(mm) do { } while (0)
#define init_new_context(tsk,mm) (0)
#define destroy_context(mm) do { } while (0)
Expand All @@ -173,10 +133,11 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
#define get_TTB() (0)
#define activate_context(mm,cpu) do { } while (0)
#define switch_mm(prev,next,tsk) do { } while (0)
#endif /* CONFIG_MMU */

#define activate_mm(prev, next) switch_mm((prev),(next),NULL)
#define deactivate_mm(tsk,mm) do { } while (0)
#define activate_mm(prev,next) do { } while (0)
#define enter_lazy_tlb(mm,tsk) do { } while (0)
#endif /* CONFIG_MMU */

#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
/*
Expand Down
47 changes: 47 additions & 0 deletions trunk/include/asm-sh/mmu_context_32.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,47 @@
#ifndef __ASM_SH_MMU_CONTEXT_32_H
#define __ASM_SH_MMU_CONTEXT_32_H

/*
* Destroy context related info for an mm_struct that is about
* to be put to rest.
*/
static inline void destroy_context(struct mm_struct *mm)
{
/* Do nothing */
}

static inline void set_asid(unsigned long asid)
{
unsigned long __dummy;

__asm__ __volatile__ ("mov.l %2, %0\n\t"
"and %3, %0\n\t"
"or %1, %0\n\t"
"mov.l %0, %2"
: "=&r" (__dummy)
: "r" (asid), "m" (__m(MMU_PTEH)),
"r" (0xffffff00));
}

static inline unsigned long get_asid(void)
{
unsigned long asid;

__asm__ __volatile__ ("mov.l %1, %0"
: "=r" (asid)
: "m" (__m(MMU_PTEH)));
asid &= MMU_CONTEXT_ASID_MASK;
return asid;
}

/* MMU_TTB is used for optimizing the fault handling. */
static inline void set_TTB(pgd_t *pgd)
{
ctrl_outl((unsigned long)pgd, MMU_TTB);
}

static inline pgd_t *get_TTB(void)
{
return (pgd_t *)ctrl_inl(MMU_TTB);
}
#endif /* __ASM_SH_MMU_CONTEXT_32_H */
75 changes: 75 additions & 0 deletions trunk/include/asm-sh/mmu_context_64.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,75 @@
#ifndef __ASM_SH_MMU_CONTEXT_64_H
#define __ASM_SH_MMU_CONTEXT_64_H

/*
* sh64-specific mmu_context interface.
*
* Copyright (C) 2000, 2001 Paolo Alberelli
* Copyright (C) 2003 - 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <asm/cpu/registers.h>
#include <asm/cacheflush.h>

#define SR_ASID_MASK 0xffffffffff00ffffULL
#define SR_ASID_SHIFT 16

/*
* Destroy context related info for an mm_struct that is about
* to be put to rest.
*/
static inline void destroy_context(struct mm_struct *mm)
{
/* Well, at least free TLB entries */
flush_tlb_mm(mm);
}

static inline unsigned long get_asid(void)
{
unsigned long long sr;

asm volatile ("getcon " __SR ", %0\n\t"
: "=r" (sr));

sr = (sr >> SR_ASID_SHIFT) & MMU_CONTEXT_ASID_MASK;
return (unsigned long) sr;
}

/* Set ASID into SR */
static inline void set_asid(unsigned long asid)
{
unsigned long long sr, pc;

asm volatile ("getcon " __SR ", %0" : "=r" (sr));

sr = (sr & SR_ASID_MASK) | (asid << SR_ASID_SHIFT);

/*
* It is possible that this function may be inlined and so to avoid
* the assembler reporting duplicate symbols we make use of the
* gas trick of generating symbols using numerics and forward
* reference.
*/
asm volatile ("movi 1, %1\n\t"
"shlli %1, 28, %1\n\t"
"or %0, %1, %1\n\t"
"putcon %1, " __SR "\n\t"
"putcon %0, " __SSR "\n\t"
"movi 1f, %1\n\t"
"ori %1, 1 , %1\n\t"
"putcon %1, " __SPC "\n\t"
"rte\n"
"1:\n\t"
: "=r" (sr), "=r" (pc) : "0" (sr));
}

/* No spare register to twiddle, so use a software cache */
extern pgd_t *mmu_pdtp_cache;

#define set_TTB(pgd) (mmu_pdtp_cache = (pgd))
#define get_TTB() (mmu_pdtp_cache)

#endif /* __ASM_SH_MMU_CONTEXT_64_H */
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