drm/nv50: import initial clock get/set routines + hook up pm engine

This will make nouveau_pm attempt to report the card's current performance
level both during bootup, and through sysfs.

This is a very initial implementation, and can be improved a *lot*

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/Makefile

@@ -24,7 +24,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
              nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
              nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \
              nv10_gpio.o nv50_gpio.o \
-	     nv50_calc.o
+	     nv50_calc.o \
+	     nv50_pm.o
 
 nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
 nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o

drivers/gpu/drm/nouveau/nouveau_pm.h

@@ -41,4 +41,9 @@ int  nouveau_voltage_gpio_set(struct drm_device *, int voltage);
 void nouveau_perf_init(struct drm_device *);
 void nouveau_perf_fini(struct drm_device *);
 
+/* nv50_pm.c */
+int nv50_pm_clock_get(struct drm_device *, u32 id);
+void *nv50_pm_clock_pre(struct drm_device *, u32 id, int khz);
+void nv50_pm_clock_set(struct drm_device *, void *);
+
 #endif

drivers/gpu/drm/nouveau/nouveau_state.c

@@ -355,6 +355,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->gpio.get		= nv50_gpio_get;
 		engine->gpio.set		= nv50_gpio_set;
 		engine->gpio.irq_enable		= nv50_gpio_irq_enable;
+		engine->pm.clock_get		= nv50_pm_clock_get;
+		engine->pm.clock_pre		= nv50_pm_clock_pre;
+		engine->pm.clock_set		= nv50_pm_clock_set;
+		engine->pm.voltage_get		= nouveau_voltage_gpio_get;
+		engine->pm.voltage_set		= nouveau_voltage_gpio_set;
 		break;
 	case 0xC0:
 		engine->instmem.init		= nvc0_instmem_init;

drivers/gpu/drm/nouveau/nv50_pm.c

@@ -0,0 +1,126 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_pm.h"
+
+/*XXX: boards using limits 0x40 need fixing, the register layout
+ *     is correct here, but, there's some other funny magic
+ *     that modifies things, so it's not likely we'll set/read
+ *     the correct timings yet..  working on it...
+ */
+
+struct nv50_pm_state {
+	struct pll_lims pll;
+	enum pll_types type;
+	int N, M, P;
+};
+
+int
+nv50_pm_clock_get(struct drm_device *dev, u32 id)
+{
+	struct pll_lims pll;
+	int P, N, M, ret;
+	u32 reg0, reg1;
+
+	ret = get_pll_limits(dev, id, &pll);
+	if (ret)
+		return ret;
+
+	if (pll.vco2.maxfreq) {
+		reg0 = nv_rd32(dev, pll.reg + 0);
+		reg1 = nv_rd32(dev, pll.reg + 4);
+		P = (reg0 & 0x00070000) >> 16;
+		N = (reg1 & 0x0000ff00) >> 8;
+		M = (reg1 & 0x000000ff);
+
+		return ((pll.refclk * N / M) >> P);
+	}
+
+	reg0 = nv_rd32(dev, pll.reg + 4);
+	P = (reg0 & 0x003f0000) >> 16;
+	N = (reg0 & 0x0000ff00) >> 8;
+	M = (reg0 & 0x000000ff);
+	return pll.refclk * N / M / P;
+}
+
+void *
+nv50_pm_clock_pre(struct drm_device *dev, u32 id, int khz)
+{
+	struct nv50_pm_state *state;
+	int dummy, ret;
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return ERR_PTR(-ENOMEM);
+	state->type = id;
+
+	ret = get_pll_limits(dev, id, &state->pll);
+	if (ret < 0) {
+		kfree(state);
+		return ERR_PTR(ret);
+	}
+
+	ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M,
+			    &dummy, &dummy, &state->P);
+	if (ret < 0) {
+		kfree(state);
+		return ERR_PTR(ret);
+	}
+
+	return state;
+}
+
+void
+nv50_pm_clock_set(struct drm_device *dev, void *pre_state)
+{
+	struct nv50_pm_state *state = pre_state;
+	u32 reg = state->pll.reg, tmp;
+	int N = state->N;
+	int M = state->M;
+	int P = state->P;
+
+	if (state->pll.vco2.maxfreq) {
+		if (state->type == PLL_MEMORY) {
+			nv_wr32(dev, 0x100210, 0);
+			nv_wr32(dev, 0x1002dc, 1);
+		}
+
+		tmp  = nv_rd32(dev, reg + 0) & 0xfff8ffff;
+		tmp |= 0x80000000 | (P << 16);
+		nv_wr32(dev, reg + 0, tmp);
+		nv_wr32(dev, reg + 4, (N << 8) | M);
+
+		if (state->type == PLL_MEMORY) {
+			nv_wr32(dev, 0x1002dc, 0);
+			nv_wr32(dev, 0x100210, 0x80000000);
+		}
+	} else {
+		nv_wr32(dev, reg + 4, (P << 16) | (N << 8) | M);
+	}
+
+	kfree(state);
+}
+