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viafb: add support for the VX855 chipset
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Add support for a new VIA integrated graphics chipset, the VX855.

Signed-off-by: HaraldWelte <HaraldWelte@viatech.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Scott Fang <ScottFang@viatech.com.cn>
Cc: Joseph Chan <JosephChan@via.com.tw>
Cc: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Harald Welte authored and Linus Torvalds committed Sep 23, 2009
1 parent 5ff32f6 commit 0306ab1
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Showing 7 changed files with 314 additions and 69 deletions.
3 changes: 3 additions & 0 deletions drivers/video/via/chip.h
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,9 @@
#define UNICHROME_VX800 11
#define UNICHROME_VX800_DID 0x1122

#define UNICHROME_VX855 12
#define UNICHROME_VX855_DID 0x5122

/**************************************************/
/* Definition TMDS Trasmitter Information */
/**************************************************/
Expand Down
208 changes: 140 additions & 68 deletions drivers/video/via/hw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,106 +33,147 @@ static const struct pci_device_id_info pciidlist[] = {
{PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
{PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
{PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
{PCI_VIA_VENDOR_ID, UNICHROME_VX855_DID, UNICHROME_VX855},
{0, 0, 0}
};

static struct pll_map pll_value[] = {
{CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
{CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
{CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
{CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
{CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
{CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
{CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
{CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
{CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
{CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
{CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
{CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M},
{CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M},
{CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M},
{CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M},
{CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M},
{CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
{CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
{CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M},
{CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
{CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M},
{CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M},
{CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
{CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M},
{CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M},
{CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
{CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M},
{CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M},
{CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M},
{CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
{CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
{CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M},
{CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
{CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M},
{CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
{CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M},
{CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
{CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M},
{CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
CX700_25_175M, VX855_25_175M},
{CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
CX700_29_581M, VX855_29_581M},
{CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
CX700_26_880M, VX855_26_880M},
{CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
CX700_31_490M, VX855_31_490M},
{CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
CX700_31_500M, VX855_31_500M},
{CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
CX700_31_728M, VX855_31_728M},
{CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
CX700_32_668M, VX855_32_668M},
{CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
CX700_36_000M, VX855_36_000M},
{CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
CX700_40_000M, VX855_40_000M},
{CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
CX700_41_291M, VX855_41_291M},
{CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
CX700_43_163M, VX855_43_163M},
{CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
CX700_45_250M, VX855_45_250M},
{CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
CX700_46_000M, VX855_46_000M},
{CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
CX700_46_996M, VX855_46_996M},
{CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
CX700_48_000M, VX855_48_000M},
{CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
CX700_48_875M, VX855_48_875M},
{CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
CX700_49_500M, VX855_49_500M},
{CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
CX700_52_406M, VX855_52_406M},
{CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
CX700_52_977M, VX855_52_977M},
{CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
CX700_56_250M, VX855_56_250M},
{CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
CX700_60_466M, VX855_60_466M},
{CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
CX700_61_500M, VX855_61_500M},
{CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
CX700_65_000M, VX855_65_000M},
{CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
CX700_65_178M, VX855_65_178M},
{CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
CX700_66_750M, VX855_66_750M},
{CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
CX700_68_179M, VX855_68_179M},
{CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
CX700_69_924M, VX855_69_924M},
{CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
CX700_70_159M, VX855_70_159M},
{CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
CX700_72_000M, VX855_72_000M},
{CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
CX700_78_750M, VX855_78_750M},
{CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
CX700_80_136M, VX855_80_136M},
{CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
CX700_83_375M, VX855_83_375M},
{CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
CX700_83_950M, VX855_83_950M},
{CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
CX700_84_750M, VX855_84_750M},
{CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
CX700_85_860M, VX855_85_860M},
{CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
CX700_88_750M, VX855_88_750M},
{CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
CX700_94_500M, VX855_94_500M},
{CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
CX700_97_750M, VX855_97_750M},
{CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
CX700_101_000M},
CX700_101_000M, VX855_101_000M},
{CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
CX700_106_500M},
CX700_106_500M, VX855_106_500M},
{CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
CX700_108_000M},
CX700_108_000M, VX855_108_000M},
{CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
CX700_113_309M},
CX700_113_309M, VX855_113_309M},
{CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
CX700_118_840M},
CX700_118_840M, VX855_118_840M},
{CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
CX700_119_000M},
CX700_119_000M, VX855_119_000M},
{CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
CX700_121_750M},
CX700_121_750M, 0},
{CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
CX700_125_104M},
CX700_125_104M, 0},
{CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
CX700_133_308M},
CX700_133_308M, 0},
{CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
CX700_135_000M},
CX700_135_000M, VX855_135_000M},
{CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
CX700_136_700M},
CX700_136_700M, VX855_136_700M},
{CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
CX700_138_400M},
CX700_138_400M, VX855_138_400M},
{CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
CX700_146_760M},
CX700_146_760M, VX855_146_760M},
{CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
CX700_153_920M},
CX700_153_920M, VX855_153_920M},
{CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
CX700_156_000M},
CX700_156_000M, VX855_156_000M},
{CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
CX700_157_500M},
CX700_157_500M, VX855_157_500M},
{CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
CX700_162_000M},
CX700_162_000M, VX855_162_000M},
{CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
CX700_187_000M},
CX700_187_000M, VX855_187_000M},
{CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
CX700_193_295M},
CX700_193_295M, VX855_193_295M},
{CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
CX700_202_500M},
CX700_202_500M, VX855_202_500M},
{CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
CX700_204_000M},
CX700_204_000M, VX855_204_000M},
{CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
CX700_218_500M},
CX700_218_500M, VX855_218_500M},
{CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
CX700_234_000M},
CX700_234_000M, VX855_234_000M},
{CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
CX700_267_250M},
CX700_267_250M, VX855_267_250M},
{CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
CX700_297_500M},
{CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
CX700_297_500M, VX855_297_500M},
{CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
CX700_74_481M, VX855_74_481M},
{CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
CX700_172_798M},
CX700_172_798M, VX855_172_798M},
{CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
CX700_122_614M},
{CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M},
CX700_122_614M, VX855_122_614M},
{CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
CX700_74_270M, 0},
{CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
CX700_148_500M}
CX700_148_500M, VX855_148_500M}
};

static struct fifo_depth_select display_fifo_depth_reg = {
Expand Down Expand Up @@ -1219,6 +1260,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}

if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
VX855_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}

/* Set Display FIFO Depath Select */
reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
viafb_load_reg_num =
Expand Down Expand Up @@ -1350,6 +1400,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}

if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
VX855_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}

if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
/* Set Display FIFO Depath Select */
reg_value =
Expand Down Expand Up @@ -1438,6 +1497,8 @@ u32 viafb_get_clk_value(int clk)
case UNICHROME_P4M900:
case UNICHROME_VX800:
return pll_value[i].cx700_pll;
case UNICHROME_VX855:
return pll_value[i].vx855_pll;
}
}
}
Expand Down Expand Up @@ -1471,6 +1532,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
case UNICHROME_VX855:
viafb_write_reg(SR44, VIASR, CLK / 0x10000);
DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
Expand Down Expand Up @@ -1499,6 +1561,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
case UNICHROME_VX855:
viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
viafb_write_reg(SR4C, VIASR, CLK % 0x100);
Expand Down Expand Up @@ -2215,6 +2278,10 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
case UNICHROME_VX800:
viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
break;

case UNICHROME_VX855:
viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
break;
}

device_off();
Expand Down Expand Up @@ -2597,6 +2664,7 @@ static int get_fb_size_from_pci(void)
case P4M890_FUNCTION3:
case P4M900_FUNCTION3:
case VX800_FUNCTION3:
case VX855_FUNCTION3:
/*case CN750_FUNCTION3: */
outl(configid + 0xA0, (unsigned long)0xCF8);
FBSize = inl((unsigned long)0xCFC);
Expand Down Expand Up @@ -2660,6 +2728,10 @@ static int get_fb_size_from_pci(void)
VideoMemSize = (256 << 20); /*256M */
break;

case 0x00007000: /* Only on VX855/875 */
VideoMemSize = (512 << 20); /*512M */
break;

default:
VideoMemSize = (32 << 20); /*32M */
break;
Expand Down
14 changes: 14 additions & 0 deletions drivers/video/via/hw.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -324,6 +324,17 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
/* location: {CR94,0,6} */
#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128

/* For VT3409 */
#define VX855_IGA1_FIFO_MAX_DEPTH 400
#define VX855_IGA1_FIFO_THRESHOLD 320
#define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
#define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160

#define VX855_IGA2_FIFO_MAX_DEPTH 200
#define VX855_IGA2_FIFO_THRESHOLD 160
#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320

#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
#define IGA1_FIFO_THRESHOLD_REG_NUM 2
#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
Expand Down Expand Up @@ -688,6 +699,7 @@ struct pll_map {
u32 cle266_pll;
u32 k800_pll;
u32 cx700_pll;
u32 vx855_pll;
};

struct rgbLUT {
Expand Down Expand Up @@ -832,6 +844,8 @@ struct iga2_crtc_timing {
#define P4M900_FUNCTION3 0x3364
/* VT3353 chipset*/
#define VX800_FUNCTION3 0x3353
/* VT3409 chipset*/
#define VX855_FUNCTION3 0x3409

#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)

Expand Down
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