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Merge branch 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/h…
…orms/renesas into next/soc From Simon Horman, a series of SoC updates for shmobile. * 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7779: scif .irqs used SCIx_IRQ_MUXED() ARM: mach-shmobile: sh73a0: Initialise MMCIF using DT ARM: mach-shmobile: sh73a0: Minimal setup using DT ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT ARM: SH-Mobile: sh73a0: Add CPU Hotplug ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags ARM: shmobile: r8a7740: Add CPU sleep suspend ARM: shmobile: sh73a0: Add CPU sleep suspend ARM: shmobile: add function declarations for sh7372 DT helper functions ARM: sh7372: fix cache clean / invalidate order ARM: sh7372: add clock lookup entries for DT-based devices ARM: mach-shmobile: sh73a0 external IRQ wake update ARM: shmobile: sh73a0: fixup div4_clks bitmap ARM: shmobile: r8a7740: add TMU timer support ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c Signed-off-by: Olof Johansson <olof@lixom.net> Fix trivial conflict in board_bcm due to Simon resolving the same conflict with one less line of whitespace. Keeping end result common with what we already have in arm-soc. Conflicts: arch/arm/mach-bcm/board_bcm.c
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,24 @@ | ||
| /* | ||
| * Device Tree Source for the SH73A0 SoC | ||
| * | ||
| * Copyright (C) 2012 Renesas Solutions Corp. | ||
| * | ||
| * This file is licensed under the terms of the GNU General Public License | ||
| * version 2. This program is licensed "as is" without any warranty of any | ||
| * kind, whether express or implied. | ||
| */ | ||
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| /include/ "sh73a0.dtsi" | ||
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| / { | ||
| compatible = "renesas,sh73a0"; | ||
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| mmcif: mmcif@0x10010000 { | ||
| compatible = "renesas,sh-mmcif"; | ||
| reg = <0xe6bd0000 0x100>; | ||
| interrupt-parent = <&gic>; | ||
| interrupts = <0 140 0x4 | ||
| 0 141 0x4>; | ||
| reg-io-width = <4>; | ||
| }; | ||
| }; |
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| @@ -0,0 +1,93 @@ | ||
| /* | ||
| * Device Tree Source for the SH73A0 SoC | ||
| * | ||
| * Copyright (C) 2012 Renesas Solutions Corp. | ||
| * | ||
| * This file is licensed under the terms of the GNU General Public License | ||
| * version 2. This program is licensed "as is" without any warranty of any | ||
| * kind, whether express or implied. | ||
| */ | ||
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| /include/ "skeleton.dtsi" | ||
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| / { | ||
| compatible = "renesas,sh73a0"; | ||
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| cpus { | ||
| cpu@0 { | ||
| compatible = "arm,cortex-a9"; | ||
| }; | ||
| cpu@1 { | ||
| compatible = "arm,cortex-a9"; | ||
| }; | ||
| }; | ||
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| gic: interrupt-controller@f0001000 { | ||
| compatible = "arm,cortex-a9-gic"; | ||
| #interrupt-cells = <3>; | ||
| #address-cells = <1>; | ||
| interrupt-controller; | ||
| reg = <0xf0001000 0x1000>, | ||
| <0xf0000100 0x100>; | ||
| }; | ||
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| i2c0: i2c@0xe6820000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "renesas,rmobile-iic"; | ||
| reg = <0xe6820000 0x425>; | ||
| interrupt-parent = <&gic>; | ||
| interrupts = <0 167 0x4 | ||
| 0 168 0x4 | ||
| 0 169 0x4 | ||
| 0 170 0x4>; | ||
| }; | ||
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| i2c1: i2c@0xe6822000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "renesas,rmobile-iic"; | ||
| reg = <0xe6822000 0x425>; | ||
| interrupt-parent = <&gic>; | ||
| interrupts = <0 51 0x4 | ||
| 0 52 0x4 | ||
| 0 53 0x4 | ||
| 0 54 0x4>; | ||
| }; | ||
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| i2c2: i2c@0xe6824000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "renesas,rmobile-iic"; | ||
| reg = <0xe6824000 0x425>; | ||
| interrupt-parent = <&gic>; | ||
| interrupts = <0 171 0x4 | ||
| 0 172 0x4 | ||
| 0 173 0x4 | ||
| 0 174 0x4>; | ||
| }; | ||
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| i2c3: i2c@0xe6826000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "renesas,rmobile-iic"; | ||
| reg = <0xe6826000 0x425>; | ||
| interrupt-parent = <&gic>; | ||
| interrupts = <0 183 0x4 | ||
| 0 184 0x4 | ||
| 0 185 0x4 | ||
| 0 186 0x4>; | ||
| }; | ||
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| i2c4: i2c@0xe6828000 { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| compatible = "renesas,rmobile-iic"; | ||
| reg = <0xe6828000 0x425>; | ||
| interrupt-parent = <&gic>; | ||
| interrupts = <0 187 0x4 | ||
| 0 188 0x4 | ||
| 0 189 0x4 | ||
| 0 190 0x4>; | ||
| }; | ||
| }; |
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| /* | ||
| * SMP support for SoC sh73a0 | ||
| * | ||
| * Copyright (C) 2012 Bastian Hecht | ||
| * | ||
| * This program is free software; you can redistribute it and/or | ||
| * modify it under the terms of the GNU General Public License as | ||
| * published by the Free Software Foundation; either version 2 of | ||
| * the License, or (at your option) any later version. | ||
| * | ||
| * This program is distributed in the hope that it will be useful, | ||
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | ||
| * GNU General Public License for more details. | ||
| * | ||
| * You should have received a copy of the GNU General Public License | ||
| * along with this program; if not, write to the Free Software | ||
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| * MA 02111-1307 USA | ||
| */ | ||
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| #include <linux/linkage.h> | ||
| #include <linux/init.h> | ||
| #include <asm/memory.h> | ||
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| __CPUINIT | ||
| /* | ||
| * Reset vector for secondary CPUs. | ||
| * | ||
| * First we turn on L1 cache coherency for our CPU. Then we jump to | ||
| * shmobile_invalidate_start that invalidates the cache and hands over control | ||
| * to the common ARM startup code. | ||
| * This function will be mapped to address 0 by the SBAR register. | ||
| * A normal branch is out of range here so we need a long jump. We jump to | ||
| * the physical address as the MMU is still turned off. | ||
| */ | ||
| .align 12 | ||
| ENTRY(sh73a0_secondary_vector) | ||
| mrc p15, 0, r0, c0, c0, 5 @ read MIPDR | ||
| and r0, r0, #3 @ mask out cpu ID | ||
| lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits | ||
| mov r1, #0xf0000000 @ SCU base address | ||
| ldr r2, [r1, #8] @ SCU Power Status Register | ||
| mov r3, #3 | ||
| bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) | ||
| str r2, [r1, #8] @ write back | ||
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| ldr pc, 1f | ||
| 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET | ||
| ENDPROC(sh73a0_secondary_vector) |
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