---

yaml
---
r: 36587
b: refs/heads/master
c: 48388b2
h: refs/heads/master
i:
  36585: 52b7bad
  36583: 322c276
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7e9740b11529a0a69789fbe92d324f293e6266f6
+refs/heads/master: 48388b2a56ae5e0f1c422e84d536f31729469b17

trunk/arch/arm/plat-iop/Makefile

@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y			:= i2c.o pci.o setup.o
+obj-y			:= i2c.o pci.o setup.o time.o
 obj-m			:=
 obj-n			:=
 obj-			:=

trunk/arch/arm/plat-iop/time.c

@@ -0,0 +1,94 @@
+/*
+ * arch/arm/plat-iop/time.c
+ *
+ * Timer code for IOP32x and IOP33x based systems
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright 2002-2003 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/init.h>
+#include <linux/timex.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+#ifdef CONFIG_ARCH_IOP32X
+#define IRQ_IOP3XX_TIMER0	IRQ_IOP321_TIMER0
+#else
+#ifdef CONFIG_ARCH_IOP33X
+#define IRQ_IOP3XX_TIMER0	IRQ_IOP331_TIMER0
+#endif
+#endif
+
+static unsigned long ticks_per_jiffy;
+static unsigned long ticks_per_usec;
+static unsigned long next_jiffy_time;
+
+unsigned long iop3xx_gettimeoffset(void)
+{
+	unsigned long offset;
+
+	offset = next_jiffy_time - *IOP3XX_TU_TCR1;
+
+	return offset / ticks_per_usec;
+}
+
+static irqreturn_t
+iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	write_seqlock(&xtime_lock);
+
+	asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
+
+	while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
+							>= ticks_per_jiffy) {
+		timer_tick(regs);
+		next_jiffy_time -= ticks_per_jiffy;
+	}
+
+	write_sequnlock(&xtime_lock);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction iop3xx_timer_irq = {
+	.name		= "IOP3XX Timer Tick",
+	.handler	= iop3xx_timer_interrupt,
+	.flags		= IRQF_DISABLED | IRQF_TIMER,
+};
+
+void __init iop3xx_init_time(unsigned long tick_rate)
+{
+	u32 timer_ctl;
+
+	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
+	ticks_per_usec = tick_rate / 1000000;
+	next_jiffy_time = 0xffffffff;
+
+	timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED |
+			IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1;
+
+	/*
+	 * We use timer 0 for our timer interrupt, and timer 1 as
+	 * monotonic counter for tracking missed jiffies.
+	 */
+	asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
+	asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
+	asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
+	asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
+
+	setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
+}

trunk/include/asm-arm/arch-iop32x/iop321.h

@@ -233,6 +233,12 @@
 
 /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
 
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_TIMER_REG(reg)  (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
+
 #include <asm/hardware/iop3xx.h>
 
 

trunk/include/asm-arm/arch-iop33x/iop331.h

@@ -238,6 +238,12 @@
 
 /* Reserved 0x0000178c through 0x000019ff */
 
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_TIMER_REG(reg)  (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
+
 #include <asm/hardware/iop3xx.h>
 
 

trunk/include/asm-arm/hardware/iop3xx.h

@@ -81,6 +81,24 @@
 #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
 #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
 
+/* Timers  */
+#define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
+#define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
+#define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
+#define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
+#define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
+#define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
+#define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
+#define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
+#define IOP3XX_TMR_TC		0x01
+#define IOP3XX_TMR_EN		0x02
+#define IOP3XX_TMR_RELOAD	0x04
+#define IOP3XX_TMR_PRIVILEGED	0x09
+#define IOP3XX_TMR_RATIO_1_1	0x00
+#define IOP3XX_TMR_RATIO_4_1	0x10
+#define IOP3XX_TMR_RATIO_8_1	0x20
+#define IOP3XX_TMR_RATIO_16_1	0x30
+
 /* I2C bus interface unit  */
 #define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
 #define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
@@ -109,6 +127,8 @@
 
 #ifndef __ASSEMBLY__
 void iop3xx_map_io(void);
+void iop3xx_init_time(unsigned long);
+unsigned long iop3xx_gettimeoffset(void);
 
 extern struct platform_device iop3xx_i2c0_device;
 extern struct platform_device iop3xx_i2c1_device;