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yaml
---
r: 63882
b: refs/heads/master
c: d3f7eae
h: refs/heads/master
v: v3
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Andi Kleen authored and Linus Torvalds committed Aug 11, 2007
1 parent b97acd6 commit 0533632
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Showing 5 changed files with 14 additions and 9 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: d2d0251f6faa2cf341500a44310bbaa815a8a972
refs/heads/master: d3f7eae182b04997be19343a23f7009170f4f7a5
10 changes: 4 additions & 6 deletions trunk/arch/i386/kernel/apic.c
Original file line number Diff line number Diff line change
Expand Up @@ -61,8 +61,9 @@ static int enable_local_apic __initdata = 0;

/* Local APIC timer verification ok */
static int local_apic_timer_verify_ok;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
static int local_apic_timer_disabled;
/* Disable local APIC timer from the kernel commandline or via dmi quirk
or using CPU MSR check */
int local_apic_timer_disabled;
/* Local APIC timer works in C2 */
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
Expand Down Expand Up @@ -370,12 +371,9 @@ void __init setup_boot_APIC_clock(void)
long delta, deltapm;
int pm_referenced = 0;

if (boot_cpu_has(X86_FEATURE_LAPIC_TIMER_BROKEN))
local_apic_timer_disabled = 1;

/*
* The local apic timer can be disabled via the kernel
* commandline or from the test above. Register the lapic
* commandline or from the CPU detection code. Register the lapic
* timer as a dummy clock event source on SMP systems, so the
* broadcast mechanism is used. On UP systems simply ignore it.
*/
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7 changes: 6 additions & 1 deletion trunk/arch/i386/kernel/cpu/amd.c
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Expand Up @@ -3,6 +3,7 @@
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/apic.h>

#include "cpu.h"

Expand All @@ -22,6 +23,7 @@
extern void vide(void);
__asm__(".align 4\nvide: ret");

#ifdef CONFIG_X86_LOCAL_APIC
#define ENABLE_C1E_MASK 0x18000000
#define CPUID_PROCESSOR_SIGNATURE 1
#define CPUID_XFAM 0x0ff00000
Expand Down Expand Up @@ -52,6 +54,7 @@ static __cpuinit int amd_apic_timer_broken(void)
}
return 0;
}
#endif

int force_mwait __cpuinitdata;

Expand Down Expand Up @@ -282,8 +285,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
num_cache_leaves = 3;
}

#ifdef CONFIG_X86_LOCAL_APIC
if (amd_apic_timer_broken())
set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);
local_apic_timer_disabled = 1;
#endif

if (c->x86 == 0x10 && !force_mwait)
clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
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2 changes: 2 additions & 0 deletions trunk/include/asm-i386/apic.h
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Expand Up @@ -116,6 +116,8 @@ extern void enable_NMI_through_LVT0 (void * dummy);
extern int timer_over_8254;
extern int local_apic_timer_c2_ok;

extern int local_apic_timer_disabled;

#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }

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2 changes: 1 addition & 1 deletion trunk/include/asm-i386/cpufeature.h
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Expand Up @@ -79,7 +79,7 @@
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */
/* 14 free */
#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */

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