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yaml
---
r: 147400
b: refs/heads/master
c: 4b7bfd0
h: refs/heads/master
v: v3
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Robert Richter authored and Ingo Molnar committed Apr 29, 2009
1 parent 370022f commit 06a882f
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Showing 2 changed files with 5 additions and 4 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: a29aa8a7ff93e4196d558036928597e68337dd8d
refs/heads/master: 4b7bfd0d276da3a006d37e85d3cf900d7a14ae2a
7 changes: 4 additions & 3 deletions trunk/arch/x86/kernel/cpu/perf_counter.c
Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,7 @@ static u64 amd_pmu_raw_event(u64 event)
* Can only be executed on the CPU where the counter is active.
* Returns the delta events processed.
*/
static void
static u64
x86_perf_counter_update(struct perf_counter *counter,
struct hw_perf_counter *hwc, int idx)
{
Expand Down Expand Up @@ -165,6 +165,8 @@ x86_perf_counter_update(struct perf_counter *counter,

atomic64_add(delta, &counter->count);
atomic64_sub(delta, &hwc->period_left);

return new_raw_count;
}

static atomic_t num_counters;
Expand Down Expand Up @@ -785,8 +787,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
continue;
counter = cpuc->counters[idx];
hwc = &counter->hw;
x86_perf_counter_update(counter, hwc, idx);
val = atomic64_read(&hwc->prev_count);
val = x86_perf_counter_update(counter, hwc, idx);
if (val & (1ULL << (x86_pmu.counter_bits - 1)))
continue;
/* counter overflow */
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