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ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
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Now that MULTI_IRQ_HANDLER is selected by all the in-tree
GIC users, make it mandatory and remove the unused macros.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Marc Zyngier committed Nov 15, 2011
1 parent ab65be2 commit 08d33b2
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Showing 10 changed files with 2 additions and 76 deletions.
6 changes: 0 additions & 6 deletions arch/arm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -278,7 +278,6 @@ config ARCH_REALVIEW
select ARM_TIMER_SP804
select GPIO_PL061 if GPIOLIB
select NEED_MACH_MEMORY_H
select MULTI_IRQ_HANDLER
help
This enables support for ARM Ltd RealView boards.

Expand Down Expand Up @@ -311,7 +310,6 @@ config ARCH_VEXPRESS
select ICST
select PLAT_VERSATILE
select PLAT_VERSATILE_CLCD
select MULTI_IRQ_HANDLER
help
This enables support for the ARM Ltd Versatile Express boards.

Expand Down Expand Up @@ -347,7 +345,6 @@ config ARCH_HIGHBANK
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select USE_OF
select MULTI_IRQ_HANDLER
help
Support for the Calxeda Highbank SoC based boards.

Expand All @@ -366,7 +363,6 @@ config ARCH_CNS3XXX
select ARM_GIC
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
select MULTI_IRQ_HANDLER
help
Support for Cavium Networks CNS3XXX platform.

Expand Down Expand Up @@ -855,7 +851,6 @@ config ARCH_EXYNOS
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select NEED_MACH_MEMORY_H
select MULTI_IRQ_HANDLER
help
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)

Expand Down Expand Up @@ -979,7 +974,6 @@ config ARCH_ZYNQ
select ARM_AMBA
select ICST
select USE_OF
select MULTI_IRQ_HANDLER
help
Support for Xilinx Zynq ARM Cortex A9 Platform
endchoice
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1 change: 1 addition & 0 deletions arch/arm/common/Kconfig
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
config ARM_GIC
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
bool

config GIC_NON_BANKED
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4 changes: 0 additions & 4 deletions arch/arm/common/gic.c
Original file line number Diff line number Diff line change
Expand Up @@ -71,9 +71,6 @@ struct gic_chip_data {

static DEFINE_RAW_SPINLOCK(irq_controller_lock);

/* Address of GIC 0 CPU interface */
void __iomem *gic_cpu_base_addr __read_mostly;

/*
* Supported arch specific GIC irq extension.
* Default make them NULL.
Expand Down Expand Up @@ -700,7 +697,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
* For secondary GICs, skip over PPIs, too.
*/
if (gic_nr == 0) {
gic_cpu_base_addr = cpu_base;
domain->hwirq_base = 16;
if (irq_start > 0)
irq_start = (irq_start & ~31) + 16;
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60 changes: 0 additions & 60 deletions arch/arm/include/asm/hardware/entry-macro-gic.S

This file was deleted.

1 change: 0 additions & 1 deletion arch/arm/include/asm/hardware/gic.h
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,6 @@
#include <linux/irqdomain.h>
struct device_node;

extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;

void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
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2 changes: 0 additions & 2 deletions arch/arm/mach-msm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,6 @@ config ARCH_MSM8X60
select GPIO_MSM_V2
select MSM_GPIOMUX
select MSM_SCM if SMP
select MULTI_IRQ_HANDLER

config ARCH_MSM8960
bool "MSM8960"
Expand All @@ -61,7 +60,6 @@ config ARCH_MSM8960
select MSM_V2_TLMM
select MSM_GPIOMUX
select MSM_SCM if SMP
select MULTI_IRQ_HANDLER

endchoice

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1 change: 1 addition & 0 deletions arch/arm/mach-omap2/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ config ARCH_OMAP3
select ARCH_HAS_OPP
select PM_OPP if PM
select ARM_CPU_SUSPEND if PM
select MULTI_IRQ_HANDLER

config ARCH_OMAP4
bool "TI OMAP4"
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1 change: 0 additions & 1 deletion arch/arm/mach-tegra/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@ config ARCH_TEGRA_2x_SOC
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
select MULTI_IRQ_HANDLER
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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1 change: 0 additions & 1 deletion arch/arm/mach-ux500/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ config UX500_SOC_COMMON
select HAS_MTU
select ARM_ERRATA_753970
select ARM_ERRATA_754322
select MULTI_IRQ_HANDLER

menu "Ux500 SoC"

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1 change: 0 additions & 1 deletion arch/arm/plat-omap/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,6 @@ config ARCH_OMAP2PLUS
select CLKDEV_LOOKUP
select GENERIC_IRQ_CHIP
select OMAP_DM_TIMER
select MULTI_IRQ_HANDLER
help
"Systems based on OMAP2, OMAP3 or OMAP4"

Expand Down

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