sh: hw-breakpoints: Add preliminary support for SH-4A UBC.

This adds preliminary support for the SH-4A UBC to the hw-breakpoints API.
Presently only a single channel is implemented, and the ptrace interface
still needs to be converted. This is the first step to cleaning up the
long-standing UBC mess, making the UBC more generally accessible, and
finally making it SMP safe.

An additional abstraction will be layered on top of this as with the perf
events code to permit the various CPU families to wire up support for
their own specific UBCs, as many variations exist.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

arch/sh/Kconfig

@@ -39,6 +39,7 @@ config SUPERH32
 	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
 	select HAVE_FUNCTION_GRAPH_TRACER
 	select HAVE_ARCH_KGDB
+	select HAVE_HW_BREAKPOINT if CPU_SH4A
 	select ARCH_HIBERNATION_POSSIBLE if MMU
 
 config SUPERH64

arch/sh/include/asm/Kbuild

@@ -1,6 +1,8 @@
 include include/asm-generic/Kbuild.asm
 
-header-y += cachectl.h cpu-features.h
+header-y += cachectl.h
+header-y += cpu-features.h
+header-y += hw_breakpoint.h
 
 unifdef-y += unistd_32.h
 unifdef-y += unistd_64.h

arch/sh/include/asm/hw_breakpoint.h

@@ -0,0 +1,53 @@
+#ifndef __ASM_SH_HW_BREAKPOINT_H
+#define __ASM_SH_HW_BREAKPOINT_H
+
+#include <linux/kdebug.h>
+#include <linux/types.h>
+#include <asm/ubc.h>
+
+#ifdef __KERNEL__
+#define __ARCH_HW_BREAKPOINT_H
+
+struct arch_hw_breakpoint {
+	char		*name; /* Contains name of the symbol to set bkpt */
+	unsigned long	address;
+	unsigned long	asid;
+	u16		len;
+	u16		type;
+};
+
+enum {
+	SH_BREAKPOINT_READ	= (1 << 1),
+	SH_BREAKPOINT_WRITE	= (1 << 2),
+	SH_BREAKPOINT_RW	= SH_BREAKPOINT_READ | SH_BREAKPOINT_WRITE,
+
+	SH_BREAKPOINT_LEN_1	= (1 << 12),
+	SH_BREAKPOINT_LEN_2	= (1 << 13),
+	SH_BREAKPOINT_LEN_4	= SH_BREAKPOINT_LEN_1 | SH_BREAKPOINT_LEN_2,
+	SH_BREAKPOINT_LEN_8	= (1 << 14),
+};
+
+/* Total number of available UBC channels */
+#define HBP_NUM		1 /* XXX */
+
+struct perf_event;
+struct task_struct;
+struct pmu;
+
+extern int arch_check_va_in_userspace(unsigned long va, u16 hbp_len);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp,
+					 struct task_struct *tsk);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+					   unsigned long val, void *data);
+
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+void hw_breakpoint_pmu_unthrottle(struct perf_event *bp);
+
+extern void arch_fill_perf_breakpoint(struct perf_event *bp);
+
+extern struct pmu perf_ops_bp;
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_HW_BREAKPOINT_H */

arch/sh/include/asm/kdebug.h

@@ -6,6 +6,8 @@ enum die_val {
 	DIE_TRAP,
 	DIE_NMI,
 	DIE_OOPS,
+	DIE_BREAKPOINT,
+	DIE_SSTEP,
 };
 
 #endif /* __ASM_SH_KDEBUG_H */

arch/sh/include/asm/processor_32.h

@@ -14,6 +14,7 @@
 #include <asm/page.h>
 #include <asm/types.h>
 #include <asm/ptrace.h>
+#include <asm/ubc.h>
 
 /*
  * Default implementation of macro that returns current
@@ -99,8 +100,8 @@ struct thread_struct {
 	unsigned long sp;
 	unsigned long pc;
 
-	/* Hardware debugging registers */
-	unsigned long ubc_pc;
+	/* Save middle states of ptrace breakpoints */
+	struct perf_event	*ptrace_bps[NR_UBC_CHANNELS];
 
 	/* floating point info */
 	union sh_fpu_union fpu;
@@ -111,9 +112,6 @@ struct thread_struct {
 #endif
 };
 
-/* Count of active tasks with UBC settings */
-extern int ubc_usercnt;
-
 #define INIT_THREAD  {						\
 	.sp = sizeof(init_stack) + (long) &init_stack,		\
 }

arch/sh/include/asm/system.h

@@ -144,8 +144,6 @@ void per_cpu_trap_init(void);
 void default_idle(void);
 void cpu_idle_wait(void);
 
-asmlinkage void break_point_trap(void);
-
 #ifdef CONFIG_SUPERH32
 #define BUILD_TRAP_HANDLER(name)					\
 asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5,	\

arch/sh/include/asm/thread_info.h

@@ -117,6 +117,7 @@ extern void free_thread_info(struct thread_info *ti);
 #define TIF_SECCOMP		6	/* secure computing */
 #define TIF_NOTIFY_RESUME	7	/* callback before returning to user */
 #define TIF_SYSCALL_TRACEPOINT	8	/* for ftrace syscall instrumentation */
+#define TIF_DEBUG		9	/* uses UBC */
 #define TIF_USEDFPU		16	/* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG	17	/* true if poll_idle() is polling TIF_NEED_RESCHED */
 #define TIF_MEMDIE		18
@@ -131,6 +132,7 @@ extern void free_thread_info(struct thread_info *ti);
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
 #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
+#define _TIF_DEBUG		(1 << TIF_DEBUG)
 #define _TIF_USEDFPU		(1 << TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
 #define _TIF_FREEZE		(1 << TIF_FREEZE)

arch/sh/include/asm/ubc.h

@@ -10,8 +10,8 @@
  */
 #ifndef __ASM_SH_UBC_H
 #define __ASM_SH_UBC_H
-#ifdef __KERNEL__
 
+#ifdef __KERNEL__
 #include <cpu/ubc.h>
 
 /* User Break Controller */
@@ -60,6 +60,12 @@
 #define BRCR_UBDE		(1 << 0)
 #endif
 
+/*
+ * All SH parts have 2 UBC channels. I defy any hardware designer to
+ * invalidate this assertion.
+ */
+#define NR_UBC_CHANNELS		2
+
 #ifndef __ASSEMBLY__
 /* arch/sh/kernel/cpu/ubc.S */
 extern void ubc_sleep(void);

arch/sh/kernel/Makefile

@@ -36,6 +36,7 @@ obj-$(CONFIG_DUMP_CODE)		+= disassemble.o
 obj-$(CONFIG_HIBERNATION)	+= swsusp.o
 obj-$(CONFIG_DWARF_UNWINDER)	+= dwarf.o
 
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)		+= hw_breakpoint.o
 obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)	+= localtimer.o
 
 EXTRA_CFLAGS += -Werror

arch/sh/kernel/cpu/sh3/ex.S

@@ -49,7 +49,7 @@ ENTRY(exception_handling_table)
 	.long	exception_error	! reserved_instruction (filled by trap_init) /* 180 */
 	.long	exception_error	! illegal_slot_instruction (filled by trap_init) /*1A0*/
 	.long	nmi_trap_handler	/* 1C0 */	! Allow trap to debugger
-	.long	break_point_trap	/* 1E0 */
+	.long	breakpoint_trap_handler	/* 1E0 */
 
 	/*
 	 * Pad the remainder of the table out, exceptions residing in far