---

yaml
---
r: 36255
b: refs/heads/master
c: b7e108e
h: refs/heads/master
i:
  36253: bed4b6a
  36251: 09c6e36
  36247: af00eb2
  36239: afa4c25
  36223: d653080
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 298476220d1f793ca0ac6c9e5dc817e1ad3e9851
+refs/heads/master: b7e108ee63624176af85b97d4d80bef6fe099395

trunk/arch/sh/kernel/head.S

@@ -12,6 +12,17 @@
  */
 #include <linux/linkage.h>
 
+#ifdef CONFIG_CPU_SH4A
+#define SYNCO()		synco
+
+#define PREFI(label, reg)	\
+	mov.l	label, reg;	\
+	prefi	@reg
+#else
+#define SYNCO()
+#define PREFI(label, reg)
+#endif
+
 	.section	.empty_zero_page, "aw"
 ENTRY(empty_zero_page)
 	.long	1		/* MOUNT_ROOT_RDONLY */
@@ -42,18 +53,25 @@ ENTRY(_stext)
 	!			Initialize global interrupt mask
 	mov	#0, r0
 	ldc	r0, r6_bank
+
+	/*
+	 * Prefetch if possible to reduce cache miss penalty.
+	 *
+	 * We do this early on for SH-4A as a micro-optimization,
+	 * as later on we will have speculative execution enabled
+	 * and this will become less of an issue.
+	 */
+	PREFI(5f, r0)
+	PREFI(6f, r0)
+
 	!
 	mov.l	2f, r0
 	mov	r0, r15		! Set initial r15 (stack pointer)
 	mov	#0x20, r1	!
 	shll8	r1		! r1 = 8192
 	sub	r1, r0		!
 	ldc	r0, r7_bank	! ... and initial thread_info
-	!
-	!			Additional CPU initialization
-	mov.l	6f, r0
-	jsr	@r0
-	 nop
+
 	!			Clear BSS area
 	mov.l	3f, r1
 	add	#4, r1
@@ -62,6 +80,14 @@ ENTRY(_stext)
 9:	cmp/hs	r2, r1
 	bf/s	9b		! while (r1 < r2)
 	 mov.l	r0,@-r2
+
+	!			Additional CPU initialization
+	mov.l	6f, r0
+	jsr	@r0
+	 nop
+
+	SYNCO()			! Wait for pending instructions..
+
 	!			Start kernel
 	mov.l	5f, r0
 	jmp	@r0