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Merge tag 'iommu-updates-v3.4' of git://git.kernel.org/pub/scm/linux/…
…kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: "The IOMMU updates for this round are not very large patch-wise. But they contain two new IOMMU drivers for the ARM Tegra 2 and 3 platforms. Besides that there are also a few patches for the AMD IOMMU which prepare the driver for adding intr-remapping support and a couple of fixes." * tag 'iommu-updates-v3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/amd: Fix section mismatch iommu/amd: Move interrupt setup code into seperate function iommu/amd: Make sure IOMMU interrupts are re-enabled on resume iommu/amd: Fix section warning for prealloc_protection_domains iommu/amd: Don't initialize IOMMUv2 resources when not required iommu/amd: Update git-tree in MAINTAINERS iommu/tegra-gart: fix spin_unlock in map failure path iommu/amd: Fix double free of mem-region in error-path iommu/amd: Split amd_iommu_init function ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver ARM: IOMMU: Tegra20: Add iommu_ops for GART driver
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/* | ||
* IOMMU API for SMMU in Tegra30 | ||
* | ||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | ||
* | ||
* This program is free software; you can redistribute it and/or modify it | ||
* under the terms and conditions of the GNU General Public License, | ||
* version 2, as published by the Free Software Foundation. | ||
* | ||
* This program is distributed in the hope it will be useful, but WITHOUT | ||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
* more details. | ||
* | ||
* You should have received a copy of the GNU General Public License along with | ||
* this program; if not, write to the Free Software Foundation, Inc., | ||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
*/ | ||
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#ifndef MACH_SMMU_H | ||
#define MACH_SMMU_H | ||
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enum smmu_hwgrp { | ||
HWGRP_AFI, | ||
HWGRP_AVPC, | ||
HWGRP_DC, | ||
HWGRP_DCB, | ||
HWGRP_EPP, | ||
HWGRP_G2, | ||
HWGRP_HC, | ||
HWGRP_HDA, | ||
HWGRP_ISP, | ||
HWGRP_MPE, | ||
HWGRP_NV, | ||
HWGRP_NV2, | ||
HWGRP_PPCS, | ||
HWGRP_SATA, | ||
HWGRP_VDE, | ||
HWGRP_VI, | ||
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HWGRP_COUNT, | ||
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HWGRP_END = ~0, | ||
}; | ||
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#define HWG_AFI (1 << HWGRP_AFI) | ||
#define HWG_AVPC (1 << HWGRP_AVPC) | ||
#define HWG_DC (1 << HWGRP_DC) | ||
#define HWG_DCB (1 << HWGRP_DCB) | ||
#define HWG_EPP (1 << HWGRP_EPP) | ||
#define HWG_G2 (1 << HWGRP_G2) | ||
#define HWG_HC (1 << HWGRP_HC) | ||
#define HWG_HDA (1 << HWGRP_HDA) | ||
#define HWG_ISP (1 << HWGRP_ISP) | ||
#define HWG_MPE (1 << HWGRP_MPE) | ||
#define HWG_NV (1 << HWGRP_NV) | ||
#define HWG_NV2 (1 << HWGRP_NV2) | ||
#define HWG_PPCS (1 << HWGRP_PPCS) | ||
#define HWG_SATA (1 << HWGRP_SATA) | ||
#define HWG_VDE (1 << HWGRP_VDE) | ||
#define HWG_VI (1 << HWGRP_VI) | ||
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#endif /* MACH_SMMU_H */ |
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